CN212569756U

CN212569756U - Software testing system of multi-FPGA platform

Info

Publication number: CN212569756U
Application number: CN202021452597.0U
Authority: CN
Inventors: 李付庭; 盛沨; 魏一平
Original assignee: Wuxi Guoxin Microelectronics System Co ltd
Current assignee: Wuxi Guoxin Microelectronics System Co ltd
Priority date: 2020-07-21
Filing date: 2020-07-21
Publication date: 2021-02-19
Anticipated expiration: 2030-07-21

Abstract

The utility model discloses a software testing system of many FPGA platforms, relate to the test technology field, this software testing system includes the host computer, the FPGA switching platform that first FPGA chip and the net gape that links to each other and first SRIO interface formed, the second SRIO interface that connects gradually, the FPGA core processing platform that DDR3 memory and second FPGA chip formed, the net gape of FPGA switching platform is connected to the host computer, the second SRIO interface of the first SRIO interface connection FPGA core processing platform of FPGA switching platform, this entire system uses the FPGA chip as the core, it uses the giga net gape to assist again, all kinds of peripheral hardware such as DDR3 and SRIO interface, avoided the core processing platform to arouse the inconvenient problem of test because of the peripheral hardware is not enough, make entire system more nimble, adaptability is stronger, and can improve data transmission's high speed and stability.

Description

Software testing system of multi-FPGA platform

Technical Field

The utility model belongs to the technical field of the test technique and specifically relates to a software testing system of many FPGA platforms.

Background

With the progress of technology, the change brought by platformization, high speed and systematization is larger and larger, and the field of software testing is the same, so that the FPGA chip is gradually and widely applied to a testing system due to excellent processing speed and strong control capability, and a software testing system taking the FPGA chip as a core has the characteristics of stability, high speed and strong adaptability, and is gradually replacing the traditional testing scheme with low efficiency and high cost.

However, the existing software testing system using the FPGA chip as the core also has certain defects, such as insufficient flexibility due to insufficient peripheral devices, low data transmission stability, easy data loss, insufficient accuracy and reliability due to limited transmission interface speed, and the like.

SUMMERY OF THE UTILITY MODEL

The inventor of the present invention provides a software testing system of many FPGA platforms to above-mentioned problem and technical demand, the technical scheme of the utility model as follows:

a software testing system of a multi-FPGA platform comprises an upper computer, an FPGA switching platform and an FPGA core processing platform, wherein the FPGA switching platform comprises a first FPGA chip, a network port and a first SRIO interface, the network port and the first SRIO interface are respectively connected with the first FPGA chip, the FPGA core processing platform comprises a second FPGA chip, a second SRIO interface and a DDR3 memory, and the second SRIO interface, the DDR3 memory and the second FPGA chip are sequentially connected; the upper computer is connected with a network port of the FPGA switching platform, and a first SRIO interface of the FPGA switching platform is connected with a second SRIO interface of the FPGA core processing platform.

The software testing system further comprises a monitoring platform, the FPGA switching platform and/or the FPGA core processing platform are respectively provided with a plurality of monitoring interfaces, each monitoring interface is connected to a corresponding signal node inside the platform, and all monitoring interfaces of the FPGA switching platform and/or the FPGA core processing platform are connected to the monitoring platform.

The FPGA switching platform is provided with a network port data monitoring interface, and the network port data monitoring interface is connected to the first FPGA chip in the FPGA switching platform.

The technical scheme is that the FPGA core processing platform is provided with a first SRIO data monitoring interface, a second SRIO data monitoring interface, a DDR3 data monitoring interface and a data processing monitoring interface, in the FPGA core processing platform, the first SRIO data monitoring interface is connected to the input end of the second SRIO interface, the second SRIO data monitoring interface is connected to the output end of the second SRIO interface, the DDR3 data monitoring interface is connected to a signal link between the DDR3 memory and the second FPGA chip, and the data processing monitoring interface is connected to the second FPGA chip.

The further technical scheme is that the monitoring platform comprises a logic analyzer and/or an oscilloscope.

The utility model has the beneficial technical effects that:

the application discloses software testing system of many FPGA platforms, this system utilizes the net gape of FPGA switching platform to link to each other with the net gape of host computer, it links to each other to recycle the SRIO interface between FPGA switching platform and the FPGA core processing platform, whole system uses the FPGA chip as the core, be assisted with the giga net gape again, all kinds of peripheral hardware such as DDR3 and SRIO interface, avoided the core processing platform because of the peripheral hardware not enough arouse the inconvenient problem of test, make whole system more nimble, the adaptability is stronger.

And the system transmits data through a gigabit network port and an SRIO interface, stores data through a DDR3 memory, and compared with the traditional serial port transmission and FIFO storage, the system ensures the high speed and stability, so that the system can be suitable for software testing with higher speed and larger data capacity, and the data transmission efficiency is higher, thereby improving the testing efficiency and reducing the testing cost.

The test system also leads out monitoring interfaces to the monitoring platform at different nodes of the transmission link, so that the system has a monitoring function, can monitor the data transmission process and ensure the accuracy of data transmission.

Drawings

Fig. 1 is a system configuration diagram of a software test system of the present application.

Detailed Description

The following describes the embodiments of the present invention with reference to the accompanying drawings.

The application discloses software testing system of many FPGA platforms please refer to fig. 1, and this software testing system includes host computer, FPGA switching platform and FPGA core processing platform, and FPGA switching platform includes first FPGA chip, net gape, first SRIO interface, and first FPGA chip is connected respectively to net gape and first SRIO interface. The FPGA core processing platform comprises a second FPGA chip, a second SRIO interface and a DDR3 memory, wherein the second SRIO interface, the DDR3 memory and the second FPGA chip are sequentially connected. The upper computer is connected with a network port of the FPGA switching platform, and a first SRIO interface of the FPGA switching platform is connected with a second SRIO interface of the FPGA core processing platform.

The net gape of FPGA switching platform links to each other with the net gape of host computer, and the net gape adopts the giga net gape, and transmission rate has 1000Mbps, is fit for high-speed data transmission. The FPGA switching platform is connected with the FPGA core processing platform through the SRIO interface, the transmission rate of the SRIO interface is 1Gbps, and the transmission speed is improved.

The software testing system further comprises a monitoring platform, the FPGA switching platform and/or the FPGA core processing platform are respectively provided with a plurality of monitoring interfaces, each monitoring interface is connected to a corresponding signal node inside the platform, and all monitoring interfaces of the FPGA switching platform and/or the FPGA core processing platform are connected to the monitoring platform. Wherein, the monitoring platform comprises a logic analyzer and/or an oscilloscope.

In the application, the FPGA switching platform is provided with a network port data monitoring interface S1, and the network port data monitoring interface S1 is connected to the first FPGA chip in the FPGA switching platform. The FPGA core processing platform is provided with a first SRIO data monitoring interface S2, a second SRIO data monitoring interface S3, a DDR3 data monitoring interface S4 and a data processing monitoring interface S5, in the FPGA core processing platform, the first SRIO data monitoring interface S2 is connected to the input end of the second SRIO interface, the second SRIO data monitoring interface S3 is connected to the output end of the second SRIO interface, the DDR3 data monitoring interface S4 is connected to a signal link between a DDR3 memory and a second FPGA chip, and the data processing monitoring interface S5 is connected to the second FPGA chip. Therefore, in the test process, the monitoring platform can be used for monitoring the data at the relevant nodes through each monitoring interface, and the accuracy of data transmission is ensured.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and scope of the present invention are to be considered as included within the scope of the present invention.

Claims

1. The software testing system of the multiple FPGA platforms is characterized by comprising an upper computer, an FPGA switching platform and an FPGA core processing platform, wherein the FPGA switching platform comprises a first FPGA chip, a network port and a first SRIO interface, the network port and the first SRIO interface are respectively connected with the first FPGA chip, the FPGA core processing platform comprises a second FPGA chip, a second SRIO interface and a DDR3 memory, and the second SRIO interface, the DDR3 memory and the second FPGA chip are sequentially connected; the upper computer is connected with the internet access of the FPGA switching platform, and the first SRIO interface of the FPGA switching platform is connected with the second SRIO interface of the FPGA core processing platform.

2. The software testing system of claim 1, further comprising a monitoring platform, wherein the FPGA switching platform and/or the FPGA core processing platform are each provided with a plurality of monitoring interfaces, each monitoring interface is connected to a corresponding signal node inside the platform, and all monitoring interfaces of the FPGA switching platform and/or the FPGA core processing platform are connected to the monitoring platform.

3. The software testing system of claim 2, wherein the FPGA switching platform is provided with a portal data monitoring interface, the portal data monitoring interface being connected to the first FPGA chip within the FPGA switching platform.

4. The software testing system of claim 2, wherein the FPGA core processing platform is provided with a first SRIO data monitoring interface, a second SRIO data monitoring interface, a DDR3 data monitoring interface, and a data processing monitoring interface, and in the FPGA core processing platform, the first SRIO data monitoring interface is connected to an input of the second SRIO interface, the second SRIO data monitoring interface is connected to an output of the second SRIO interface, the DDR3 data monitoring interface is connected to a signal link between the DDR3 memory and the second FPGA chip, and the data processing monitoring interface is connected to the second FPGA chip.

5. The software testing system of any one of claims 2-4, wherein the monitoring platform comprises a logic analyzer and/or an oscilloscope.