CN101582011B - Serial-parallel conversion interface data acquisition method and device - Google Patents

Abstract

The embodiment of the invention relates to a serializer/deserializer (Serdes) interface data acquisition method and a device. The method comprises the following steps: acquiring Serdes interface data of predetermined quantity according to the instruction of data acquisition starting signal; stopping acquiring the Serdes interface data after finishing acquiring the Serdes interface data of predetermined quantity. The device comprises a first acquisition module and an acquisition stop module; wherein, the first acquisition module is used for acquiring the Serdes interface data of predetermined quantity according to the instruction of data acquisition starting signal; the acquisition stop module is used for stopping acquiring the Serdes interface data after finishing acquiring the Serdes interface data of predetermined quantity. The Serdes interface data acquisition method and device, provided by the embodiment of the invention, can acquire the Serdes interface data of predetermined quantity according to the instruction of data acquisition starting signal, thereby quickly positioning the problems of the Serdes interface and ensuring to quickly isolate and solve the problem of the Serdes interface by analyzing the acquired Serdes interface data.

Description

Serial-parallel conversion interface data acquisition method and device

technical field

The invention relates to communication technology, in particular to a serial-to-parallel conversion interface data acquisition method and device.

Background technique

With the rapid development of science and technology, the number of chips on a single board is increasing, and the chips communicate with each other. In general, multiple ASICs (Application Specific Integrated Circuits, hereinafter referred to as ASIC) are connected through an interface switching chip or an interface Field Programmable Gate Array (Field Programmable Gate Array). If high-speed communication is performed between multiple ASICs, a serializer/deserializer (Serdes for short) needs to be added to the high-speed interface, and the high-speed interface with Serdes added is called a Serdes interface.

When the board is started or reset, the Serdes interface is prone to abnormal conditions. However, since the Serdes interface is located inside the ASIC, when an exception occurs on the Serdes interface, the outside world cannot locate the problem of the Serdes interface.

Contents of the invention

Embodiments of the present invention provide a serial-to-parallel conversion interface data collection method and device, which are used to collect Serdes interface data, so as to quickly locate the problem of the Serdes interface.

An embodiment of the present invention provides a serial-to-parallel conversion interface data collection method, including:

According to the indication of the data collection start signal, collect a preset number of serial-to-parallel conversion interface data;

After the preset number of serial-to-parallel conversion interface data collection ends, stop collecting serial-to-parallel conversion interface data.

The embodiment of the present invention also provides a serial-to-parallel conversion interface data acquisition device, including:

The first collection module is used to collect a preset number of serial-to-parallel conversion interface data according to the indication of the data collection start signal;

The stop collection module is configured to stop collecting serial-to-parallel conversion interface data after the preset number of serial-to-parallel conversion interface data collections is completed.

The serial-to-parallel conversion interface data acquisition method and device provided by the embodiments of the present invention collect a preset number of Serdes interface data according to the indication of the data acquisition start signal, so that the problem of the Serdes interface can be quickly located by analyzing the collected Serdes interface data. Ensure fast isolation and resolution of Serdes interface issues.

Description of drawings

Fig. 1 is the flowchart of the first embodiment of the Serdes interface data acquisition method of the present invention;

Fig. 2 is the flowchart of the second embodiment of the Serdes interface data collection method of the present invention;

Fig. 3 is the flowchart of the second embodiment of the Serdes interface data acquisition method of the present invention;

Fig. 4 is the structural representation of the first embodiment of the Serdes interface data acquisition device of the present invention;

Fig. 5 is the structural representation of the second embodiment of the Serdes interface data acquisition device of the present invention;

Fig. 6 is a schematic structural diagram of the third embodiment of the Serdes interface data acquisition device of the present invention.

Detailed ways

The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

As shown in Figure 1, it is a flow chart of the first embodiment of the Serdes interface data acquisition method of the present invention, which may specifically include the following steps:

Step 11, the acquisition circuit collects a preset number of Serdes interface data according to the indication of the data acquisition start signal;

Specifically, the collection circuit is a hardware logic circuit arranged on the Serdes interface and independent of the Serdes interface logic circuit, which can collect Serdes interface data. The indication of the data acquisition start signal can be sent by an external processor, or when the Serdes interface logic circuit finds that the Serdes interface is abnormal, for example, loss of signal (Loss of signal, hereinafter referred to as: LOS), coding error, phase-locked loop (Phase-locked Loop, hereinafter referred to as: PLL) loss of lock, 10 ms BFN frame exception, asynchronous First In First Out (hereinafter referred to as: FIFO), etc., are sent by the Serdes interface logic circuit, which trigger method is used , selected by the external processor. In addition, the preset number can be flexibly set according to different application scenarios.

Step 12, after the preset number of Serdes interface data collection ends, the acquisition circuit stops collecting Serdes interface data;

Specifically, after the Serdes interface circuit stops collecting Serdes interface data, it may output a collection end flag until the external processor starts up again and returns to the state to be collected. Then technicians can analyze the collected Serdes interface data to locate the problem of the Serdes interface.

In this embodiment, the sampling circuit collects a preset amount of Serdes interface data under the instruction of the data acquisition start signal, so that the problem of the Serdes interface can be quickly located by analyzing and collecting the Serdes interface data, and the problem of the Serdes interface can be quickly isolated and solved.

As shown in FIG. 2 , it is a flowchart of the second embodiment of the Serdes interface data acquisition method of the present invention. In this embodiment, a register is provided in the acquisition circuit, for example, a data acquisition status register. The data acquisition status register may include a trigger condition identification bit, and the external processor may configure the trigger condition identification bit to determine whether the output acquisition start signal is sent by the external processor or by the Serdes interface logic circuit. In addition, the data acquisition status register can also include a data acquisition direction bit, and the external processor configures the data acquisition direction bit to configure whether the data acquisition direction is the receiving direction or the sending direction, for example: when the data acquisition direction bit is configured as 1, Indicates that the direction of data collection is the receiving direction. When the data collection direction bit is configured as 0, it indicates that the direction of data collection is the sending direction. When collecting the Serdes interface data of the receiving direction, the 10 millisecond BFN frame of the sending end is used to collect the Serdes of the sending direction. For interface data, local 10ms BFN frames are used. It should be noted that, during specific implementation, different identification bits may also be implemented by different registers.

In this embodiment, the external processor configures the trigger condition identification bit as an abnormal trigger, and the data acquisition start signal is specifically an abnormal indication signal sent by the logic circuit of the Serdes interface, so as to collect service data (for example: voice service data) transmitted by the Serdes interface. ). During specific implementation, the data acquisition status register may also include an abnormal trigger cause bit, and the acquisition circuit may set the abnormal trigger cause bit to a preset value corresponding to the abnormal situation, for example: when the abnormal situation may be a Serdes interface coding error, The acquisition circuit sets the abnormal trigger cause bit to 00, and when the abnormal situation may be LOS on the Serdes interface, the acquisition circuit sets the abnormal trigger cause bit to 01. On the basis of the previous embodiment, step 11 may specifically be:

Step 21, the acquisition circuit starts from the frame header of the next 10 millisecond frame number counter (NodeB Frame Number Counter, hereinafter referred to as: BFN) frame after receiving the abnormal indication signal sent by the Serdes interface logic circuit, and collects a preset number of Serdes interfaces data;

Specifically, after the Serdes interface logic circuit detects that the Serdes interface is abnormal, it sends an abnormality indication signal to the acquisition circuit. Optionally, the Serdes interface logic circuit can also detect that the Serdes interface is abnormal, after several BFN frame periods, if after the several BFN frame periods, the Serdes interface still has an abnormality, send an abnormal indication signal to the acquisition circuit , to ensure that the collection circuit can collect the Serdes interface data after the Serdes interface is abnormal, and prevent wrong collection due to the short-term abnormality of the Serdes interface. In addition, the preset number can be freely set according to actual needs, for example: the preset number is N, and N is a positive integer greater than or equal to 1.

On the basis of the previous embodiment, the following steps may also be included after step 12:

Step 23, the acquisition circuit saves a preset number of Serdes interface data;

Specifically, a random-access memory (Random-access Memory, hereinafter referred to as: RAM) can be set inside the acquisition circuit. The RAM does not affect normal data. When the control read-write switch of the RAM is turned on, the collected Serdes interface Data is stored in this RAM in a circular overlay.

In this embodiment, after step 23, the following steps may also be included:

Step 24, the acquisition circuit outputs a data acquisition end signal.

In this embodiment, the data collection signal may specifically be a data collection end interrupt signal, and step 24 may specifically include the following steps:

Step 241, the acquisition circuit sends a data acquisition end interrupt signal to the internal processor, so that the internal processor sends the preset number of serial-to-parallel conversion interface data saved by the acquisition circuit to the external processor;

The internal processor knows that the acquisition circuit has completed data acquisition according to the data acquisition end interrupt signal, and sends the Serdes interface data stored in the RAM to the external processor, and the external processor can obtain N frames of data after the Serdes interface is abnormal. Optionally, the acquisition circuit can also directly send the data acquisition end interrupt signal to the external processor, and the external processor knows that the acquisition circuit has completed data acquisition according to the data acquisition end interrupt signal, and directly obtains the collected Serdes interface data from the RAM . The technician can correspond the Serdes interface data with the abnormal cause identified by the abnormal cause bit in the data acquisition status register. If the characteristics of the data conform to the corresponding abnormal cause, it can be determined that a corresponding abnormal situation has occurred in the Serdes interface logic circuit. Otherwise, continue to analyze the data to find the problem, so as to quickly locate the problem of the Serdes interface.

In this embodiment, when the acquisition circuit receives the abnormal indication signal sent by the Serdes interface logic circuit after detecting the occurrence of the Serdes interface, it collects a preset number of Serdes interface data after the Serdes interface is abnormal, and then the acquisition circuit saves the preset number of data. Serdes interface data, after the acquisition is completed, the acquisition circuit sends a data acquisition end interrupt signal to the internal processor, and the internal processor sends the preset number of Serdes interface data collected by the acquisition circuit to the external processor, so that the collected Serdes interface data can The data quickly locates the problem of the Serdes interface.

As shown in FIG. 3 , it is a flow chart of the second embodiment of the Serdes interface data acquisition method of the present invention. The difference from the technical solution shown in FIG. 1 is that the acquisition circuit provides a register, such as a data acquisition status register. The data acquisition status register includes a trigger condition identification, and the external processor can configure the trigger condition identification bit to determine whether the data acquisition start signal is sent by the external processor or by the Serdes interface logic circuit. In this embodiment, the external processor configures the trigger condition identifier in the data acquisition status register as a data acquisition start signal sent by the external processor, so that the external processor can collect Serdes interface data as required and provide debugging means for the Serdes interface. On the basis of the technical solution shown in Figure 1, the data acquisition start signal can specifically be a data acquisition trigger signal sent by an external processor, and step 11 can specifically be:

Step 31, the acquisition circuit collects a preset amount of Serdes interface data starting from the frame header of the next 10 millisecond BFN frame after receiving the data acquisition trigger signal sent by the external processor.

Specifically, when the external processor needs to debug the Serdes interface, it sends a data acquisition trigger signal to the acquisition circuit, and then the acquisition circuit starts to collect a preset number of Serdes interface data, and stores the collected Serdes interface data into the RAM. In addition, the preset number can be freely set according to the actual situation. For example, if it is set to M, and M is a positive integer greater than or equal to 1, after the acquisition circuit receives the data acquisition trigger signal sent by the external processor, it will start from the next 10 milliseconds Start with the frame header of the BFN frame, collect M frames of Serdes interface data, and then stop collecting data.

On the basis of the previous embodiment, after step 12, the following steps may also be included:

Step 33, the acquisition circuit saves a preset number of Serdes interface data;

Specifically, a RAM can be set inside the acquisition circuit, and the RAM does not affect normal data. When the control read-write switch of the RAM is turned on, the collected Serdes interface data is stored in the RAM in a cyclic overlay mode.

In this embodiment, after step 33, the following steps may also be included:

Step 34, the acquisition circuit outputs a data acquisition end signal.

In this embodiment, the collection end signal may specifically be a data collection end flag in the data collection status register.

Specifically, the data acquisition status register may include a data acquisition status identifier. During the process of acquiring Serdes interface data, the acquisition circuit sets the data acquisition status identifier as the data acquisition in progress identifier. After the acquisition is completed, the acquisition circuit identifies the data acquisition status as Set to mark the end of data collection. Step 34 specifically may include the following steps:

Step 341, the acquisition circuit sets the data acquisition status identifier in the data acquisition status register as the data acquisition end identifier, so that after the external processor inquires the data acquisition end identifier, it can obtain a preset number of serial-to-parallel conversion interface data saved by the acquisition circuit;

Then, the external processor regularly inquires about the data acquisition status identifier in the data acquisition status register, and when the data acquisition status identifier is inquired as the data acquisition end identifier, the external processor knows that the acquisition circuit has stopped collecting data according to the data acquisition end identifier, Then the external processor reads the preset amount of data collected by the acquisition circuit from the RAM. Technicians can compare the collected Serdes interface data with the test data. If the Serdes interface is abnormal after comparison, they can quickly locate the problem of the Serdes interface based on the collected Serdes interface data.

In this embodiment, the external processor instructs the acquisition circuit to collect a preset amount of Serdes interface data as needed, and if an abnormality occurs on the Serdes interface, the problem of the Serdes interface can be quickly located according to the Serdes interface data.

As shown in FIG. 4 , it is a schematic structural diagram of the first embodiment of the Serdes interface data collection device of the present invention, which may specifically include a first collection module 41 and a stop collection module 42 .

Wherein, the first collection module 41 is used to collect a preset number of Serdes interface data according to the indication of the data collection start signal;

The Serdes interface data acquisition device is a hardware logic circuit arranged on the Serdes interface and independent from the Serdes interface logic circuit. The indication of the data acquisition start signal can be sent by an external processor, or when the logic circuit of the Serdes interface finds that the Serdes interface is abnormal, such as LOS, encoding error, PLL out of lock, 10 ms BFN frame exception, asynchronous FIFO, etc., It is sent by the Serdes interface logic circuit, and the specific trigger mode is selected by the external processor. In addition, the preset number can be flexibly set according to different application scenarios.

The stop collection module 42 is used to stop collecting the Serdes interface data after the preset number of Serdes interface data collection ends;

Specifically, after the Serdes interface circuit stops collecting Serdes interface data, it may output a collection end flag until the external processor starts up again and returns to the state to be collected.

In this embodiment, the first acquisition module 41 collects a preset number of Serdes interface data under the instruction of the data acquisition start signal, and technicians can quickly locate the problem of the Serdes interface by analyzing and collecting the Serdes interface data to ensure rapid isolation and resolution. Serdes interface problem.

As shown in Figure 5, it is a schematic structural diagram of the second embodiment of the Serdes interface data acquisition device of the present invention. The difference from the structural schematic diagram shown in Figure 4 is that this embodiment can also include a register 50, and the register 50 can specifically be , for example: data acquisition status register. The data acquisition status register may include a trigger condition identification bit, and the external processor may configure the trigger condition identification bit to determine whether the output acquisition start signal is sent by the external processor or by the Serdes interface logic circuit. In addition, the data acquisition status register can also include a data acquisition direction bit, and the external processor configures the data acquisition direction bit to configure whether the data acquisition direction is the receiving direction or the sending direction, for example: when the data acquisition direction bit is configured as 1, Indicates that the direction of data collection is the receiving direction. When the data collection direction bit is configured as 0, it indicates that the direction of data collection is the sending direction. When collecting the Serdes interface data of the receiving direction, the 10 millisecond BFN frame of the sending end is used to collect the Serdes of the sending direction. For interface data, the local 10 ms BFN frame is used. It should be noted that, during specific implementation, different identification bits may also be implemented by different registers.

In this embodiment, the register 50 configures the data collection start signal as an abnormal indication signal sent by the logic circuit of the Serdes interface, so as to collect service data (eg, voice service data) transmitted by the Serdes interface. On the basis of the structural diagram shown in FIG. 4 , the first collection module 41 may specifically include a first receiving unit 52 , a first counter 53 and a first collection unit 54 .

Wherein, the first receiving unit 52 is used for receiving the abnormal indication signal sent by the Serdes interface logic circuit.

Specifically, after the Serdes interface logic circuit detects that the Serdes interface is abnormal, it sends an abnormality indication signal to the Serdes interface data acquisition device. Optionally, the Serdes interface logic circuit can also detect that after the Serdes interface is abnormal, after several BFN frame periods, if after the several BFN frame periods, the Serdes interface still has an abnormality, it sends to the Serdes interface data acquisition device Abnormal indication signal to ensure that the Serdes interface data acquisition device can collect the Serdes interface data after the Serdes interface is abnormal, and prevent wrong collection due to the short-term abnormality of the Serdes interface.

The first counter 53 is used to set a preset number.

The preset number can be freely set according to actual needs, for example: the preset number is N, and N is a positive integer greater than or equal to 1;

The first collecting unit 54 is configured to collect a preset amount of Serdes interface data starting from the frame header of the next 10 millisecond BFN frame after the first receiving unit 52 receives the abnormal indication signal.

This embodiment may further include a storage module 51 configured to store a preset amount of Serdes interface data collected by the first collection unit 54 .

Specifically, the storage module 51 is a RAM, and the RAM does not affect normal data. When the control read-write switch of the RAM is turned on, the Serdes interface data collected by the first acquisition unit 54 is stored in the RAM in a cyclic overlay mode. .

On the basis of the structural diagram shown in FIG. 4 , this embodiment may further include an output module 55 for outputting a data collection end signal. In this embodiment, the data collection end signal may specifically be a data collection end interrupt signal, and the output module 55 may specifically include a sending unit 56 for sending a data collection end interrupt signal to an internal processor, so that the internal processor will store the module 51 and send the preset number of serial-to-parallel conversion interface data saved to the external processor.

Specifically, the internal processor knows that the Serdes interface data acquisition device has completed data acquisition according to the data acquisition end interrupt signal, and sends the N frames of data stored in the RAM after the Serdes interface abnormality occurs to the external processor, so that the Serdes interface occurrence can be obtained. N frames of data after the exception.

Optionally, the sending unit 56 can also directly send the data collection end interrupt signal to the external processor, and the external processor knows that the Serdes interface data collection device has completed data collection according to the data collection end interrupt signal, and directly receives the data from the storage module 51. Obtain the collected Serdes interface data.

Correspond the N frames of data after the Serdes interface is abnormal to the abnormal cause identified by the abnormal cause bit in the data acquisition status register. If the characteristics of these data conform to the corresponding abnormal cause, it can be determined that the corresponding abnormal occurred in the Serdes interface logic circuit Otherwise, continue to analyze the data to find the problem, so as to quickly locate the problem of the Serdes interface.

In addition, after this data collection finishes, the first acquisition unit 54 no longer collects Serdes interface data, until the external processor restarts the Serdes interface data acquisition device and gets back to the state to be collected, the first acquisition unit 54 continues to collect Serdes interface data again .

In this embodiment, when the first receiving unit 52 receives the abnormal indication signal sent by the Serdes interface logic circuit after detecting that the Serdes interface occurs, the first acquisition unit 54 collects the preset number of Serdes interface data after the Serdes interface is abnormal, and then The storage module 51 saves the preset quantity of Serdes interface data. After the collection is completed, the sending unit 56 sends a data collection end interrupt signal to the internal processor, and the internal processor sends the preset quantity of Serdes interface data collected by the first collection unit 54. to the external processor, so that the problem of the Serdes interface can be quickly located according to the collected Serdes interface data.

As shown in Figure 6, it is a schematic structural diagram of the third embodiment of the Serdes interface data acquisition device of the present invention. The difference from the structural schematic diagram shown in Figure 4 is that this embodiment can also include a register 50, for example: data acquisition status register. The data acquisition status register includes a trigger condition identification, and the external processor can configure the trigger condition identification bit to determine whether the data acquisition start signal is sent by the external processor or by the Serdes interface logic circuit. In this embodiment, the register 50 configures the data collection start signal as a data collection trigger signal sent by the external processor, so that the external processor collects Serdes interface data as needed and provides debugging means for the Serdes interface.

On the basis of the structural diagram shown in FIG. 4 , the first collection module 41 may specifically include a second receiving unit 61 , a second counter 62 and a second collection unit 63 .

Wherein, the second receiving unit 61 is configured to receive a data collection trigger signal sent by an external processor. Specifically, when the external processor needs to debug the Serdes interface, it sends a data acquisition trigger signal to the Serdes interface data acquisition device,

The second counter 62 is used to set a preset number.

The second collection unit 63 is configured to collect the preset number of Serdes interface data set by the second counter 62 starting from the frame header of the next 10 millisecond BFN frame after the second receiving unit 61 receives the data collection trigger signal.

This preset number can be freely set according to actual conditions, for example: set to M, then after the second receiving unit 61 receives the data acquisition trigger signal sent by the external processor, the second acquisition unit 63 starts from the frame of the next 10 millisecond BFN frame Start at the beginning, collect M frames of Serdes interface data, and then stop the collection module 42 to stop collecting data.

The difference from the structural diagram shown in FIG. 4 is that this embodiment may further include a storage module 51 for storing a preset amount of Serdes interface data.

Specifically, the storage module 51 can be a RAM, and the RAM does not affect normal data. When the control read/write switch of the RAM is turned on, the collected Serdes interface data is stored in the RAM in a cyclic overlay mode.

On the basis of the structural diagram shown in FIG. 4 , this embodiment may further include an output module 55 for outputting a data collection end signal. In this embodiment, the collection end signal may specifically be the data collection end flag in the register 50, and the output module 55 may specifically include a setting unit 64 for setting the data collection status flag in the register 50 as the data collection end flag.

Specifically, the register 50 may include a data collection status identifier. During the process of collecting Serdes interface data by the second acquisition unit 63, the setting unit 64 sets the data acquisition status identifier as the data collection in-process identifier. After the collection is completed, the setting unit 64 sets the The data collection status flag is set as the data collection end flag.

Then, the external processor regularly inquires about the data collection status mark in the register 50. When the data collection state mark is inquired as the data collection end mark, the external processor knows that the Serdes interface data collection device has stopped collecting data, so it reads the data from the RAM. Get the preset amount of data collected by the Serdes interface data acquisition device. Then, compare the collected Serdes interface data with the test data. If it is judged that the Serdes interface is abnormal after comparison, the problem of the Serdes interface can be quickly located according to the collected Serdes interface data.

In this embodiment, the second receiving unit 61 receives the data acquisition trigger signal sent by the external processor according to the needs, and the second acquisition unit 63 collects a preset number of Serdes interface data, so that if the Serdes interface is abnormal, the Serdes interface data can be quickly Locate the problem with the Serdes interface.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention without limitation, although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be Modifications or equivalent replacements can be made without departing from the spirit and scope of the technical solutions of the present invention.

Claims (6)

1. A data acquisition method of a serial-parallel conversion interface is characterized by comprising the following steps:

acquiring serial-parallel conversion interface data of a preset quantity according to the indication of the data acquisition starting signal;

stopping collecting the serial-parallel conversion interface data after the collection of the serial-parallel conversion interface data of the preset number is finished;

after the serial-parallel conversion interface data of the preset number are stored, outputting a data acquisition ending signal;

the data acquisition ending signal is specifically a data acquisition ending interrupt signal; the output data acquisition end signal specifically comprises: sending a data acquisition ending interrupt signal to the internal processor so that the internal processor sends the stored serial-parallel conversion interface data with the preset number to the external processor; or,

the data acquisition ending signal is specifically a data acquisition ending identifier; the output data acquisition end signal specifically comprises: and setting the data acquisition state identifier in the data acquisition state register as a data acquisition end identifier so that the external processor can acquire the stored serial-parallel conversion interface data with the preset quantity after inquiring the data acquisition end identifier.

2. The method according to claim 1, wherein the data acquisition start signal is specifically an abnormality indication signal sent by a serial-to-parallel conversion interface logic circuit;

the method for acquiring the serial-parallel conversion interface data of the preset number according to the indication of the data acquisition starting signal specifically comprises the following steps:

and collecting the serial-parallel conversion interface data with preset quantity from the frame head of the next 10-millisecond frame number counter frame after receiving the abnormal indication signal sent by the serial-parallel conversion interface logic circuit.

3. The method according to claim 1, characterized in that the data acquisition initiation signal is in particular a data acquisition trigger signal sent by an external processor;

the method for acquiring the serial-parallel conversion interface data of the preset number according to the indication of the data acquisition starting signal specifically comprises the following steps:

and acquiring the serial-parallel conversion interface data with a preset quantity from the frame head of the next 10-millisecond frame number counter frame after receiving the data acquisition trigger signal sent by the external processor.

4. A serial-to-parallel conversion interface data acquisition device, comprising:

the first acquisition module is used for acquiring serial-parallel conversion interface data of a preset number according to the indication of the data acquisition starting signal;

the acquisition stopping module is used for stopping acquiring the serial-parallel conversion interface data after the acquisition of the preset number of the serial-parallel conversion interface data is finished;

the storage module is used for storing the serial-parallel conversion interface data with the preset quantity;

the output module is used for outputting a data acquisition ending signal;

the data acquisition ending signal is specifically a data acquisition ending interrupt signal; the output module includes: the sending unit is used for sending the data acquisition ending interrupt signal to the internal processor so that the internal processor sends the serial-parallel conversion interface data of the preset number stored by the storage module to the external processor; or,

the data acquisition ending signal is specifically a data acquisition ending identifier in a register; the output module includes: and the setting unit is used for setting the data acquisition state identifier in the register as the data acquisition ending identifier so as to obtain the serial-parallel conversion interface data of the preset quantity stored by the storage module after the external processor inquires the data acquisition ending identifier.

5. The apparatus of claim 4,

the register is used for configuring the data acquisition starting signal into an abnormal indicating signal sent by a serial-parallel conversion interface logic circuit;

the first acquisition module comprises:

the first receiving unit is used for receiving an abnormal indication signal sent by the serial-parallel conversion interface logic circuit;

a first counter for setting the preset number;

and the first acquisition unit is used for acquiring the serial-parallel conversion interface data of the preset quantity at the beginning of the frame header of the next 10-millisecond frame number counter frame after the first receiving unit receives the abnormal indication signal.

6. The apparatus of claim 4,

the register is used for configuring the data acquisition starting signal into a data acquisition triggering signal sent by an external processor;

the first acquisition module comprises:

the second receiving unit is used for receiving the data acquisition trigger signal sent by the external processor;

a second counter for setting the preset number;

and the second acquisition unit is used for acquiring the serial-parallel conversion interface data with the preset quantity from the frame header of the next 10-millisecond frame number counter frame after the second receiving unit receives the data acquisition trigger signal.

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