CN101582011B - Serializer/deserializer (Serdes) interface data acquisition method and device - Google Patents
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Abstract
The embodiment of the invention relates to a serializer/deserializer (Serdes) interface data acquisition method and a device. The method comprises the following steps: acquiring Serdes interface data of predetermined quantity according to the instruction of data acquisition starting signal; stopping acquiring the Serdes interface data after finishing acquiring the Serdes interface data of predetermined quantity. The device comprises a first acquisition module and an acquisition stop module; wherein, the first acquisition module is used for acquiring the Serdes interface data of predetermined quantity according to the instruction of data acquisition starting signal; the acquisition stop module is used for stopping acquiring the Serdes interface data after finishing acquiring the Serdes interface data of predetermined quantity. The Serdes interface data acquisition method and device, provided by the embodiment of the invention, can acquire the Serdes interface data of predetermined quantity according to the instruction of data acquisition starting signal, thereby quickly positioning the problems of the Serdes interface and ensuring to quickly isolate and solve the problem of the Serdes interface by analyzing the acquired Serdes interface data.
Description
Technical Field
The invention relates to a communication technology, in particular to a method and a device for acquiring serial-parallel conversion interface data.
Background
With the rapid development of science and technology, the number of chips on a single board is more and more, and the chips are communicated with each other. Typically, a plurality of Application Specific Integrated Circuits (ASICs) are connected via an interface switch chip or an interface Field Programmable Gate Array (Field Programmable Gate Array). When high-speed communication is performed between ASICs, a serial-to-parallel converter (Serdes) needs to be added to a high-speed interface, and the Serdes-added high-speed interface is called a Serdes interface.
When the single board is started or reset, the Serdes interface is easy to have abnormal conditions. However, since the Serdes interface is located inside the ASIC, when the Serdes interface is abnormal, the problem that the Serdes interface cannot be located by the outside world is.
Disclosure of Invention
The embodiment of the invention provides a method and a device for acquiring serial-parallel conversion interface data, which are used for acquiring Serdes interface data so as to quickly position the Serdes interface.
The embodiment of the invention provides a data acquisition method for a serial-parallel conversion interface, which comprises the following steps:
acquiring serial-parallel conversion interface data of a preset quantity according to the indication of the data acquisition starting signal;
and stopping collecting the serial-parallel conversion interface data after the collection of the serial-parallel conversion interface data of the preset number is finished.
The embodiment of the present invention further provides a serial-parallel conversion interface data acquisition apparatus, including:
the first acquisition module is used for acquiring serial-parallel conversion interface data of a preset number according to the indication of the data acquisition starting signal;
and the acquisition stopping module is used for stopping acquiring the serial-parallel conversion interface data after the acquisition of the preset number of the serial-parallel conversion interface data is finished.
According to the method and the device for acquiring the data of the serial-parallel conversion interface, provided by the embodiment of the invention, the Serdes interface data with the preset quantity are acquired according to the indication of the data acquisition starting signal, so that the problem of the Serdes interface can be quickly positioned by analyzing the acquired Serdes interface data, and the Serdes interface can be quickly isolated and solved.
Drawings
FIG. 1 is a flow chart of a first embodiment of a Serdes interface data collection method of the present invention;
FIG. 2 is a flow chart of a second embodiment of the Serdes interface data collection method of the present invention;
FIG. 3 is a flow chart of a second embodiment of the Serdes interface data collection method of the present invention;
fig. 4 is a schematic structural diagram of a first embodiment of the Serdes interface data acquisition device according to the present invention;
FIG. 5 is a schematic structural diagram of a second embodiment of the Serdes interface data acquisition device according to the present invention;
fig. 6 is a schematic structural diagram of a data acquisition device with Serdes interface according to a third embodiment of the present invention.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
As shown in fig. 1, which is a flowchart of a first embodiment of the data acquisition method of the Serdes interface of the present invention, specifically, the method may include the following steps:
step 11, acquiring Serdes interface data of a preset quantity by an acquisition circuit according to the indication of the data acquisition starting signal;
in particular, the acquisition circuit is a hardware logic circuit which is arranged on the Serdes interface and is independent of the Serdes interface logic circuit, and can acquire Serdes interface data. The indication of the data acquisition start signal may be sent by the external processor, or may be sent by the Serdes interface logic circuit when the Serdes interface logic circuit finds that the Serdes interface is abnormal, for example, Loss of signal (LOS), coding error, Phase-locked Loop (PLL) Loss, 10 ms BFN frame abnormality, asynchronous First In First Out (FIFO), and the like, and specifically, which triggering method is adopted is selected by the external processor. In addition, the preset number can be flexibly set according to different application scenes.
specifically, after the Serdes interface circuitry stops collecting Serdes interface data, an end-of-collection flag may be output until the external processor is again started back to the state to be collected. The technician can then analyze the collected Serdes interface data to locate the problem with the Serdes interface.
In the embodiment, the Serdes interface data of a preset number are collected under the indication of the data collection starting signal through the sampling circuit, so that the Serdes interface can be quickly positioned by analyzing and collecting the Serdes interface data, and the Serdes interface can be quickly isolated and solved.
As shown in fig. 2, which is a flowchart of a second embodiment of the data acquisition method of the Serdes interface according to the present invention, in this embodiment, a register, for example, a data acquisition status register, is provided in the acquisition circuit. The data acquisition status register may include a trigger condition flag bit therein that the external processor may configure to determine whether the output acquisition enable signal is sent by the external processor or by the Serdes interface logic. In addition, the data collection status register may further include a data collection direction bit, and the external processor configures whether the direction of data collection is a reception direction or a transmission direction by configuring the data collection direction bit, for example: when the data acquisition direction bit is configured to be 1, the direction indicating data acquisition is the receiving direction, when the data acquisition direction bit is configured to be 0, the direction indicating data acquisition is the transmitting direction, when Serdes interface data of the receiving direction is acquired, a 10-millisecond BFN frame of a transmitting end is adopted, and when Serdes interface data of the transmitting direction is acquired, a local 10-millisecond BFN frame is adopted. It should be noted that, in the specific implementation, different flag bits may be implemented by different registers.
In this embodiment, the external processor configures the trigger condition flag as an exception trigger, and the data acquisition start signal is specifically an exception indication signal sent by the Serdes interface logic circuit, so as to acquire service data (e.g., voice service data) transmitted by the Serdes interface. In specific implementation, the data acquisition status register may further include an exception trigger cause bit, and the acquisition circuit may set the exception trigger cause bit to a preset value corresponding to an exception condition, for example: when the abnormal condition is that the Serdes interface has coding error, the acquisition circuit sets the abnormal trigger reason bit to 00, and when the abnormal condition is that the Serdes interface has LOS, the acquisition circuit sets the abnormal trigger reason bit to 01. On the basis of the above embodiment, step 11 may specifically be:
step 21, the collecting circuit collects the Serdes interface data with a preset quantity from the Frame header of the next 10 ms Frame Number Counter (NodeB Frame Number Counter, BFN) Frame after receiving the abnormal indication signal sent by the Serdes interface logic circuit;
specifically, after the Serdes interface logic circuit detects that the Serdes interface is abnormal, an abnormal indication signal is sent to the acquisition circuit. Optionally, after detecting that the Serdes interface is abnormal, after a plurality of BFN frame periods, if the Serdes interface is still abnormal after the plurality of BFN frame periods, the Serdes interface logic circuit may send an abnormal indication signal to the acquisition circuit, so as to ensure that the acquisition circuit can acquire Serdes interface data after the Serdes interface is abnormal, and prevent erroneous acquisition due to short abnormality of the Serdes interface. In addition, the preset number can be freely set according to actual needs, such as: the preset number is N, and N is a positive integer greater than or equal to 1.
On the basis of the above embodiment, the step 12 may further include the following steps:
step 23, the acquisition circuit stores a preset number of Serdes interface data;
specifically, a Random-access memory (RAM) may be disposed inside the acquisition circuit, the RAM does not affect normal data, and the acquired Serdes interface data is stored in the RAM in a circular coverage manner when a control read-write switch of the RAM is turned on.
In this embodiment, step 23 may further include the following steps:
and 24, outputting a data acquisition ending signal by the acquisition circuit.
In this embodiment, the data acquisition signal may specifically be a data acquisition end interrupt signal, and step 24 may specifically include the following steps:
241, the acquisition circuit sends a data acquisition ending interrupt signal to the internal processor, so that the internal processor sends the serial-parallel conversion interface data of the preset number stored by the acquisition circuit to the external processor;
the internal processor knows that the acquisition circuit finishes data acquisition according to the data acquisition ending interrupt signal, sends the Serdes interface data stored in the RAM to the external processor, and the external processor can acquire N frame data after the Serdes interface is abnormal. Optionally, the acquisition circuit may also directly send the data acquisition end interrupt signal to an external processor, and the external processor learns that the acquisition circuit has completed data acquisition according to the data acquisition end interrupt signal, and directly acquires acquired Serdes interface data from the RAM. Technicians can enable the Serdes interface data to correspond to the abnormal reasons identified by the abnormal reason bits in the data acquisition state register, if the characteristics of the data accord with the corresponding abnormal reasons, the corresponding abnormal conditions of the Serdes interface logic circuit can be determined, otherwise, the data are continuously analyzed to find the problems, and therefore the problems of the Serdes interface are quickly located.
In the embodiment, when an abnormal indication signal sent by a Serdes interface logic circuit after a Serdes interface is detected is received by an acquisition circuit, Serdes interface data of a preset quantity after the Serdes interface is abnormal is acquired, then the acquisition circuit stores the Serdes interface data of the preset quantity, after the acquisition is finished, the acquisition circuit sends a data acquisition finishing interrupt signal to an internal processor, and the internal processor sends the Serdes interface data of the preset quantity acquired by the acquisition circuit to an external processor, so that the problem of the Serdes interface can be quickly positioned according to the acquired Serdes interface data.
As shown in fig. 3, which is a flowchart of a second embodiment of the Serdes interface data acquisition method of the present invention, the difference from the technical solution shown in fig. 1 is that the acquisition circuit provides a register, for example: a data acquisition status register. The data acquisition status register includes a trigger condition flag that the external processor can configure to determine whether the data acquisition enable signal is sent by the external processor or by the Serdes interface logic. In this embodiment, the external processor configures the trigger condition flag in the data collection status register as a data collection start signal to be sent by the external processor, so that the external processor collects Serdes interface data as required, and a debugging means is provided for the Serdes interface. On the basis of the technical scheme shown in fig. 1, the data acquisition start signal may specifically be a data acquisition trigger signal sent by an external processor, and step 11 may specifically be:
and step 31, the acquisition circuit acquires the Serdes interface data with a preset quantity from the frame header of the next 10-millisecond BFN frame after receiving the data acquisition trigger signal sent by the external processor.
Specifically, when the Serdes interface needs to be debugged, the external processor sends a data acquisition trigger signal to the acquisition circuit, and then the acquisition circuit starts to acquire a preset amount of Serdes interface data and stores the acquired Serdes interface data in the RAM. In addition, the preset number can be freely set according to actual conditions, such as: and setting M as a positive integer greater than or equal to 1, after receiving a data acquisition trigger signal sent by an external processor, an acquisition circuit acquires M-frame Serdes interface data from the frame header of the next 10-millisecond BFN frame, and then stops acquiring the data.
On the basis of the above embodiment, the following steps may be further included after step 12:
step 33, the acquisition circuit stores a preset amount of Serdes interface data;
specifically, a RAM may be provided inside the acquisition circuit, the RAM does not affect normal data, and the acquired Serdes interface data is stored in the RAM in a cyclic coverage manner under the condition that a control read-write switch of the RAM is turned on.
In this embodiment, step 33 may further include the following steps:
and step 34, outputting a data acquisition ending signal by the acquisition circuit.
In this embodiment, the collection end signal may specifically be a data collection end identifier in a data collection status register.
Specifically, the data collection status register may include a data collection status flag, the data collection status flag is set as a data collection middle flag by the collection circuit in the process of collecting the Serdes interface data, and after collection is finished, the data collection status flag is set as a data collection end flag by the collection circuit. Step 34 may specifically include the following steps:
step 341, the acquisition circuit sets the data acquisition state identifier in the data acquisition state register as a data acquisition end identifier, so that after the external processor queries the data acquisition end identifier, the external processor acquires the serial-to-parallel conversion interface data of the preset number stored in the acquisition circuit;
then, the external processor queries the data acquisition state identifier in the data acquisition state register at regular time, and when the data acquisition state identifier is queried to be a data acquisition end identifier, the external processor learns that the acquisition circuit stops acquiring data according to the data acquisition end identifier, so that the external processor reads the preset amount of data acquired by the acquisition circuit from the RAM. Technicians can compare the collected Serdes interface data with the test data, and if the Serdes interface data are judged to be abnormal after comparison, the problems of the Serdes interface can be quickly positioned according to the collected Serdes interface data.
In this embodiment, the external processor instructs the acquisition circuit to acquire a preset amount of Serdes interface data as needed, and if the Serdes interface is abnormal, the problem of the Serdes interface can be quickly located according to the Serdes interface data.
As shown in fig. 4, which is a schematic structural diagram of the first embodiment of the Serdes interface data acquisition apparatus of the present invention, the apparatus may specifically include a first acquisition module 41 and a stop acquisition module 42.
The first acquisition module 41 is configured to acquire Serdes interface data of a preset number according to an instruction of a data acquisition start signal;
the Serdes interface data acquisition device is a hardware logic circuit which is arranged on the Serdes interface and is independent of the Serdes interface logic circuit. The indication of the data acquisition start signal may be sent by the external processor, or may be sent by the Serdes interface logic circuit when the Serdes interface logic circuit finds that an abnormality occurs in the Serdes interface, for example, LOS, coding error, PLL lock LOSs, 10 ms BFN frame abnormality, asynchronous FIFO, or the like, and specifically, which triggering method is adopted is selected by the external processor. In addition, the preset number can be flexibly set according to different application scenes.
The acquisition stopping module 42 is configured to stop acquiring the Serdes interface data after the acquisition of the preset number of Serdes interface data is finished;
specifically, after the Serdes interface circuitry stops collecting Serdes interface data, an end-of-collection flag may be output until the external processor is again started back to the state to be collected.
In the embodiment, the first acquisition module 41 acquires the Serdes interface data in a preset amount under the indication of the data acquisition starting signal, so that a technician can quickly locate the Serdes interface by analyzing and acquiring the Serdes interface data, and the problem of the Serdes interface is guaranteed to be quickly isolated and solved.
As shown in fig. 5, a schematic structural diagram of a second embodiment of the Serdes interface data acquisition device of the present invention is different from the schematic structural diagram shown in fig. 4 in that the present embodiment may further include a register 50, and the register 50 may specifically be, for example: a data acquisition status register. The data acquisition status register may include a trigger condition flag bit therein that the external processor may configure to determine whether the output acquisition enable signal is sent by the external processor or by the Serdes interface logic. In addition, the data collection status register may further include a data collection direction bit, and the external processor configures whether the direction of data collection is a reception direction or a transmission direction by configuring the data collection direction bit, for example: when the data acquisition direction bit is configured to be 1, the direction indicating data acquisition is the receiving direction, when the data acquisition direction bit is configured to be 0, the direction indicating data acquisition is the transmitting direction, when Serdes interface data of the receiving direction is acquired, a 10-millisecond BFN frame of a transmitting end is adopted, and when Serdes interface data of the transmitting direction is acquired, a local 10-millisecond BFN frame is adopted. It should be noted that, in the specific implementation, different flag bits may be implemented by different registers.
In the present embodiment, the register 50 configures the data acquisition start signal as an abnormal indication signal sent by the Serdes interface logic circuit, so as to acquire service data (e.g., voice service data) transmitted by the Serdes interface. On the basis of the schematic structural diagram shown in fig. 4, the first acquisition module 41 may specifically include a first receiving unit 52, a first counter 53, and a first acquisition unit 54.
The first receiving unit 52 is configured to receive an abnormal indication signal sent by the Serdes interface logic circuit.
Specifically, after the Serdes interface logic circuit detects that the Serdes interface is abnormal, an abnormal indication signal is sent to the Serdes interface data acquisition device. Optionally, the Serdes interface logic circuit may further send an abnormality indication signal to the Serdes interface data acquisition device after a plurality of BFN frame periods pass after the Serdes interface is detected to be abnormal, if the Serdes interface still has an abnormality after the plurality of BFN frame periods, so as to ensure that the Serdes interface data acquisition device can acquire Serdes interface data after the Serdes interface is abnormal, and prevent erroneous acquisition due to a short abnormality of the Serdes interface.
The first counter 53 is used to set a preset number.
The preset number can be freely set according to actual needs, for example: the preset number is N, and N is a positive integer greater than or equal to 1;
the first collecting unit 54 is configured to collect a preset amount of Serdes interface data from a frame header of a next 10 ms BFN frame after the first receiving unit 52 receives the abnormality indication signal.
The present embodiment may further include a storage module 51, configured to store a preset amount of Serdes interface data acquired by the first acquisition unit 54.
Specifically, the storage module 51 is a RAM, which does not affect normal data, and stores the Serdes interface data acquired by the first acquisition unit 54 in a cyclic coverage manner in the RAM when a control read-write switch of the RAM is turned on.
On the basis of the schematic structural diagram shown in fig. 4, the present embodiment may further include an output module 55 for outputting a data acquisition end signal. In this embodiment, the data collection end signal may specifically be a data collection end interrupt signal, and the output module 55 may specifically include a sending unit 56, configured to send the data collection end interrupt signal to the internal processor, so that the internal processor sends the predetermined number of serial-to-parallel conversion interface data stored in the storage module 51 to the external processor.
Specifically, the internal processor knows that the data acquisition device of the Serdes interface has finished data acquisition according to the data acquisition end interrupt signal, and sends N frame data after the Serdes interface is abnormal, which is stored in the RAM, to the external processor, so that the N frame data after the Serdes interface is abnormal can be acquired.
Alternatively, the sending unit 56 may also send the data acquisition end interrupt signal directly to an external processor, and the external processor learns that the Serdes interface data acquisition device has completed data acquisition according to the data acquisition end interrupt signal, and directly acquires the acquired Serdes interface data from the storage module 51.
And corresponding the N frame data after the Serdes interface is abnormal to the abnormal reason identified by the abnormal reason bit in the data acquisition state register, if the characteristics of the data accord with the corresponding abnormal reason, determining that the corresponding abnormal condition occurs in the Serdes interface logic circuit, otherwise, continuously analyzing the data to find the problem, thereby quickly positioning the problem of the Serdes interface.
In addition, after the data acquisition is finished, the first acquisition unit 54 does not acquire the Serdes interface data until the external processor restarts the Serdes interface data acquisition device to return to the state to be acquired, and the first acquisition unit 54 continues to acquire the Serdes interface data.
In this embodiment, when the first receiving unit 52 receives an abnormal indication signal sent by the Serdes interface logic circuit after detecting that the Serdes interface occurs, the first acquiring unit 54 acquires a preset number of Serdes interface data after the Serdes interface occurs abnormally, then the storage module 51 stores the preset number of Serdes interface data, after the acquisition is completed, the transmitting unit 56 sends a data acquisition completion interrupt signal to the internal processor, and the internal processor sends the preset number of Serdes interface data acquired by the first acquiring unit 54 to the external processor, so that the problem of the Serdes interface can be quickly located according to the acquired Serdes interface data.
As shown in fig. 6, a schematic structural diagram of a third embodiment of the Serdes interface data acquisition device of the present invention is different from the schematic structural diagram shown in fig. 4 in that the present embodiment may further include a register 50, for example: a data acquisition status register. The data acquisition status register includes a trigger condition flag that the external processor can configure to determine whether the data acquisition enable signal is sent by the external processor or by the Serdes interface logic. In this embodiment, the register 50 configures the data acquisition start signal as a data acquisition trigger signal sent by the external processor, so that the external processor acquires the Serdes interface data as needed, and provides a debugging means for the Serdes interface.
On the basis of the schematic structural diagram shown in fig. 4, the first acquisition module 41 may specifically include a second receiving unit 61, a second counter 62, and a second acquisition unit 63.
The second receiving unit 61 is configured to receive a data acquisition trigger signal sent by an external processor. Specifically, when the Serdes interface needs to be debugged, the external processor sends a data acquisition trigger signal to the Serdes interface data acquisition device,
the second counter 62 is used to set a preset number.
The second acquiring unit 63 is configured to acquire the preset number of Serdes interface data set by the second counter 62 from the frame header of the next 10 ms BFN frame after the second receiving unit 61 receives the data acquisition trigger signal.
The preset number can be freely set according to actual conditions, such as: when the setting is M, after the second receiving unit 61 receives the data acquisition trigger signal sent by the external processor, the second acquiring unit 63 acquires the M-frame Serdes interface data from the frame header of the next 10-millisecond BFN frame, and then stops the acquiring module 42 to stop acquiring the data.
The difference from the schematic structural diagram shown in fig. 4 is that the present embodiment may further include a storage module 51, configured to store a preset number of Serdes interface data.
Specifically, the storage module 51 may be a RAM, which does not affect normal data, and stores the collected Serdes interface data in the RAM in a cyclic coverage manner when a control read-write switch of the RAM is turned on.
On the basis of the schematic structural diagram shown in fig. 4, the present embodiment may further include an output module 55 for outputting a data acquisition end signal. In this embodiment, the collection end signal may specifically be a data collection end identifier in the register 50, and the output module 55 may specifically include a setting unit 64, configured to set the data collection status identifier in the register 50 as the data collection end identifier.
Specifically, the register 50 may include a data collection status flag, during the collection of the Serdes interface data by the second collection unit 63, the setting unit 64 sets the data collection status flag as a data collection middle flag, and after the collection is finished, the setting unit 64 sets the data collection status flag as a data collection end flag.
Then, the external processor periodically queries the data acquisition status flag in the register 50, and when the data acquisition status flag is queried to be the data acquisition end flag, the external processor knows that the Serdes interface data acquisition device has stopped acquiring data, and then reads the preset amount of data acquired by the Serdes interface data acquisition device from the RAM. And then, comparing the acquired Serdes interface data with the test data, and if the Serdes interface data is judged to be abnormal after comparison, quickly positioning the problem of the Serdes interface according to the acquired Serdes interface data.
In this embodiment, the second receiving unit 61 receives a data acquisition trigger signal sent by an external processor as required, and the second acquiring unit 63 acquires a preset amount of Serdes interface data, so that if the Serdes interface is abnormal, the problem of the Serdes interface can be quickly located according to the Serdes interface data.
Finally, it should be noted that: although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention.
Claims (6)
1. A data acquisition method of a serial-parallel conversion interface is characterized by comprising the following steps:
acquiring serial-parallel conversion interface data of a preset quantity according to the indication of the data acquisition starting signal;
stopping collecting the serial-parallel conversion interface data after the collection of the serial-parallel conversion interface data of the preset number is finished;
after the serial-parallel conversion interface data of the preset number are stored, outputting a data acquisition ending signal;
the data acquisition ending signal is specifically a data acquisition ending interrupt signal; the output data acquisition end signal specifically comprises: sending a data acquisition ending interrupt signal to the internal processor so that the internal processor sends the stored serial-parallel conversion interface data with the preset number to the external processor; or,
the data acquisition ending signal is specifically a data acquisition ending identifier; the output data acquisition end signal specifically comprises: and setting the data acquisition state identifier in the data acquisition state register as a data acquisition end identifier so that the external processor can acquire the stored serial-parallel conversion interface data with the preset quantity after inquiring the data acquisition end identifier.
2. The method according to claim 1, wherein the data acquisition start signal is specifically an abnormality indication signal sent by a serial-to-parallel conversion interface logic circuit;
the method for acquiring the serial-parallel conversion interface data of the preset number according to the indication of the data acquisition starting signal specifically comprises the following steps:
and collecting the serial-parallel conversion interface data with preset quantity from the frame head of the next 10-millisecond frame number counter frame after receiving the abnormal indication signal sent by the serial-parallel conversion interface logic circuit.
3. The method according to claim 1, characterized in that the data acquisition initiation signal is in particular a data acquisition trigger signal sent by an external processor;
the method for acquiring the serial-parallel conversion interface data of the preset number according to the indication of the data acquisition starting signal specifically comprises the following steps:
and acquiring the serial-parallel conversion interface data with a preset quantity from the frame head of the next 10-millisecond frame number counter frame after receiving the data acquisition trigger signal sent by the external processor.
4. A serial-to-parallel conversion interface data acquisition device, comprising:
the first acquisition module is used for acquiring serial-parallel conversion interface data of a preset number according to the indication of the data acquisition starting signal;
the acquisition stopping module is used for stopping acquiring the serial-parallel conversion interface data after the acquisition of the preset number of the serial-parallel conversion interface data is finished;
the storage module is used for storing the serial-parallel conversion interface data with the preset quantity;
the output module is used for outputting a data acquisition ending signal;
the data acquisition ending signal is specifically a data acquisition ending interrupt signal; the output module includes: the sending unit is used for sending the data acquisition ending interrupt signal to the internal processor so that the internal processor sends the serial-parallel conversion interface data of the preset number stored by the storage module to the external processor; or,
the data acquisition ending signal is specifically a data acquisition ending identifier in a register; the output module includes: and the setting unit is used for setting the data acquisition state identifier in the register as the data acquisition ending identifier so as to obtain the serial-parallel conversion interface data of the preset quantity stored by the storage module after the external processor inquires the data acquisition ending identifier.
5. The apparatus of claim 4,
the register is used for configuring the data acquisition starting signal into an abnormal indicating signal sent by a serial-parallel conversion interface logic circuit;
the first acquisition module comprises:
the first receiving unit is used for receiving an abnormal indication signal sent by the serial-parallel conversion interface logic circuit;
a first counter for setting the preset number;
and the first acquisition unit is used for acquiring the serial-parallel conversion interface data of the preset quantity at the beginning of the frame header of the next 10-millisecond frame number counter frame after the first receiving unit receives the abnormal indication signal.
6. The apparatus of claim 4,
the register is used for configuring the data acquisition starting signal into a data acquisition triggering signal sent by an external processor;
the first acquisition module comprises:
the second receiving unit is used for receiving the data acquisition trigger signal sent by the external processor;
a second counter for setting the preset number;
and the second acquisition unit is used for acquiring the serial-parallel conversion interface data with the preset quantity from the frame header of the next 10-millisecond frame number counter frame after the second receiving unit receives the data acquisition trigger signal.
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杨兴等.组合电路内建自测试技术的研究.《电子质量》.2008,(第12期),第3-5,7页. * |
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