CN116825170B - Automatic calibration architecture and chip for die-to-die interconnect - Google Patents
Automatic calibration architecture and chip for die-to-die interconnect Download PDFInfo
- Publication number
- CN116825170B CN116825170B CN202311109092.2A CN202311109092A CN116825170B CN 116825170 B CN116825170 B CN 116825170B CN 202311109092 A CN202311109092 A CN 202311109092A CN 116825170 B CN116825170 B CN 116825170B
- Authority
- CN
- China
- Prior art keywords
- calibration
- die
- demultiplexer
- multiplexer
- architecture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 claims abstract description 178
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 230000005540 biological transmission Effects 0.000 description 12
- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 4
- 238000004590 computer program Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
The application discloses an automatic calibration architecture and chip for die-to-die interconnection. The architecture is applied to a D2D interconnect architecture, comprising: the master calibration module is arranged in the first crystal grain and the slave calibration module is arranged in the second crystal grain, and is connected with the slave calibration module through a state connecting wire, and when power is on, the master calibration module sequentially generates calibration test data packets and sends the calibration test data packets to the second crystal grain under the state that the connection between the multiplexer and the demultiplexer is in different delay values; the slave calibration module compares the locally generated calibration test template data packet with the calibration test data packet and sends the comparison result to the master calibration module through a state connecting wire; the main calibration module determines an optimal delay value between the multiplexer and the demultiplexer according to comparison results obtained in states of different delay values and sets the optimal delay value. The technical scheme of the embodiment of the application can reduce the overhead and complexity of the automatic calibration of the D2D interconnection.
Description
Technical Field
Embodiments of the present application relate to chip technology, and more particularly, to an automatic calibration architecture for die-to-die interconnect and a chip.
Background
Chip (chip) is a new die-to-die (D2D) interconnect technology, which is one of the key features that today improves memory performance. In the chip technology, a data transmission channel is formed between a plurality of interconnected chips by a high-speed multiplexer and a multiplexer analog front end pair.
To minimize the impact of process variations (including substrate capacitance and resistance) and conditions (e.g., temperature and voltage) on the system environment, i.e., to reduce the variation between interconnected chips, chiplet techniques employ power-on calibration techniques to adjust the delay in capturing the data clock. However, one of the main problems of die-to-die connection is that the interconnect between the chip as the data transmitting side and the chip as the data receiving side may be disconnected at a high operating frequency before calibration.
In order to solve the above problem, one of the currently adopted processing methods is to reduce the operating frequency of the upper electric device, and the other processing method is to provide a low-frequency sideband channel for the calibration process of two interconnected chips. However, the above-described processing may add additional overhead or complexity to the calibration process.
Disclosure of Invention
The application provides an automatic calibration architecture and a chip for die-to-die interconnection, which can reduce the overhead and complexity of D2D interconnection automatic calibration.
In a first aspect, an embodiment of the present application provides an auto-calibration architecture for die-to-die interconnect, applied to a D2D interconnect architecture, the D2D interconnect architecture including a first die and a second die, a multiplexer disposed in the first die being connected to a demultiplexer disposed in the second die, the auto-calibration architecture comprising;
a master calibration module disposed in a first die and a slave calibration module disposed in the second die;
the master calibration module is connected with the slave calibration module through a state connecting wire;
when the D2D interconnection architecture is powered on, the main calibration module sequentially generates calibration test data packets in a state that the connection between the multiplexer and the demultiplexer is in different delay values, and sends the calibration test data packets to the second crystal grain through the connection between the multiplexer and the demultiplexer;
the slave calibration module compares the locally generated calibration test template data packet with the calibration test data packet and sends a comparison result to the master calibration module through the state connecting line;
the main calibration module determines an optimal delay value between the multiplexer and the demultiplexer according to a comparison result obtained when the connection between the multiplexer and the demultiplexer is in different delay values;
the master calibration module sets a delay value between the multiplexer and the demultiplexer to the optimal delay value.
In a possible implementation manner of the first aspect, the master calibration module includes a calibration test data packet generator and a calibration test controller, and the slave calibration module includes a calibration test template data packet generator and a data comparator;
the calibration test data packet generator is used for generating a calibration test data packet, and the calibration test controller is used for controlling the multiplexer to send the calibration test data packet to the demultiplexer in a state that the connection with the demultiplexer is in different delay values;
the data comparator is used for comparing the calibration test template data packet with the calibration test data packet and sending a comparison result to the calibration test controller through the state connecting wire;
the calibration test controller is further configured to determine an optimal delay value between the multiplexer and the demultiplexer, and control the multiplexer to set the delay value between the multiplexer and the demultiplexer to the optimal delay value.
In a possible implementation manner of the first aspect, the slave calibration module further includes a memory, where the memory is configured to store the calibration test template data packet generated by the calibration test template data packet generator;
the data comparator is used for comparing the calibration test template data packet stored in the memory with the calibration test data packet and sending the comparison result to the calibration test controller through the state connecting wire.
In a possible implementation manner of the first aspect, the memory is a FIFO memory.
In a possible implementation manner of the first aspect, the data comparator is specifically configured to compare the calibration test template data packet with the calibration test data packet, send a comparison passing result to the calibration test controller through the status connection line if the comparison is consistent, and send a comparison failure result to the calibration test controller through the status connection line if the comparison is inconsistent.
In a possible implementation manner of the first aspect, the calibration test controller is specifically configured to select an optimal delay value between the multiplexer and the demultiplexer from delay values of the multiplexer and the demultiplexer corresponding to a comparison passing result received from the data comparator.
In a possible implementation manner of the first aspect, the calibration test template packet generator is specifically configured to set the connection between the multiplexer and the demultiplexer to different delay values after each generation of the calibration test template packet.
In a possible implementation manner of the first aspect, the slave calibration module is specifically configured to send, when powered on, readiness information to the master calibration module through the status connection line;
the master calibration module is specifically configured to sequentially generate calibration test data packets in a state that a connection between the multiplexer and the demultiplexer is at different delay values after receiving the readiness information sent by the slave calibration module, and send the calibration test data packets to the second die through the connection between the multiplexer and the demultiplexer.
In a possible implementation manner of the first aspect, automatic calibration is achieved by providing an additional automatic calibration architecture between the multiplexer provided in the second die and the demultiplexer provided in the first die.
In a possible implementation manner of the first aspect, when the D2D interconnection architecture includes a plurality of second dies, a plurality of multiplexers are disposed in the first dies, a demultiplexer disposed in each second die is connected to one or more multiplexers in the first dies, and automatic calibration is achieved by setting the automatic calibration architecture between the connection of each pair of multiplexers and demultiplexers.
In a second aspect, embodiments of the present application provide a chip comprising at least two dies, any two of the at least two dies including an auto-calibration architecture for die-to-die interconnection as described in any one of the possible implementations of the first aspect.
According to the grain-to-grain interconnection automatic calibration framework and the chip provided by the embodiment of the application, the automatic calibration of the D2D interconnection framework can be realized by only arranging the master calibration module and the slave calibration module and the state connecting wire for connecting the master calibration module and the slave calibration module in two grains which are interconnected, other extra operations on the grains are not needed, and extra low-frequency sideband channels are not needed to be configured, so that the cost and the system complexity for calibrating the D2D framework are reduced.
Drawings
FIG. 1 is a schematic diagram of an architecture for automatic calibration of die-to-die interconnection according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an alternative die-to-die interconnect auto-calibration architecture according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an architecture for automatic calibration of die-to-die interconnection according to another embodiment of the present application;
fig. 4-9 are schematic diagrams illustrating states of embodiments of an automatic calibration using an automatic die-to-die interconnect calibration architecture provided by embodiments of the present application.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings.
Fig. 1 is a schematic structural diagram of an automatic calibration architecture for die-to-die interconnection according to an embodiment of the present application, as shown in fig. 1, the automatic calibration architecture for die-to-die interconnection according to the present embodiment is applied to a D2D interconnection architecture, where the D2D interconnection architecture includes a first die 11 and a second die 12, and a multiplexer 111 disposed in the first die 11 is connected to a demultiplexer 121 disposed in the second die 12.
The first die 11 and the second die 12 constitute a basic D2D interconnect architecture, i.e. consist of two interconnected dies, wherein a multiplexer 111 is provided in the first die 11 and a demultiplexer 121 is provided in the second die 12. The first die 11 and the second die 12 are connected to each other via a multiplexer 111 and a demultiplexer 121 to realize data transmission. The first die 11 and the second die 12 connected through the multiplexer 111 and the demultiplexer 121 can only realize unidirectional data transmission of the first die 11 to the second die 12, and in some scenarios where a D2D interconnect architecture is applied, it is necessary to use a D2D interconnect architecture that can only realize unidirectional data transmission. Of course, a demultiplexer may be further disposed in the first die 11, a multiplexer may be further disposed in the second die 12, and a data transmission channel from the second die 12 to the first die 11 is formed after the demultiplexer disposed in the first die 11 and the multiplexer disposed in the second die 12 are connected with each other. The embodiment takes the data transmission channel between the first die 11 and the second die 12 through the multiplexer 111 and the demultiplexer 121 as an example, and describes an automatic calibration architecture for die-to-die interconnection provided in the embodiment of the present application. For each data transmission channel formed by the multiplexer and the demultiplexer in the D2D interconnection architecture, the automatic calibration architecture of die-to-die interconnection provided by the embodiment of the present application may be used to implement automatic calibration. Where multiplexer 111 is a multiplexer and demultiplexer 121 is a demultiplexer.
The automatic calibration architecture provided by the embodiment of the application comprises the following steps: a master calibration module 112 disposed in the first die 11 and a slave calibration module 122 disposed in the second die 12. The master calibration module 112 and the slave calibration module 122 are connected by a status connection line 13. The status connection line 13 is a normal connection line and is used only for transmitting calibration status information.
Since in the D2D interconnection architecture, the clocks may be inconsistent due to the influence of various factors such as process, temperature, voltage, etc. of the first die 11 and the second die 12, calibration needs to be performed during power-up, in this embodiment, the master calibration module 112 is dominant by the master calibration module 112 disposed in the first die 11, and the master calibration module 112 cooperates with the slave calibration module 122 to implement automatic calibration of the first die 11 and the second die 12. The master calibration module 112 and the slave calibration module 122 are in a master-slave control relationship, the whole calibration process is controlled by the master calibration module 112, and the slave calibration module 122 is used for feeding back the control completion state according to the master calibration module 112.
The connection between the first die 11 and the second die 12 established through the multiplexer 111 and the demultiplexer 121 may be divided into a data transmission line (dq) and a gate transmission line (dqs), which have different delay values, and the clock skew between the first die 11 and the second die 12 may be compensated by setting the different delay values for dq and dqs. When a specific delay value combination is set for dq and dqs, clock skew of the connection established between the first die 11 and the second die 12 through the multiplexer 111 and the demultiplexer 121 can be eliminated, thereby completing calibration.
In this embodiment, first, at power-up of the D2D interconnect architecture, the master calibration module 112 generates a calibration test packet, while the slave calibration module 122 generates a calibration test template packet. The master calibration module 112 and the slave calibration module 122 independently generate a calibration test data packet and a calibration test template data packet, respectively. Wherein the calibration data packet is the same as the calibration test template data packet. After the master calibration module 112 generates the calibration test data packet, the calibration test data packet is sent to the second die 12 through the connection between the multiplexer 111 and the demultiplexer 112. In order to calibrate the D2D interconnect architecture, the master calibration module 112 needs to send calibration test packets to the second die 12 in states where the connection between the multiplexer 111 and the demultiplexer 112 is at different delay values.
After receiving the calibration test data packet sent by the main calibration module 112, the demultiplexer 121 of the second die 12 compares the locally generated calibration test template data packet with the received calibration test data packet by the slave calibration module 122, and then sends the comparison result to the main calibration module 112 through the status connection line 13. The master calibration module 112 sends a calibration test packet to the second die 12 when the connection between the multiplexer 111 and the demultiplexer 112 is at each different delay value, and the slave calibration module 122 compares the locally generated calibration test template packet with the received calibration test packet each time the demultiplexer 121 receives the calibration test packet, and sends the comparison result to the master calibration module 112, so that the master calibration module 112 can know the comparison result of the calibration test template packet and the calibration test packet when the connection between the multiplexer 111 and the demultiplexer 121 is at different delay values. When the first die 11 and the second die 12 are not clock synchronized, the data packet sent by the first die 11 to the second die 12 through the connection between the multiplexer 111 and the demultiplexer 121 may be in error due to the out of clock, so that the comparison result of the calibration test template data packet and the calibration test data packet in the state that the main calibration module 121 is in different delay values through the connection between the multiplexer 111 and the demultiplexer 121 can determine which delay value or delay values can synchronize the clocks between the first die 11 and the second die 12.
The master calibration module 112 determines an optimal delay value between the multiplexer 111 and the demultiplexer 121 according to a comparison result obtained in a state that the connection between the multiplexer 111 and the demultiplexer 121 is at different delay values, wherein the optimal delay value may be one or more. The optimal delay value indicates that the comparison result of the calibration test packet and the calibration test template packet is identical when the optimal delay value is set between the multiplexer 111 and the demultiplexer 121, that is, the data between the first die 11 and the second die 12 can be normally transmitted.
Finally, the master calibration module 112 sets the delay value between the multiplexer 111 and the demultiplexer 121 to the determined optimal delay value. When the determined optimal delay value is a plurality, the master calibration module 112 may set any one of the optimal delay values. Or the master calibration module 112 may set one of the optimal delay values according to a preset policy, such as setting the one of the optimal delay values with the smallest delay value. After the setting of the optimal delay value is completed, normal data transmission between the first die 11 and the second die 12 can be realized through the connection between the multiplexer 111 and the demultiplexer 121, that is, the calibration of the D2D interconnection architecture is completed.
The slave calibration module 122 is specifically configured to send, when powered on, preparation status information to the master calibration module 112 through the status connection line 13; the master calibration module 112 is specifically configured to, after receiving the readiness information sent by the slave calibration module 122, sequentially generate calibration test data packets in a state that the connection between the multiplexer 111 and the demultiplexer 121 is at different delay values, and send the calibration test data packets to the second die 12 through the connection between the multiplexer 111 and the demultiplexer 121. Since clocks of the first die 11 and the second die 12 in the D2D interconnect architecture may not be synchronized, power-up times of the first die 11 and the second die 12 may be different, and data processing according to a uniform timing may not be performed until calibration is not completed. Therefore, in order to ensure the reliability of the automatic calibration process, a status parameter may be set for the status connection line 13, and when the slave calibration module 122 is powered on, the status connection line 13 is used to send preparation status information to the master calibration module 112, where the preparation status information is used to enable the master calibration module 112 to know that the slave calibration module 122 has completed automatic calibration preparation, and the master calibration module 112 only sends a calibration test data packet, so that it is avoided that the slave calibration module 122 does not generate a calibration test template data packet after the master calibration module 112 controls the sending of the calibration test data packet, and the automatic calibration cannot be performed normally. That is, the die-to-die interconnection auto-calibration architecture provided by the embodiments of the present application can achieve self-sustained auto-calibration without considering the power-up time of the die.
In addition, to further improve the reliability of the automatic calibration, different readiness information may be configured for the power-up phase and the calibration phase of the calibration process. After the second die 12 is powered up, the slave calibration module 122 first sends "idle" status information to the master calibration module 112 via the status connection line 13 to inform the master calibration module 112 that the second die 12 has been powered up, but at this time the slave calibration module 122 has not yet generated a calibration test template data packet, so the master calibration module 112 has not yet been able to send a calibration test data packet to the second die 12. After the calibration test template data packet is generated from the calibration module 122, the "ready" status information is sent to the master calibration module 112 via the status connection line 13, at which point the master calibration module 112 resumes sending the calibration test data packet to the second die 12. The state connection 13 only requires 1bit bandwidth to send both the "idle" and "ready" state parameters.
According to the automatic calibration architecture for the D2D interconnection, provided by the embodiment, the automatic calibration of the D2D interconnection architecture can be realized only by respectively arranging the master calibration module and the slave calibration module in two crystal grains which are interconnected and connecting the state connecting wires of the master calibration module and the slave calibration module, other extra operations on the crystal grains are not needed, and extra low-frequency sideband channels are not needed to be configured, so that the cost and the system complexity for calibrating the D2D interconnection are reduced.
In the die-to-die interconnect auto-calibration architecture shown in fig. 1, auto-calibration is shown implemented for a connection configuration auto-calibration architecture between a multiplexer 111 in a first die 11 and a demultiplexer 121 in a second die 12. When the D2D architecture further comprises a connection between the multiplexer in the second die 12 and the demultiplexer in the first die 11, an additional auto-calibration architecture is provided between the first die 11 and the second die 12 to enable auto-calibration of the connection, except that a master calibration module is provided in the second die 12 and a slave calibration module is provided in the first die 11.
In addition, the auto-calibration architecture of the D2D interconnect shown in fig. 1 shows only auto-calibration between two dies. In practice, the D2D interconnect may be composed of more than two dies, as shown in fig. 2, fig. 2 is a schematic structural diagram of another die-to-die interconnect auto-calibration architecture according to an embodiment of the present application. As shown in fig. 2, the D2D interconnect is composed of a first die 11, a second die 12, and a third die 19. Wherein the first die 11 and the second die 12 comprise a connection between the multiplexer 111 and the demultiplexer 121. The first die 11 and the third die 19 include a connection between the multiplexer 116 and the demultiplexer 126 and a connection between the multiplexer 127 and the demultiplexer 117. Then for each of the three connections an auto-calibration architecture as shown in figure 1 may be provided to enable auto-calibration of each connection. The corresponding automatic calibration structures of each connection are mutually independent and do not interfere with each other, and the automatic calibration of each connection is completed respectively.
As shown in fig. 2, in addition to the master calibration module 112 and the slave calibration module 122 and the status connection line 13 provided at the connection of the multiplexer 111 and the demultiplexer 121, the master calibration module 118 and the slave calibration module 128 and the status connection line 14 provided at the connection of the multiplexer 116 and the demultiplexer 126, and the master calibration module 119 and the slave calibration module 129 and the status connection line 15 provided at the connection of the multiplexer 117 and the demultiplexer 127 are included. The master calibration module 112, the slave calibration module 122 and the status connection line 13 are a set of auto-calibration architecture, the master calibration module 118, the slave calibration module 128 and the status connection line 14 are a set of auto-calibration architecture, and the master calibration module 119, the slave calibration module 129 and the status connection line 15 are a set of auto-calibration architecture.
Fig. 3 is a schematic structural diagram of an automatic calibration architecture for die-to-die interconnection according to an embodiment of the present application, as shown in fig. 3, in which, based on fig. 1, the master calibration module 112 further includes a calibration test packet generator 113 and a calibration test controller 114, and the slave calibration module 122 includes a calibration test template packet generator 123 and a data comparator 124.
The calibration test packet generator 113 is configured to generate a calibration test packet, and the calibration test controller 114 is configured to control the multiplexer 111 to send the calibration test packet to the demultiplexer 121 in a state that a connection with the demultiplexer 121 is at a different delay value. The calibration test template data packet generator 123 is configured to generate a calibration test template data packet, and the data comparator 124 is configured to compare the calibration test template data packet with the calibration test data packet, and send the comparison result to the calibration test controller 114 through the status connection line 13. The calibration test controller 114 is further configured to determine an optimal delay value between the multiplexer 111 and the demultiplexer 121, and control the multiplexer 111 to set the delay value between the multiplexer 111 and the demultiplexer 121 to the optimal delay value.
Further, the slave calibration module 122 may further include a memory 125, where the memory 125 is configured to store the calibration test template data packet generated by the calibration test template data packet generator 123. The data comparator 124 is configured to compare the calibration test template data packet stored in the memory 125 with the calibration test data packet, and send the comparison result to the calibration test controller 114 through the status connection line 13. Since the first die 11 and the second die 12 may be asynchronous before the automatic calibration is completed, in order to avoid that the calibration test template packet generator 123 has not generated the calibration test template packet when the demultiplexer 121 receives the calibration test packet, the memory 125 may be configured such that the timing of generating the calibration test template packet by the calibration test template packet generator 123 is irrelevant to the timing of generating the calibration test packet by the calibration test packet generator 113, and the data comparator 124 only needs to compare the calibration test template packet stored in the memory 125 with the calibration test packet received by the demultiplexer 121.
Further, the memory 125 may be a first-in first-out (First Input First Output, FIFO) memory.
The data comparator 124 is specifically configured to compare the calibration test template data packet with the calibration test data packet, send a comparison result to the calibration test controller 114 through the status connection line 13 if the comparison is consistent, and send a comparison failure result to the calibration test controller 114 through the status connection line 13 if the comparison is inconsistent. The data comparator 124 compares the calibration test template data packet with the calibration test data packet to obtain a consistent or inconsistent result, and only needs to send a "pass" comparison result through the state connection line 13 when the result is consistent, and only needs to send a "fail" comparison result through the state connection line 13 when the result is inconsistent. And the comparison results of pass and fail only need 1bit bandwidth to realize transmission, thus reducing the system overhead required by completing calibration.
The calibration test controller 114 is specifically configured to select an optimal delay value between the multiplexer 111 and the demultiplexer 121 from delay values of the multiplexer 111 and the demultiplexer 121 corresponding to a comparison result received from the data comparator 124. The calibration test controller 114 may receive the comparison result of the calibration test template data packet and the calibration test data packet of the multiplexer 111 and the demultiplexer 121 under each delay value combination, and after receiving the comparison result corresponding to all delay values, the calibration test controller 114 selects the best delay value from the comparison result according to a preset policy. The preset strategy is, for example, a random selection, a selection according to a minimum delay, etc.
The calibration test pattern data packet generator 123 is specifically configured to set the connection between the multiplexer 111 and the demultiplexer 121 to different delay values after each generation of the calibration test pattern data packet. Each time the calibration test template packet generator 123 generates a calibration test template packet, which indicates that the second die 12 receives a sequential calibration test packet, the calibration test template packet generator 123 changes the delay value between the multiplexer 111 and the demultiplexer 121, so that the calibration test packet received by the second die 12 next time is sent through a different delay value between the multiplexer 111 and the demultiplexer 121, thereby realizing automatic calibration.
The present application provides an automated die-to-die interconnect calibration architecture, in one embodiment, as described in further detail below.
Fig. 4-9 are schematic diagrams illustrating states of embodiments of an automatic calibration using an automatic die-to-die interconnect calibration architecture provided by embodiments of the present application. In fig. 4-9, the die-to-die interconnect auto-calibration architecture is the same as that shown in fig. 3, wherein a multiplexer 111 (MUX analog front-end in this embodiment) provided in a first die 11 is connected to a demultiplexer 121 (demux analog front-end in this embodiment) provided in the second die 12. The connection between multiplexer 111 and demultiplexer 121 comprises two sets of transmission lines dq and dqs. A calibration test packet generator 113 (in this embodiment, a test template generator (test pattern generator, vec_gen)) and a calibration test controller 114 (in this embodiment, a finite state machine (finite state machine, FSM)) are disposed in the first die 11, and the calibration test packet generator 113 and the calibration test controller 114 constitute a master calibration module 112 (which may also be referred to as a master calibration engine (master calibration engine)). The second die 12 is provided with a calibration test template packet generator 123 (in this embodiment, a golden test template generator (golden test pattern generator, g_vec_gen)), a data comparator 124 (in this embodiment, a scoreboard and verifier (score board and checker, sb_chk)), and a memory 125 (in this embodiment, FIFO). The calibration test template packet generator 123 and the data comparator 124 constitute a slave calibration module 122 (which may also be referred to as a slave calibration engine (slave calibration engine)). The calibration test controller 114 is connected to the data comparator 124 via the status connection line 13.
First, after the D2D interconnect hard reset is powered up, the master calibration module 112 and the slave calibration module 122 begin an auto-calibration procedure. First, as shown in fig. 4, during power-up, a calibration test template packet (gold test template (golden test pattern) in this embodiment) is generated from the calibration test template packet generator 123 in the calibration module 122. The memory 125 is now empty. The state parameters of the idle state (idle) are now sent from the data comparator 124 in the calibration module 122 via the state connection 13. At this point, the calibration test controller 114 in the master calibration module 111 is in a wait state (wait) after power-up.
As shown in fig. 5, after the first calibration test template packet is generated, the calibration module 122 is changed to ready and the state parameters of the ready state are sent through the state connection 13. The calibration test template packet generator 123 stores the generated calibration test template packet in the memory 125, with the memory 125 being non-empty. The calibration test controller 114 in the master calibration module 111 is still in a standby state.
As shown in fig. 6, the calibration test controller 114 in the main calibration module 111 is in a standby state after power-up, and the calibration test controller 114 continuously monitors the status connection line 13 and maintains the standby state until the ready state is monitored from the status connection line 13. Once the calibration test controller 114 detects the waiting state of the state connection line 13, the calibration test controller 114 will switch to the active state and control the calibration test packet generator 113 to start generating the first calibration test packet and then send it to the second die 12 via the connection between the multiplexer 111 and the demultiplexer 121.
As shown in fig. 7, the calibration test controller 114 will stop and change state to hold after transmitting the first calibration test packet. In the hold state, the calibration test controller 114 will continuously monitor the status connection line 13 awaiting the results fed back from the calibration module 122.
As shown in fig. 8, when the second die 12 receives the calibration test data packet, the data comparator 124 extracts the calibration test template data packet from the memory 125 and compares it with the received calibration test data packet. When the comparison of the data packets is completed, the data comparator 124 sends the comparison result (pass/fail) to the calibration test controller 114 via the status connection 13. In addition, the calibration test template packet generator 123 has not yet changed the delay value of the connection between multiplexer 111 and demultiplexer 121 for the next set of calibrations.
As shown in fig. 9, after receiving the inspection result of the data comparator 124 by the state connection line 13, the calibration test controller 114 will switch to the active state, and control the calibration test packet generator 113 to generate a second calibration test packet and send the second calibration test packet to the second die 12 for testing of the next set of delay values.
The tests of fig. 6-9 are continued until the data test of all delay value combinations of the connections (i.e., dq and dqs connection lines) between multiplexer 111 and demultiplexer 121 is completed. The pass or fail results of all delay value combinations recorded are analyzed and the best delay value is determined.
Once the above is completed, the master calibration module 112 and the slave calibration module 122 are both brought into an idle state, the first die 11 and the second die 12 will be set to a normal operation mode, while the delay value between the first die 11 and the second die 12 is set to the determined optimal delay value.
As can be seen from the embodiments shown in fig. 4 to 9, compared with the conventional D2D interconnection architecture calibration procedure, in this embodiment, the master calibration module and the slave calibration module are self-maintained, and do not depend on any sideband channel, and only a low-speed state connection line for state exchange needs to be provided between the master calibration module and the slave calibration module. And as can be seen from fig. 4-9, the state connection line only needs to transmit the idle state, the ready state, the pass and the fail state parameters, that is, the state connection line only needs 2bit bandwidth. Therefore, the automatic calibration framework provided by the embodiment of the application can greatly simplify the calibration process and has small occupied cost.
In addition, the master and slave calibration modules do not have a power-on timing requirement, i.e., it is not required to reset the die on the side of the D2D interconnect first, and the master calibration module resumes the calibration flow after determining that the slave calibration module is ready to complete.
Finally, if there are more than 1 connection between the multiplexer and the demultiplexer in the D2D interconnect, the automatic calibration of all connections can be performed simultaneously, and the calibration of each connection is self-maintained only by the automatic calibration architecture configured for it, which can greatly reduce the automatic calibration time after power-up.
Embodiments of the present application also provide a chip comprising at least two dies including an auto-calibration architecture for die-to-die interconnection between any two dies of the at least two dies as described in the embodiments of fig. 1-9.
In general, the various embodiments of the application may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.
Embodiments of the application may be implemented by a data processor of a computer apparatus executing computer program instructions, e.g. in a processor entity, either in hardware, or in a combination of software and hardware. The computer program instructions may be assembly instructions, instruction set architecture ((Instruction Set Architecture, ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages.
The block diagrams of any of the logic flows in the figures of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on a memory. The Memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), optical Memory devices and systems (digital versatile disks (Digital Video Disc, DVD) or Compact Discs (CDs)), etc., the computer readable medium may comprise a non-transitory storage medium.
Claims (11)
1. An auto-calibration architecture for a die-to-die interconnect, characterized by being applied to a die-to-die D2D interconnect architecture, the D2D interconnect architecture comprising a first die and a second die, a multiplexer disposed in the first die being connected to a demultiplexer disposed in the second die, the auto-calibration architecture comprising:
a master calibration module disposed in a first die and a slave calibration module disposed in the second die;
the master calibration module is connected with the slave calibration module through a state connecting wire;
when the D2D interconnection architecture is powered on, the main calibration module sequentially generates calibration test data packets in a state that the connection between the multiplexer and the demultiplexer is in different delay values, and sends the calibration test data packets to the second crystal grain through the connection between the multiplexer and the demultiplexer;
the slave calibration module compares the locally generated calibration test template data packet with the calibration test data packet and sends a comparison result to the master calibration module through the state connecting line;
the main calibration module determines an optimal delay value between the multiplexer and the demultiplexer according to a comparison result obtained when the connection between the multiplexer and the demultiplexer is in different delay values;
the master calibration module sets a delay value between the multiplexer and the demultiplexer to the optimal delay value.
2. The die-to-die interconnect automatic calibration architecture of claim 1, wherein the master calibration module comprises a calibration test packet generator and a calibration test controller, and the slave calibration module comprises a calibration test template packet generator and a data comparator;
the calibration test data packet generator is used for generating a calibration test data packet, and the calibration test controller is used for controlling the multiplexer to send the calibration test data packet to the demultiplexer in a state that the connection with the demultiplexer is in different delay values;
the data comparator is used for comparing the calibration test template data packet with the calibration test data packet and sending a comparison result to the calibration test controller through the state connecting wire;
the calibration test controller is further configured to determine an optimal delay value between the multiplexer and the demultiplexer, and control the multiplexer to set the delay value between the multiplexer and the demultiplexer to the optimal delay value.
3. The die-to-die interconnect automatic calibration architecture of claim 2, wherein the slave calibration module further comprises a memory for storing calibration test template packets generated by the calibration test template packet generator;
the data comparator is used for comparing the calibration test template data packet stored in the memory with the calibration test data packet and sending the comparison result to the calibration test controller through the state connecting wire.
4. The die-to-die interconnect auto-calibration architecture of claim 3, wherein the memory is a first-in-first-out FIFO memory.
5. The die-to-die interconnect automatic calibration architecture of claim 3, wherein the data comparator is specifically configured to compare the calibration test template data packet with the calibration test data packet, send a comparison pass result to the calibration test controller via the status connection line if the comparison is consistent, and send a comparison fail result to the calibration test controller via the status connection line if the comparison is inconsistent.
6. The die-to-die interconnect automatic calibration architecture of claim 5, wherein the calibration test controller is specifically configured to select an optimal delay value between the multiplexer and the demultiplexer among delay values of the multiplexer and the demultiplexer corresponding to a comparison pass result received from the data comparator.
7. The die-to-die interconnect automatic calibration architecture of claim 2, wherein the calibration test template packet generator is specifically configured to set the connection between the multiplexer and the demultiplexer to different delay values after each generation of a calibration test template packet.
8. The die-to-die interconnect automatic calibration architecture of any of claims 1-7, wherein the slave calibration module is specifically configured to send readiness information to the master calibration module via the status connection line upon power-up;
the master calibration module is specifically configured to sequentially generate calibration test data packets in a state that a connection between the multiplexer and the demultiplexer is at different delay values after receiving the readiness information sent by the slave calibration module, and send the calibration test data packets to the second die through the connection between the multiplexer and the demultiplexer.
9. The die-to-die interconnect auto-calibration architecture of any of claims 1-7, wherein auto-calibration is achieved by providing additional auto-calibration architecture between a multiplexer provided in the second die and a demultiplexer provided in the first die.
10. The die-to-die interconnect auto-calibration architecture of any one of claims 1-7, wherein when the D2D interconnect architecture includes a plurality of second dies, a plurality of multiplexers are disposed in the first die, a demultiplexer disposed in each second die is respectively connected to one or more multiplexers in the first die, and auto-calibration is achieved by disposing the auto-calibration architecture between the connections of each pair of multiplexers and demultiplexers.
11. A chip comprising at least two dies, wherein any two of the at least two dies are interconnected, and wherein the die-to-die interconnection auto-calibration architecture of any one of claims 1-10 is included between the dies.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311109092.2A CN116825170B (en) | 2023-08-31 | 2023-08-31 | Automatic calibration architecture and chip for die-to-die interconnect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311109092.2A CN116825170B (en) | 2023-08-31 | 2023-08-31 | Automatic calibration architecture and chip for die-to-die interconnect |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116825170A CN116825170A (en) | 2023-09-29 |
| CN116825170B true CN116825170B (en) | 2023-11-07 |
Family
ID=88139606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311109092.2A Active CN116825170B (en) | 2023-08-31 | 2023-08-31 | Automatic calibration architecture and chip for die-to-die interconnect |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116825170B (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SU902018A1 (en) * | 1980-01-17 | 1982-01-30 | Предприятие П/Я А-1586 | Device for checking logic units |
| US5568492A (en) * | 1994-06-06 | 1996-10-22 | Motorola, Inc. | Circuit and method of JTAG testing multichip modules |
| US6889357B1 (en) * | 2000-05-10 | 2005-05-03 | Micron Technology, Inc. | Timing calibration pattern for SLDRAM |
| CN105161487A (en) * | 2015-08-20 | 2015-12-16 | 上海华力微电子有限公司 | Interconnect parasitic resistance and capacitance calibration structure |
| CN106257588A (en) * | 2015-06-19 | 2016-12-28 | 爱思开海力士有限公司 | Semiconductor device and operational approach thereof including delay circuit |
| CN106575961A (en) * | 2014-09-08 | 2017-04-19 | 高通股份有限公司 | Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems |
| WO2017157026A1 (en) * | 2016-03-16 | 2017-09-21 | 珠海全志科技股份有限公司 | Clock duty-cycle calibration and frequency-doubling circuit |
| US10797683B1 (en) * | 2020-03-06 | 2020-10-06 | Faraday Technology Corp. | Calibration circuit and associated calibrating method capable of precisely adjusting clocks with distorted duty cycles and phases |
| CN111863065A (en) * | 2020-08-04 | 2020-10-30 | 西安紫光国芯半导体有限公司 | ZQ calibrator, ZQ calibration method and memory |
| CN112751660A (en) * | 2015-09-01 | 2021-05-04 | 高通股份有限公司 | Method and apparatus for multi-phase clock data recovery circuit calibration |
| CN115461632A (en) * | 2020-04-20 | 2022-12-09 | 普腾泰克斯有限公司 | Die-to-die connectivity monitoring |
| WO2022262587A1 (en) * | 2021-06-16 | 2022-12-22 | 中兴通讯股份有限公司 | Data transmission method and apparatus, system, electronic device, and readable medium |
| CN115576894A (en) * | 2022-10-27 | 2023-01-06 | 无锡先进技术研究院 | Chiplet core particle based on PCIE standard interface interconnection and interface multiplexing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7818135B2 (en) * | 2008-05-30 | 2010-10-19 | Agere Systems Inc. | Optimum timing of write and read clock paths |
| US8140756B2 (en) * | 2009-04-15 | 2012-03-20 | International Business Machines Corporation | Information handling system with immediate scheduling of load operations and fine-grained access to cache memory |
-
2023
- 2023-08-31 CN CN202311109092.2A patent/CN116825170B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SU902018A1 (en) * | 1980-01-17 | 1982-01-30 | Предприятие П/Я А-1586 | Device for checking logic units |
| US5568492A (en) * | 1994-06-06 | 1996-10-22 | Motorola, Inc. | Circuit and method of JTAG testing multichip modules |
| US6889357B1 (en) * | 2000-05-10 | 2005-05-03 | Micron Technology, Inc. | Timing calibration pattern for SLDRAM |
| CN106575961A (en) * | 2014-09-08 | 2017-04-19 | 高通股份有限公司 | Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems |
| CN106257588A (en) * | 2015-06-19 | 2016-12-28 | 爱思开海力士有限公司 | Semiconductor device and operational approach thereof including delay circuit |
| CN105161487A (en) * | 2015-08-20 | 2015-12-16 | 上海华力微电子有限公司 | Interconnect parasitic resistance and capacitance calibration structure |
| CN112751660A (en) * | 2015-09-01 | 2021-05-04 | 高通股份有限公司 | Method and apparatus for multi-phase clock data recovery circuit calibration |
| WO2017157026A1 (en) * | 2016-03-16 | 2017-09-21 | 珠海全志科技股份有限公司 | Clock duty-cycle calibration and frequency-doubling circuit |
| US10797683B1 (en) * | 2020-03-06 | 2020-10-06 | Faraday Technology Corp. | Calibration circuit and associated calibrating method capable of precisely adjusting clocks with distorted duty cycles and phases |
| CN115461632A (en) * | 2020-04-20 | 2022-12-09 | 普腾泰克斯有限公司 | Die-to-die connectivity monitoring |
| CN111863065A (en) * | 2020-08-04 | 2020-10-30 | 西安紫光国芯半导体有限公司 | ZQ calibrator, ZQ calibration method and memory |
| WO2022262587A1 (en) * | 2021-06-16 | 2022-12-22 | 中兴通讯股份有限公司 | Data transmission method and apparatus, system, electronic device, and readable medium |
| CN115576894A (en) * | 2022-10-27 | 2023-01-06 | 无锡先进技术研究院 | Chiplet core particle based on PCIE standard interface interconnection and interface multiplexing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116825170A (en) | 2023-09-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7272765B2 (en) | Test apparatus and test method for testing plurality of devices in parallel | |
| US7673193B1 (en) | Processor-memory unit for use in system-in-package and system-in-module devices | |
| CN107544923B (en) | Apparatus, and associated method, for controlling access to a memory device | |
| US20060218318A1 (en) | Method and system for synchronizing communications links in a hub-based memory system | |
| JPH0787161A (en) | Method, apparatus and protocol for connection of hierarchy | |
| US8405415B2 (en) | Test apparatus synchronous module and synchronous method | |
| CN116825170B (en) | Automatic calibration architecture and chip for die-to-die interconnect | |
| US10769038B2 (en) | Counter circuitry and methods including a master counter providing initialization data and fault detection data and wherein a threshold count difference of a fault detection count is dependent upon the fault detection data | |
| US9588933B2 (en) | Single wire serial interface master module and method thereof for sampling data information | |
| CN101609714A (en) | The Memory Controller of the access of Digital Television, control store apparatus and method | |
| CN103678249B (en) | Expansion equipment and its clock adjustment method based on memory interface | |
| JPH11265313A (en) | Storage device | |
| US10049763B2 (en) | Semiconductor memory apparatus | |
| TW202206836A (en) | Automated test equipment and method using a trigger generation | |
| KR100829402B1 (en) | Sequential semiconductor test apparatus | |
| JP2000163154A (en) | Method for compensating clock signal phase delay | |
| US11506710B1 (en) | Method for testing a circuit system and a circuit system thereof | |
| US20240104042A1 (en) | Data Processing Method, Apparatus and Storage Medium | |
| CN107193705B (en) | Chip debugging method and device | |
| JP2006170761A (en) | Test system for semiconductor integrated circuit | |
| US11700144B2 (en) | Master slave communication system and control method for master slave communication system | |
| JP2007155619A (en) | Tester and test method | |
| JP2020087179A (en) | Controller and controller control method | |
| JPH02219151A (en) | Computer input/output system and its channel diagnostics | |
| KR102426476B1 (en) | Test apparatus having function for test and timing compensation of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |