JP2006170761A - Test system for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test system for a semiconductor integrated circuit which can respond to a single test or a multitest of a DUT regardless of its pin number, and can reduce a time loss at the multitest by maximally improving utilization efficiency of tester resources. <P>SOLUTION: The test system comprises; a plurality of test units 102 each having a test function executing section 104 which supplies the DUT with a power source and a test pattern and executes its test, and a tester controller 106 which communicates with a host computer 101 and can control the test function executing section 104; a motherboard 103 having a combine bus 107 which connects the plurality of test units 102, a clock generator for synchronization 108 which generates a master clock MC for synchronizations, and a distribution circuit 109 which distributes the master clock MC to respective test units 102; and a transmission route configuring means 111 which configures a transmission route between arbitrary test units 102 by organizing the combine bus 107 based on a command transmitted from the host computer 101. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention is a test system used in a test process of a semiconductor integrated circuit such as an IC or an LSI, and particularly the number of tester pins can be easily expanded. It is related with the test system which can respond | correspond to the test of this, and can operate synchronously or asynchronously in an expansion unit.

  An automatic test system (tester) for a semiconductor integrated circuit such as an IC or LSI applies a signal to each terminal of a device under test (DUT) at a determined timing and detects a signal output from the DUT at a determined timing. Then, the function and performance of the DUT are verified by comparing with the expected value.

  FIG. 8 is a basic configuration diagram of a conventional tester. The tester processor 801 is provided so as to be able to control all the hardware resources in the tester via the tester bus 809, writes a set value to each resource according to a test program, and executes a test while reading the state of each resource. A timing generator (TG) 802 generates a rate signal 810, a clock signal 811 and a strobe signal 812 according to the set values. A pattern generator (PG) 803 generates a logic waveform of a set timing based on a logic value input to each pin of the stored DUT, a rate signal 810 and a clock signal 811, and a pin electronics (pin electronics board) 805 Each driver 813 generates a signal to be converted to a predetermined signal level and applied to each pin of the DUT 808. Further, power is supplied from the device power supply 807 to the DUT 808. The pattern-input DUT 808 outputs a response signal. This output signal is input to each comparator 814 of the pin electronics 805, converted into a logic signal by comparison with the reference level 815, and the logic signal is compared by the comparison circuit 804. A comparison is made at the timing defined by the internal expected value and the strobe signal 812. As a result of the comparison determination, if it matches the expected value, it is PASS (pass), and if it does not match, it is FAIL (fail), and the determination result is stored in the fail memory 806. The determination result is read as a status by the tester processor 801.

  Regarding the configuration of the timing generator (TG) and the pattern generator (PG) in the above prior art, there is a shared resource type architecture in which timing resources are shared by a plurality of pins, and the configuration is shown in FIG. A timing generator (TG) 909 has timing generation resources of a rate generator 901 and clock generators 902 to 905. The pattern generator (PG) 910 has one multiplexer 906 to 908 per pin, and selects a clock signal from each clock generator 902 to 905. This architecture is often used in the era when the components for the timing generator were expensive.

  Further, regarding the configuration of the timing generator (TG) and the pattern generator (PG) in the prior art, there is a per-pin type architecture having an independent timing resource for each pin. FIG. 10 shows the configuration. The per-pin type architecture can set timing with a higher degree of freedom than the shared resource type architecture. Recently, hardware resources including a timing generator (TG) are often realized by a large-capacity FPGA (Field Programmable Gate Array), so the cost per component is reduced and the design is easy. A type architecture is often used.

  FIG. 11 shows a tester architecture called a site type architecture tester. In this architecture, the inside of the tester is divided into sites having a small number of pins of about 50 to 80 pins, and each site has a single tester resource as shown in FIG. The sites are independent and suitable for multi-testing.

  In the mass production test process of semiconductor integrated circuits, it is necessary to cope with the diversification of production model models. However, when a tester that supports multiple pins is used for testing a small number of pin models, multi-testing improves efficiency, but shared resources In the case of a type architecture, the same pattern generator is used, and a time loss such as a time for waiting for completion of another DUT test occurs. In the case of a site-type architecture, the time loss as described above does not occur by operating independently, but the number of pins is fixed, and it is not possible to deal with a model exceeding the number of pins of one site.

In addition, there is a test system disclosed in the following Patent Document 1 in order to solve the problems of the respective architectures. In the test system, by changing the pin configuration inside the tester, a plurality of tests can be executed simultaneously or asynchronously, and multiple tests for different DUTs can be executed simultaneously or asynchronously. However, resources can be limited by changing the internal configuration of a single tester, and the test time may be lost due to restrictions on the total number of pins that can be used.
JP 2001-174522 A

  The present invention has been made in view of the above problems, and is capable of supporting a single test or a multi-test of a device under test irrespective of the number of pins. An object of the present invention is to provide a semiconductor integrated circuit test system capable of reducing the time loss.

  In order to achieve the above object, a semiconductor integrated circuit test system according to the present invention is a semiconductor integrated circuit test system capable of testing one or more devices under test in parallel, and manages the processing of the entire test system And supplying a power to the device under test, applying a predetermined test pattern, receiving a response from the device under test, and comparing the response with a predetermined expected value. A plurality of test units each having a test function execution unit for evaluating the test function, a tester control unit connected to the host computer via a communication line and capable of controlling the test function execution unit, and the plurality of test units A combine bus connected to enable mutual communication; a synchronization clock generation circuit for generating a synchronization master clock; A command transmitted from the host computer includes a motherboard having a distribution circuit for distributing a clock to the plurality of test units, and a transmission path between arbitrary test units of the plurality of test units formed by the combine bus. Transmission path configuration means configured on the basis of the transmission path configuration means.

  According to the semiconductor integrated circuit test system having the above characteristics, even if the number of pins that can be tested by one test unit is small and the number of pins of the device under test is larger, the configuration of the combine bus is changed by the transmission path configuration means. By sharing the master clock, the number of test units that can send and receive commands and data to each other can be set arbitrarily, so that test units that operate simultaneously can be associated with devices under test that have a large number of pins. It becomes possible to test. In other words, without changing the configuration of the test unit, it is possible to arbitrarily set the configuration of the test unit that operates synchronously at the same time by changing the configuration of the combine bus. In addition, it can flexibly support testing of multi-pin devices.

  Further, since each test unit includes a tester control unit, it is possible to minimize test time overhead. Furthermore, even if each test unit is a shared resource type architecture, the time loss at the time of multi-test can be avoided by setting the number of pins of each test unit in advance according to the small pin device.

  Furthermore, by optimizing the number of testable pins in the test unit to a small number, it is possible to easily realize the optimal test unit configuration for devices under test with various pin counts, greatly improving the tester hardware utilization efficiency. This improves the tester investment efficiency.

  In the semiconductor integrated circuit test system having the above characteristics, the test unit includes a local clock generation circuit that generates a local clock, and a clock switching unit that switches an input of the local clock and the master clock supplied from the motherboard. It is preferable. As a result, the test can be executed asynchronously for each test unit independently of other test units.

  More preferably, in the semiconductor integrated circuit test system having the above characteristics, when the test unit is operating in synchronization with the master clock, the test function execution unit is independent of the other test units. And selecting means for selecting whether to start and end the test or to start and end the test in synchronization with the other test units. As a result, when the test function execution unit starts and ends the test independently of other test units, the test unit can independently perform a unit test of a small pin device. When starting and ending tests in synchronization with other test units, a multi-pin device unit test corresponding to the total number of pins of a plurality of test units operating in synchronization, or multiple low-pin device simultaneous tests Can be done.

  More preferably, in the semiconductor integrated circuit test system having the above characteristics, each of the test units is connected to another test unit via the combine bus in a synchronous mode in which the test function execution unit operates in synchronization with the master clock. And a command or data transmission / reception function. More preferably, in the semiconductor integrated circuit test system having the above characteristics, each of the test units is connected to another test unit via the combine bus in a synchronous mode in which the test function execution unit operates in synchronization with the master clock. It is configured to be able to receive data indicating the test status.

  Accordingly, when one of the plurality of test units operating in synchronism sends a test start command as a master test unit to another test unit via the transmission path formed by the combine bus, the master test unit and the test start command The other test units that have received can simultaneously start the same test in synchronization with the master clock. Similarly, when one of a plurality of test units operating in synchronization finishes the test by FAIL, the master test unit transmits all the data to the master test unit so that the master test unit operates all the test units operating in synchronization. A test end command can be transmitted to all the test unit master clocks, and the test can be completed at the same time.

  More preferably, in the semiconductor integrated circuit test system according to the above feature, the plurality of test units are configured such that a part of the plurality of test units is connected via the combine bus in a synchronous mode in which the test function execution unit operates in synchronization with the master clock. When data indicating the test end of the test unit is received, the configuration of the test unit that operates in synchronization can be dynamically changed. As a result, the test unit that has become free can be used for another test, so that the test efficiency is improved.

  More preferably, in the semiconductor integrated circuit test system having the above characteristics, a part of the combine bus is used as a master clock line for distributing the master clock to the plurality of test units. Wired to the unit at an equal length. Thereby, the timing accuracy of the master clock received by each test unit is improved, so that a test with higher time resolution is possible.

  More preferably, in the semiconductor integrated circuit test system having the above characteristics, the mother board includes an expansion connector for connecting the combine bus to another mother board. As a result, testing of multi-pin devices that cannot be supported by the number of test units that can be connected to one motherboard can add test units by adding motherboards. It becomes possible to respond by simply adding more.

  Next, an embodiment of a semiconductor integrated circuit test system according to the present invention (hereinafter referred to as “the present system” as appropriate) will be described with reference to the drawings.

  FIG. 1 shows the basic configuration of the system of the present invention. As shown in FIG. 1, a host computer 101, a plurality of test units 102, and a motherboard 103 are provided.

  The host computer 101 manages the processing of the entire system of the present invention. Each test unit 102 supplies power to a device under test (DUT) 207 (see FIG. 2), applies a predetermined test pattern, receives a response output from the DUT 207, receives the response output and a predetermined output. The test function execution unit 104 that compares the expected value and evaluates the DUT 207 is connected to the host computer 101 via the communication line 105 (for example, Ethernet (registered trademark)) to control each resource of the test function execution unit 104 A possible tester controller 106 (corresponding to a tester control unit) is provided.

  As shown in FIG. 2, the test function execution unit 104 uses, as tester resources, a timing generator (TG) 201, a pattern generator (PG) 202, a pin element (pin) as in the conventional basic tester configuration shown in FIG. (Electronic board) 203, a comparison circuit 204, a fail memory 205, a device power source 206, and the like, and operate according to a test program under the control of the tester controller 106. With this configuration, the test function execution unit 104 supplies power to the device under test (DUT) 207, applies a predetermined test pattern, receives a response output from the DUT 207, receives the response output and the predetermined output. The test function of evaluating the DUT 207 by comparing with the expected value is exhibited. Each tester resource of the test function execution unit 104 is the same as that of the conventional tester basic configuration shown in FIG.

  The motherboard 103 includes a combine bus 107 that connects the plurality of test units 102 so that the plurality of test units 102 can communicate with each other, and a synchronization clock generation circuit 108 that generates a master clock MC for synchronization. And a distribution circuit 109 that distributes the master clock MC to the plurality of test units 102. Here, as shown in FIG. 3, the distribution circuit 109 converts the signal level from the LVTTL level to the LVPECL level, converts the signal level from the LVPECL level to the LVDS level, and has the same number as the test units 102 to be connected. The driver 302 that distributes to the output has a two-stage configuration, and the master clock MC of the LVDS level distributed and output from the driver 302 is distributed to each test unit 102 using a part of the combine bus 107. The lengths of the signal lines from the driver 302 to each test unit 102 are set to be equal to each other. As a result, the master clock MC generated by the synchronization clock generation circuit 108 reaches each test unit 102 at the same time, so that an accurate synchronization operation can be performed between the test units 102.

  The motherboard 103 includes an expansion connector 110 for connecting the combine bus 107 to a combine bus of another motherboard (not shown) so that the test unit 102 can be added, and the motherboard 103 can be added. ing. When the mother board 103 is added, the master clock MC and the combine bus 107 are shared between the plurality of mother boards through the expansion connector 110.

  Each test unit 102 also has a bus organization circuit 111 (transmission) configured by controlling the tester controller 106 based on a command transmitted from the host computer 101 on a transmission path between arbitrary test units 102 formed by the combine bus 107. Each corresponding to a route constructing means). In this embodiment, in order to enable high-speed signal transmission, the combine bus 107 is configured by an LVDS bus (Low Voltage Differential Signaling Bus) configured by a multi-drop method. As shown in FIG. 4, the bus organization circuit 111 is configured by connecting a series circuit of a terminating resistor 401 and a switch 402 of the LVDS bus between signal lines for each pair of differential signals. In FIG. 4, reference numeral 403 represents an LVDS driver / receiver provided in each test unit 102.

  Further, as shown in FIG. 1, each test unit 102 includes a local clock generation circuit 112 that generates a local clock LC, and a clock switching unit 113 that switches input of the local clock LC and the master clock MC supplied from the motherboard 103. Prepare.

  With the above configuration, the system according to the present invention has a configuration in which a plurality of test units 102 can be arbitrarily connected via the combine bus 107 with respect to the conventional basic tester configuration, and each test unit 102 has a local clock LC. 1) Execution of single / multiple test pattern synchronous or asynchronous test in multi-pin device test, 2) Multiple synchronous or asynchronous test of multiple same small pin devices Execution 3) Functions as a tester that can handle multiple synchronous or asynchronous tests of a plurality of different small pin devices.

  A method for configuring a transmission path between the test units 102 on the combine bus 107 by the bus organization circuit 111 will be briefly described. In the following description, an eight test unit configuration is assumed.

  FIG. 5 schematically shows an example of organization by one master test unit M and seven slave test units S1 to S7 in a table format. In FIG. 5, BUS 1 to 8 indicate LVDS bus lines for command or data transmission of the combine bus 107. The master test unit M and the seven slave test units S1 to S7 are assumed to be connected to the master test unit M on one end side of the combine bus 107 and the slave test unit S7 on the other end side of the combine bus 107. To do. BUS1 is an LVDS bus for issuing commands from the LVDS driver of the master test unit M to the seven slave test units S1 to S7, and termination processing is performed in the bus organization circuit 111 of the slave test unit S7. BUS 2 to 8 are LVDS buses that issue commands to the master test unit M from the LVDS drivers of the slave test units S 1 to S 7, and termination processing is performed in the bus organization circuit 111 of the master test unit M. Termination processing in each test unit 102 is realized by closing the switch 402 of the corresponding bus organization circuit 111 under the control of the tester controller 106. With the organization shown in FIG. 5, eight test units 102 can be integrated to perform a synchronous test operation.

  FIG. 6 schematically shows an example of organization by two master test units M1, M2 and six slave test units S11-S13, S21-S23, which are examples of organization of other test units 102, in a table format. As in the organization example in FIG. 5, BUS 1 to 8 indicate LVDS bus lines for the command or data transmission of the combine bus 107. Further, it is assumed that the master test unit M1 is connected on one end side of the combine bus 107 and the slave test unit S23 is connected on the other end side of the combine bus 107. BUS1 is an LVDS bus that issues commands from the LVDS driver of the master test unit M1 to the three slave test units S11 to S13, and termination processing is performed in the bus organization circuit 111 of the slave test unit S13. BUS2-4 are LVDS buses that issue commands from the LVDS drivers of the slave test units S11-S13 to the master test unit M1, and termination processing is performed in the bus organization circuit 111 of the master test unit M1. BUS5 is an LVDS bus that issues commands from the LVDS driver of the master test unit M2 to the three slave test units S21 to S23, and termination processing is performed in the bus organization circuit 111 of the slave test unit S23. BUS6-8 are LVDS buses that issue commands from the LVDS drivers of the slave test units S21-S23 to the master test unit M2, and termination processing is performed in the bus organization circuit 111 of the master test unit M1. Termination processing in each test unit 102 is realized by closing the switch 402 of the corresponding bus organization circuit 111 under the control of the tester controller 106. With the organization shown in FIG. 6, two test unit groups that perform a synchronous test operation together with four test units 102 are configured, and each test unit group can perform a test operation independently of each other.

  When an arbitrary test unit 102 of a plurality of test units 102 is operated independently and asynchronously independently from other test units 102, the test unit 102 is not connected to the combine bus 107, and the tester controller The clock switching means 113 is switched under the control of 106 so that the local clock LC generated by the local clock generation circuit 112 in the test unit 102 is used.

  Next, an operation example of the system of the present invention having the configuration shown in FIG. 1 will be described with reference to the flowchart of FIG.

  Step # 1: According to the combine information set in advance in the test plan, the host computer 101 transmits information to the tester controller 106 of each test unit 102 via the communication line 105.

  Step # 2: The tester controller 106 is configured to synchronize the two test units according to the information, and is configured to synchronize the four test units. Similarly, the tester controller 106 synchronizes any number of test units such as eight or sixteen. In order to adopt the configuration, the setting information of the master test unit and the slave test unit is acquired. Note that there is only one master test unit in a test unit group that generates a pattern synchronously.

  Step # 3: In order to organize the test unit group, a transmission path between the test units 102 by the combine bus 107 is configured. Specifically, termination processing of the bus organization circuit 111 in the test unit 102 corresponding to each bus of the combine bus 107 is performed.

  Step # 4: The tester controller 106 performs setting for selection of a clock for driving the timing generator 201 and the pattern generator 202 of the test function execution unit 104. The clock switching means 113 is set so as to select the local clock LC in the case of asynchronous operation and to select the master clock MC in the case of synchronous operation. As described above, the preparation for pattern generation is completed by the processing of steps # 1 to # 4.

  Step # 5: The master test unit transmits a pattern generation start command to the combine bus 107. This command is simultaneously transmitted to all the slave test units in the synchronization group (a group of test units performing the same synchronization operation) through the organized combine bus 107. If the number of synchronization groups is large, there will be a time difference until the command arrives, but there will be no problem of synchronization deviation within one clock period of the master clock MC. With this start command, all the test units of the master and slave start pattern generation at the same time. Thereafter, the master test unit acquires the end of the test of the slave test unit through the combine bus 107. The master test unit confirms the test completion of all the test units in the synchronization group, thereby completing the test and notifying the host computer 101 of the completion of the test.

  When the master test unit confirms the end of the test by the function test FAIL of any one test unit in the synchronization group, the master test unit stops generating its own pattern and all the slave test units in the synchronization group. Is issued to all slave test units at the same time. The slave test unit that has received the pattern stop command stops pattern generation. The master test unit notifies the host computer 101 of the end of the test by the function test FAIL.

  Step # 6: The host computer 101 can reconstruct the configuration of the combine bus 107 after the test of the test units 102 of all the synchronization groups is completed.

  Although the configuration and operation of the system of the present invention have been described in detail above, the configurations of the test unit 102, the motherboard 103, the combine bus 107, and the bus organization circuit 111 are not necessarily limited to the configurations of the above-described embodiments.

The block diagram which shows the basic composition in one Embodiment of the semiconductor integrated circuit test system which concerns on this invention 1 is a circuit diagram showing a configuration example of a test function execution unit of a semiconductor integrated circuit test system according to the present invention; 1 is a circuit diagram showing a configuration example of a clock generation circuit for synchronization and a distribution circuit in a semiconductor integrated circuit test system according to the present invention; 1 is a circuit diagram showing a configuration example of a bus organization circuit of a semiconductor integrated circuit test system according to the present invention; The figure which shows typically the organization example of the combine bus | bath in the semiconductor integrated circuit test system which concerns on this invention The figure which shows typically the other organization example of the combine bus in the semiconductor integrated circuit test system which concerns on this invention The flowchart which shows the operation example in one Embodiment of the semiconductor integrated circuit test system based on this invention Block diagram showing an example of the basic configuration of a conventional automatic test system for semiconductor integrated circuits Block diagram showing a configuration example of a shared resource type architecture in a conventional automatic test system for semiconductor integrated circuits Block diagram showing a configuration example of a per-pin type architecture in a conventional automatic test system for semiconductor integrated circuits A block diagram showing a configuration example of a site type architecture tester in a conventional automatic test system for semiconductor integrated circuits

Explanation of symbols

101: Host computer 102: Test unit 103: Motherboard 104: Test function execution unit 105: Communication line 106: Tester controller (tester control unit)
107: Combine bus 108: Synchronous clock generation circuit 109: Distribution circuit 110: Expansion connector 111: Bus organization circuit (transmission path configuration means)
112: Local clock generation circuit 113: Clock switching means 201: Timing generator (TG)
202: Pattern generator (PG)
203: Pin electronics (pin electronics board)
204: Comparison circuit 205: Fail memory 206: Power supply for device 207: Device under test (DUT)
301, 302: Driver 401: Terminating resistor 402: Switch 403: LVDS driver / receiver 801: Tester processor 802, 909, 1008: Timing generator (TG)
803, 910, 1009: Pattern generator (PG)
804: Comparison circuit 805, 911, 1010: Pin electronics (pin electronics board)
806: Fail memory 807: Device power supply 808: Device under test (DUT)
809: Tester bus 810: Rate signal 811: Clock signal 812: Strobe signal 813: Driver 814: Comparator 815: Reference level 901, 1001: Rate generator 902-905, 1002-1004: Clock generator 906-908: Multiplexer LC: Local clock MC: Master clock M, M1, M2: Master test units S1 to S7, S11 to S13, S21 to S23: Slave test units

Claims (8)

A semiconductor integrated circuit test system capable of testing one or more devices under test in parallel,
A host computer that manages the entire test system;
Supply power to the device under test, apply a predetermined test pattern, receive a response from the device under test, compare the response with a predetermined expected value, and evaluate the device under test A plurality of test units each having a test function execution unit, a tester control unit connected to the host computer via a communication line and capable of controlling the test function execution unit,
A motherboard having a combine bus that connects the plurality of test units so as to communicate with each other, a synchronization clock generation circuit that generates a synchronization master clock, and a distribution circuit that distributes the master clock to the plurality of test units. When,
Transmission path configuration means configured to configure a transmission path between arbitrary test units of the plurality of test units formed by the combine bus based on a command transmitted from the host computer;
A semiconductor integrated circuit test system comprising:   2. The semiconductor according to claim 1, wherein the test unit includes a local clock generation circuit that generates a local clock, and a clock switching unit that switches an input of the master clock supplied from the local clock and the motherboard. Integrated circuit test system.   While the test unit is operating in synchronization with the master clock, the test function execution unit starts and ends a test independently of the other test units, or other test 3. The semiconductor integrated circuit test system according to claim 1, further comprising selection means for selecting whether to start and end the test in synchronization with the unit.   Each test unit has a function of transmitting or receiving a command or data to or from another test unit via the combine bus in a synchronous mode in which the test function execution unit operates in synchronization with the master clock. The semiconductor integrated circuit test system according to any one of claims 1 to 3.   Each of the test units is configured to be able to receive data indicating the test status of another test unit via the combine bus in a synchronous mode in which the test function execution unit operates in synchronization with the master clock. The semiconductor integrated circuit test system according to claim 1, wherein the test system is a semiconductor integrated circuit test system.   When the plurality of test units receive data indicating the end of tests of some of the test units via the combine bus in the synchronous mode in which the test function execution unit operates in synchronization with the master clock, The semiconductor integrated circuit test system according to claim 1, wherein the configuration of the test unit operating in synchronization can be dynamically changed.   A part of the combine bus is used as a master clock line for distributing the master clock to the plurality of test units, and is wired from the distribution circuit to each test unit at an equal length. The semiconductor integrated circuit test system according to claim 1.   The semiconductor integrated circuit test system according to claim 1, wherein the motherboard includes an expansion connector that connects the combine bus to another motherboard.

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