CN115841089A

CN115841089A - System-on-chip verification platform and verification method based on UVM

Info

Publication number: CN115841089A
Application number: CN202310168843.1A
Authority: CN
Inventors: 舒杰敏; 杨善宝
Original assignee: Hefei Hexagonal Semiconductor Co ltd
Current assignee: Hefei Hexagonal Semiconductor Co ltd
Priority date: 2023-02-27
Filing date: 2023-02-27
Publication date: 2023-03-24
Anticipated expiration: 2043-02-27
Also published as: CN115841089B

Abstract

The invention discloses a system-on-chip verification method and a platform based on UVM, wherein the method comprises the following steps: building a UVM simulation test environment; generating a module file and a test case, and creating a test path; performing RTL stage verification and gate-level netlist stage verification, and performing verification judgment; the register adapter is reloaded during the verification of the gate-level netlist stage, the operation excitation sequence of the register model is converted and coded, the read-write operation, the address and the value of the register model are represented, the read-write operation, the address and the value of the register model are stored in a fixed address area of the storage unit and matched with the CPU to execute a fixed C code program, and the access to the register and the storage unit in the system-level chip to be verified is completed. The invention can reuse the UVM test case in the RTL stage in the gate-level netlist stage without redeveloping the test case, greatly accelerates the simulation verification of the system-level chip from the RTL stage to the gate-level netlist stage, and effectively reduces the time and labor cost.

Description

System-on-chip verification platform and verification method based on UVM

Technical Field

The invention relates to the technical field of chip verification, in particular to a system-level chip verification platform and a verification method based on UVM.

Background

The system-level chip simulation verification means that a chip is stimulated through an EDA tool to simulate the actual operation scene of the chip, so that the defects of the chip design are found out, the design of the chip is verified to meet the specifications or requirements, and the performance of a product is improved. Before chip tape-out, a large amount of sufficient verification is carried out, so that the cost caused by chip tape-out failure can be effectively reduced.

One way in the existing system-level chip verification technology is as follows: the C code program is compiled into machine codes which can be executed by the CPU through the compiler, the CPU executes the test codes, the tested system level chip is configured, the generation of the platform control excitation is verified, and the simulation is coordinated to be performed and finished. But the C code program cannot make the test case random. Therefore, only direct testing, i.e., excitation of a fixed configuration of the system under test, can be performed. Thus, to achieve complete coverage, it takes a lot of time and labor to construct a lot of direct tests, which affects project schedule. Meanwhile, some extreme scenarios cannot be constructed by direct testing, which affects the collection of complete test coverage. Moreover, because the CPU executes the simulation of the C program configuration chip, the debugging is not easy, and the verification efficiency is influenced.

On the other hand, the existing system-on-chip Verification technology can not only construct a random test case, but also adopt an object-oriented Verification design by using a Verification platform based on a Universal Verification Methodology (UVM). However, the system level chip is in a gate level netlist, and due to the insertion of a test chain and a time delay, the bus cannot be accessed and configured through a CPU model, and in addition, the gate level netlist stage needs to use an actual CPU netlist and a time delay for simulation.

Disclosure of Invention

In order to solve the technical problems in the background art, the invention provides a verification method and a verification platform for a system-level chip based on UVM (Universal verification methodology), and provides a reusable test case and coverage rate convergence platform and method for the system-level chip from an RTL (real time language) stage to a gate-level netlist stage, so that the quick convergence verification time is realized, and the work tasks of verification personnel are reduced.

For better understanding of the technical solution of the present invention, some terms are explained as follows:

IP: the Intellectual Property, IP, is a completely designed and verified component with certain function for chip integration designers to choose, and a plurality of IP core modules are generally integrated in the SOC.

UVM: universal Verification Methodology, general Verification Methodology.

Coverage rate: coverage, coverage is one of the indicators that verify the integrity and validity characterization.

Register model: register Model, which is a class of UVM abstraction to registers in the chip.

Register adapter: the Register Adapter realizes the conversion between the read-write access of the Register through the Register Model and the CPU agent transaction in the test case.

The CPU agent: the bus access function is realized through a virtual interface (virtual interface) based on the UVM, and the abstract UVM Transaction is converted into a specific interface bus protocol time sequence.

Design Under Test, design to be verified in RTL stage or gate-level netlist stage.

The invention provides a system-on-chip verification platform based on UVM, which comprises: a DUT and a UVM platform;

the DUT comprises a system-on-chip to be verified, wherein the system-on-chip to be verified comprises a central processing unit, a plurality of IP core modules, a storage unit and a bus; the central processing unit, the plurality of IP core modules and the storage unit are all connected to the bus;

the UVM platform comprises a CPU agent, a plurality of IP agents, a register adapter, a register model, a test sequence library and a scoring board; the CPU agent and the plurality of IP agents are provided with virtual interfaces which can be connected with the bus; the test sequence library, the register model, the register adapter and the CPU agent are connected in sequence, and the score counting board is connected with the IP agent.

Preferably, the test sequence library comprises a plurality of test sequences, the plurality of test sequences can be called and combined into different test cases, and a register model is called to form a register operation item;

the register adapter is used for converting the excitation sequence in the register operation item into an abstract CPU transaction supporting a bus protocol;

the CPU agent is used for converting the CPU transaction into a specific bus protocol time sequence and accessing the bus through a virtual interface.

Preferably, the CPU agent includes a CPU driver, and the register adapter reload is implemented by reloading the CPU driver.

Preferably, the scoreboard comprises a reference model for providing reference transactions;

and the score counting board is used for receiving the transaction sent by the IP agent, comparing the transaction with a reference transaction provided by a reference model and determining whether the DUT is abnormal or not.

Preferably, the IP agent is used for timing information and transaction conversion.

The invention also provides a system-on-chip verification method based on UVM, which comprises the following steps:

building a UVM simulation test environment;

generating a module file and a test case, and creating a test path;

performing RTL stage verification and gate-level netlist stage verification, and performing verification judgment;

the register adapter is reloaded during the gate-level netlist stage verification, an operation excitation sequence of the register model is converted and encoded, read-write operation, an address and a value of the register model are represented, the read-write operation, the address and the value of the register model are stored in a fixed address area of the storage unit and are matched with the CPU to execute a fixed C code program, and access to a register and the storage unit in a system-level chip to be verified is completed.

Preferably, the reload register adapter specific operations comprise:

waiting for the CPU to execute SYNC, and writing a preset arbitrary value into a first address of a storage unit;

judging the operation type of the register by the excitation sequence;

if the excitation sequence is the write operation of the register, correspondingly placing the address and the data in the excitation sequence to the address of the storage unit as a third address and a second address through the access of a register model back door of the UVM, and returning to wait for the CPU to write SYNC after the CPU writes the processed new data into the second address after executing the program;

and if the excitation sequence is read for the register, the address in the excitation sequence is put to a storage unit address as a first address through the back door access of a register model of the UVM, after the CPU reads data from the first address and executes a program, the processed new data is written into the second address, and the adapter returns the new data to the register model.

Preferably, the CPU executing the fixed C code program includes:

the CPU writes SYNC to the first address, reads the value OP of the second address, and if OP equals NOP, continues to write SYNC to the first address

If the OP value indicates the bus write operation, the CPU reads the data stored in the third address and the data of the fourth address, writes new data by taking the data read from the third address as an address through the bus after executing a corresponding program, and returns to write SYNC to the first address;

if the OP value indicates a bus read operation, the CPU reads the data stored at the third address, then reads the data stored at the address with the data as the address, then writes the data to the fourth address, and returns to writing SYNC to the first address.

Preferably, performing the RTL phase verification comprises: and newly building a UVM random test case, accessing a chip bus through the register model by the UVM random test case, controlling the IP core modules in the chip, realizing the test of each IP core module or the combination thereof, and collecting the coverage rate and the passing rate.

Preferably, performing gate level netlist stage verification comprises:

a reload register adapter;

debugging the value stored by the fixed address of the C program polling storage unit executed by the CPU, decoding and executing the corresponding bus operation, and writing the bus operation back to the fixed address of the storage unit;

multiplexing or selecting UVM random test cases at an RTL stage, wherein the UVM random test cases access a chip bus through a register model, control IP core modules in the chip, realize the test of each IP core module or the combination thereof, and collect coverage rate and pass rate.

The invention is based on UVM verification platform, combines CPU to execute special C program, quickly constructs random test case and collects coverage rate in RTL stage, to ensure completeness of test case and integrity and error-free of system-level chip; in the stage of gate-level netlist, the fixed code is executed by the CPU unit through overloading the register adapter and overloading the UVM verification platform environment, so that the UVM test case in the RTL stage is multiplexed without redeveloping the test case, the simulation verification of the system-level chip from the RTL stage to the stage of gate-level netlist is greatly accelerated, and the time and labor cost are effectively reduced.

Drawings

FIG. 1 is a UVM based verification platform in the RTL phase in an embodiment of the present invention;

FIG. 2 is a UVM based test platform at the gate level netlist stage in the embodiment of the present invention;

FIG. 3 is a flowchart illustrating the execution of the register adapter after a reload according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating a process of executing a program C by a CPU according to an embodiment of the present invention;

FIG. 5 is a flowchart illustrating a verification method from an RTL stage to a gate-level netlist stage according to an embodiment of the present invention.

Detailed Description

Fig. 1 is a UVM-based verification platform in an RTL phase according to an embodiment of the present invention; FIG. 2 is a UVM based test platform at the gate level netlist stage in an embodiment of the present invention.

Referring to fig. 1-2, an embodiment of the present invention provides a UVM-based system-on-chip verification platform, including: a DUT and a UVM platform.

It can be understood that the DUT, as a design under test, includes a system on chip that needs to be verified; the UVM platform provides a simulation environment, and the functions of the system-level chip are tested through the simulation environment. The system-on-chip to be verified comprises a Central Processing Unit (CPU), a plurality of IP core modules (for example, IP1, IP2, … …, IPn), a storage unit and a bus, wherein each IP core module IP1, IP2, … …, IPn is respectively connected to the bus, and each IP core module IP1, IP2, … …, IPn is a component with a certain specific function.

It is to be noted that the system on chip to be verified may comprise one or more central processor units, e.g. CPU0, CPU1, … …, CPUk, each of said central processor units CPU0, CPU1, … …, CPUk being connected to said bus. In the present embodiment, a single central processing unit is taken as an example.

The simulation environment comprises a software test case, a universal verification methodology test case (UVM case) and a bus function model unit, wherein the software test case is a software code (C program) written by adopting C language, and the universal verification methodology test case is a test code written by adopting a universal verification methodology. The bus function model unit is composed of a register model, a register adapter and a CPU agent in the embodiment; and binding to the same interface of the central processing unit connected with the bus.

The software test case and the universal verification methodology test case are formed by calling the test sequence in the test sequence library, and are processed by the bus function model unit, and then the system level chip to be verified is accessed through the bus. The method can be as follows: the test sequence library comprises a plurality of test sequences which can be called and combined into different test cases, and a register model is called to form a register operation item; the register adapter is used for converting the excitation sequence in the register operation item into an abstract CPU transaction supporting a bus protocol; the CPU agent is used for converting the CPU transaction into a specific bus protocol time sequence and accessing the bus through a virtual interface.

In the present embodiment, the test sequence library is designed as a collection of test sequences for various test scenarios. uvm _ test realizes each reasonable test case by calling and combining each test sequence (sequence _1, sequence _2 … sequence _ n) in the test sequence library. The register model is an abstract Class (Class) of a register and a storage unit in a Design Under Test (DUT) by the UVM, and a test sequence generates a register operation item of UVM internal abstract through calling methods (such as reading and writing) of the abstract Class register model and delivers the register operation item to the register adapter. The register adapter converts an excitation sequence in the UVM register model into an abstract CPU transaction supporting a specific bus protocol, then the CPU transaction is handed to the CPU agent, and then the CPU agent converts the abstract CPU transaction into a specific bus protocol time sequence to finish the access to the design bus to be tested. The CPU agent is connected with the bus inside the design to be tested through the virtual interface to realize the access to the bus. Finally, the test sequence completes the access to the design bus to be tested by calling the register model. And the scoreboard receives the affairs sent by each IP agent, compares each affair with the reference affair provided by the internal reference model of the scoreboard, if the affairs are consistent, the function of the equipment to be tested is normal, and otherwise, the function of the equipment to be tested is abnormal. The IP proxy is connected to the signal corresponding to the DUT through the corresponding virtual interface, and the IP proxy functions include but are not limited to: (1) The affairs sent by the driving test sequence are converted into level signals supported by the corresponding IP core; (2) And detecting the time sequence information of the virtual interface, converting the time sequence information into a transaction, sending the transaction to a scoreboard for comparison, and judging whether the comparison is successful or not.

Referring to FIGS. 3-5, FIG. 3 is a flow chart illustrating the execution of the register adapter after a reload according to an embodiment of the present invention; FIG. 4 is a flowchart illustrating a process of executing a program C by a CPU according to an embodiment of the present invention; FIG. 5 is a flowchart illustrating a verification method from an RTL stage to a gate-level netlist stage according to an embodiment of the present invention. Based on the UVM-based system-on-chip verification platform, an embodiment of the present invention further provides a UVM-based system-on-chip verification method, including:

building a UVM simulation test environment;

generating a module file and a test case, and creating a test path;

In the embodiment, a UVM simulation test environment is set up; generating a module file and a test case, and creating a test path; the verification platform embodiment has been described, and details are not repeated here, and the RTL stage verification and the gate-level netlist stage verification are described as follows:

in the RTL verification stage, in order to develop a test case quickly, firstly, a CPU agent is used for replacing an actual CPU in a design to be tested and is connected to a bus through a virtual interface, and the CPU agent also converts CPU transactions into level signals of a specific bus protocol. The register adapter converts the register operation excitation sequence abstracted in the UVM into a CPU transaction corresponding to the CPU agent. The register and the memory unit in the design to be tested are abstracted into a register model, such as the physical address and bit width of the register, and the address and bit width of the memory. And the test sequences in the test scene sequence library access the bus of the design to be tested through the register model. The random test cases complete the development of each specific test case by combining and calling the sequences in the test sequence library, and the convergence of the coverage rate is completed by using a standard UVM methodology.

At the stage of the gate-level netlist, because the test signal and the time delay information are inserted into the gate-level netlist, the CPU in the actual design to be tested cannot be replaced by the CPU agent, and the actual CPU netlist needs to be subjected to time sequence simulation. In order to establish a test case and a sequence library in an RTL stage, an operation excitation sequence of a register model is converted and encoded only by reloading a register adapter to represent read-write Operation (OP), an Address (ADDR) and a value (DATA) of the register model, and a back gate stores the operation excitation sequence into a fixed address area (A, B, C, D) of a storage unit and cooperates with a CPU to execute a fixed C code program to finish access to a register and the storage unit in a design to be tested. The original register model, the test sequence library, the scoreboard and the IP agent in the UVM platform all multiplex codes in the RTL stage.

In the stage of the gate-level netlist, the execution flow of the register adapter after reloading is shown in fig. 3, if the test case has a read-write operation request for the register, the CPU driver detects and waits for the CPU to execute the first write SYNC step, that is, the CPU writes an arbitrary preset fixed value into the fixed address region;

if the excitation sequence is write operation on the register, correspondingly placing an Address (ADDR) and DATA (DATA) in the excitation sequence to positions C and D of a storage unit through the register model back-gate access of the UVM, and returning to the CPU to wait for writing SYNC after the CPU finishes executing a program to write the processed new DATA into the ADDR;

if the stimulus sequence is a read operation to the register, the address ADDR in the stimulus sequence is put to the memory location address C through the register model back-gate access of UVM, the CPU is waited to finish reading the address ADDR, and the DATA is written into the address D, and the adapter returns the new DATA to the register model.

In the gate level netlist stage, the CPU executes a C program flow as shown in fig. 4. And the CPU executes a loop program, and in the first step, the CPU writes SYNC to an address A, reads the value OP of an address B, and continues to execute the first step if the value OP is equal to NOP.

If the OP value indicates a bus write operation, executing the fifth step of the CPU reading the ADDR value stored at address C and reading the DATA value at address D, then executing the sixth step of writing the DATA value through the bus with the DATA read from address ADDR as an address, returning to the first step;

if the OP value indicates a bus read operation, then the seventh step is performed, the CPU reads the ADDR value stored at address C, then the eighth step is performed to read the value DATA stored at bus address ADDR, then the ninth step is performed to write DATA at address D, returning to the first step.

It is obvious to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to perform all or part of the above described functions. For the specific working process of the device described above, reference may be made to the corresponding process in the foregoing method embodiment, which is not described herein again.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims

1. A UVM-based system-on-chip verification platform is characterized by comprising: a DUT and a UVM platform;

the UVM platform comprises a CPU agent, a plurality of IP agents, a register adapter, a register model, a test sequence library and a score board; the CPU agent and the plurality of IP agents are provided with virtual interfaces which can be connected with the bus; the test sequence library, the register model, the register adapter and the CPU agent are connected in sequence, and the score counting board is connected with the IP agent.

2. The UVM-based system-on-chip verification platform of claim 1, wherein the test sequence library comprises a plurality of test sequences, the plurality of test sequences can be called and combined into different test cases, and the register model is called to form a register operation item;

3. The UVM-based system on chip verification platform of claim 2, wherein the CPU agent includes a CPU driver, and wherein register adapter reloading is enabled by reloading the CPU driver.

4. The UVM-based system on chip verification platform of claim 1, wherein the scoreboard includes a reference model, the reference model to provide a reference transaction;

5. The UVM-based system on a chip verification platform of claim 1, wherein the IP agent is configured to perform timing information and transaction conversion.

6. A system-on-chip verification method based on UVM is characterized by comprising the following steps:

building a UVM simulation test environment;

generating a module file and a test case, and creating a test path;

the register adapter is reloaded during the verification of the gate-level netlist stage, the operation excitation sequence of the register model is converted and coded, the read-write operation, the address and the value of the register model are represented, the read-write operation, the address and the value of the register model are stored in a fixed address area of the storage unit and matched with the CPU to execute a fixed C code program, and the access to the register and the storage unit in the system-level chip to be verified is completed.

7. The UVM-based system on chip verification method of claim 6, wherein the reload register adapter specific operations comprise:

judging the operation type of the register by the excitation sequence;

and if the excitation sequence is the read operation of the register, the address in the excitation sequence is put into the storage unit address as a first address through the access of a register model back door of the UVM, after the CPU reads data from the first address and executes a program, the processed new data is written into the second address, and the adapter returns the new data to the register model.

8. The UVM-based system on chip verification method of claim 6, wherein the CPU executing the fixed C-code program includes:

writing SYNC to the first address by the CPU, reading the value OP of the second address, and if the OP is equal to NOP, continuing to write SYNC to the first address;

9. The UVM-based system on chip verification method of claim 6, wherein performing RTL phase verification includes: and newly building a UVM random test case, accessing a chip bus through the register model by the UVM random test case, controlling the IP core modules in the chip, realizing the test of each IP core module or the combination thereof, and collecting the coverage rate and the passing rate.

10. The UVM-based system on chip verification method of claim 6, wherein performing gate level netlist stage verification includes:

a reload register adapter;