CN105930242B - A kind of multi-core processor random verification method and device for supporting accurate memory access detection - Google Patents
A kind of multi-core processor random verification method and device for supporting accurate memory access detection Download PDFInfo
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Abstract
The present invention proposes a kind of multi-core processor random verification method and its device for supporting accurate memory access detection, the method comprising the steps of 1, user in multi-core processor to be verified is constrained and is combined with instruction database, is generated there are the concurrent program of memory access conflict as verification vectors；Runtime verification vector, records the implementing result of verification vectors and the temporal information of accessing operation；Step 2, according to the implementing result and the temporal information of the accessing operation, storage consistency design Correctness checking is carried out, if the storage consistency design of the multi-core processor to be verified meets memory consistency model, performs step 3；Step 3, the temporal information of the verification vectors and the accessing operation is sent into instruction-level simulator, described instruction grade simulator performs the verification vectors according to the time sequencing of accessing operation, and result and the implementing result after multi-core processor analog simulation are compared, if comparison result is consistent, multi-core processor accidental validation is continued to execute.
Description
Technical field
The present invention relates to VLSI designs to verify field, more particularly to a kind of to support what accurate memory access detected
Multi-core processor random verification method and its device.
Background technology
The semanteme of the storage model of single core processor is very intuitive, i.e., it is right recently the read operation of any internal storage location will to be returned
The unit carries out the value that write operation is written, and hereafter write operation has then been uniquely determined to the result of same unit read operation.With
When emulation mode carries out accidental validation to single core processor, the reference that generally use reference model provides verification vectors performs knot
Fruit, by the way that the result that reference model provides and practical RTL (register-transfer level) implementing result are relatively sentenced
Break to mistake, for the serial program under single core processor environment, the result of each run has uniquely determining property, this to locate
Reason device accidental validation can be smoothed out.
Different from single core processor, chip multi-core processor uses shared memory systems, and multiple processor cores can be read and write
Same storage unit, this mean that multi-core processor share storage memory access event genetic sequence and its result can not uniquely,
Its correctness is determined that memory consistency model is as the hardware of chip multi-core processor and software, behaviour by memory consistency model
Make the interface of system and application program, the order requirements in specified in more detail shared memory systems between memory access event ensure system
The correctness of system, academia have carried out a large amount of research to the complexity for storing consistency checking, it is believed that multinuclear shares storage feelings
Access order of the correctness of concurrent program implementing result dependent on conflict operation in program under condition, and give concurrent program and hold
The correct standard of row：Acyclic (the bibliography of the digraph of concurrent program result represented with global sequence：Hu Weiwu,《Shared storage
System structure》, Higher Education Publishing House, 2001).Meanwhile academia also demonstrates and is not added with the storage consistency of any restrictions and tests
The problem of card is a problem of NP is difficult, this causes the verification of correctness of chip multi-core processor to become a great difficulty.
Then, scholar proposes in multi-core processor, every accessing operation has one execution time：This time from
It is operated into processor to start, terminate when being submitted to operation, the result of the operation in time sequence positioned at front can be by below
Observed by operation, only performing the time has between the operation of lap just there are the uncertainty of sequence, at multinuclear
Manage the execution time phase of the size limitation of the components such as action pane, access queue, write buffer and accessing operation when device is realized
The quantity of the operation of overlapping is also limited, therefore, when verification stores consistency, the derivation of order relation and performs figure middle ring
Detection can be limited in certain opereating specification, this allows multi-core processor storage consistency checking to be reduced to linearly
Time complexity (bibliography：Yunji Chen,etc."Fast Complete Memory Consistency
Verification",in Proceedings of the 15th IEEE International Symposium on
High-Performance Computer Architecture, 2009.), this conclusion to verify at multinuclear in practice
Reason device storage consistency is possibly realized, and multi-core processor concurrent program memory access sequence in limited range can be detected according to this method
Digraph it is whether acyclic, and judge accordingly multi-core processor storage consistency design it is whether correct.
However, the above method can not solve the result correctness comparison problem in multi-core processor simulating, verifying, even if
The digraph for demonstrating multi-core processor concurrent program memory access sequence is acyclic, can only also illustrate that multi-core processor storage consistency is set
Meter meets memory consistency model specification, and meet the multi-core processor memory access order in the case of memory consistency model specification and
As a result still can not uniquely, when access instruction is together with complicated order random combines more in concurrent program, this memory access
As a result nonuniqueness can cause implementing result State space explosion so that multi-core processor instructs when performing random simulation verification
The correctness of implementing result is difficult to judge.
Accidental validation technology is the important support technology in processor simulation verification flow, describe in Fig. 1 processor with
User's constraint 102 and instruction database 101 are combined by the common frame of machine verification method, are tested by generating the generation of engine 103 at random
Syndrome vector, the verification vectors of generation are respectively fed to perform in instruction-level simulator 104 and design and simulation environment 105 to be verified,
And implementing result is compared, the mistake in processor design can be detected when comparison result is inconsistent, at multinuclear
It manages for device, when access instruction is together with other complicated order random combines in concurrent program, the nonuniqueness of memory access result
Implementing result State-explosion problem can be caused so that results contrast link is difficult to complete during accidental validation, and it is difficult straight to cause
It connects and carries out multi-core processor simulating, verifying using traditional accidental validation technology, this problem is not resolved always.Verification at present
Multi-core processor common pattern is：Processor core each in multi-core processor is tested with tradition accidental validation technology first
Card, then simulating, verifying is carried out for the network-on-chip for connecting each processor core, finally multi-core processor system is stored
Consistency checking, this multi-core processor Validation Mode usually will appear design mistake escape phenomenon, particularly when multinuclear processing
Device storage consistency design is correct, and multinuclear, which intersects memory access and mixed with other instructions, to be performed when mistake can occur, and multi-core processor is tested
Card usually can not accurately detect and Wrong localization.
To sum up, in current multi-core processor simulating, verifying, the nonuniqueness of memory access result causes result phase Space Explosion
Problem so that results contrast link is difficult to complete during accidental validation, can not accurately be detected and Wrong localization, in multi-core processor core
During piece actual motion, since the randomness of scheduling and the shared storage memory access conflict of operating system causes concurrent program implementing result
It can not uniquely determine.
Invention content
In view of the deficiencies of the prior art, the present invention proposes a kind of multi-core processor accidental validation for supporting accurate memory access detection
Method and its device.
The present invention proposes a kind of multi-core processor random verification method for supporting accurate memory access detection, including：
Step 1, the user in multi-core processor to be verified is constrained and is combined with instruction database, generated by concurrent program
Device is generated there are the concurrent program of memory access conflict as verification vectors；It is run in multi-core processor simulated environment to be verified
The verification vectors record the implementing result of the verification vectors and the temporal information of accessing operation；
Step 2, according to the implementing result and the temporal information of the accessing operation, it is correct to carry out storage consistency design
Property inspection, if the multi-core processor to be verified storage consistency design meet memory consistency model, perform step
Rapid 3, it otherwise finds design mistake, stops this accidental validation and perform wrong debugging；
Step 3, the temporal information of the verification vectors and the accessing operation is sent into instruction-level simulator, described instruction
Grade simulator performs the verification vectors according to the time sequencing of accessing operation, and will be after result and multi-core processor analog simulation
Implementing result be compared, if comparison result is consistent, this accidental validation passes through, and it is random to continue to execute multi-core processor
Otherwise verification carries out wrong debugging.
It is further included before the step 1：
Step 11, global clock is set, for recording the temporal information of the accessing operation；
Step 12, the concurrent program generator is set, supports to generate the verification vectors by pseudo-random method；
Step 13, the entry time of every accessing operation and submission time are recorded and is written in file；
Step 14, by the file, storage consistency design Correctness checking is carried out；
Step 15, instruction-level simulator is improved, enables time sequencing of the described instruction grade simulator according to accessing operation
The verification vectors are performed, and implementing result and the implementing result after multi-core processor analog simulation are compared.
The step 14 includes the verification vectors memory access of the multi-core processor to be verified in detection limited range
Whether the digraph of sequence is acyclic, and judges whether the multi-core processor storage consistency design to be verified is correct.
The global clock includes the counter of setting one 64, and each timeticks increase 1 certainly since 0 moment.
Each processor core of the step 13 including monitoring the multi-core processor to be verified by gage system
The entry time and submission time of every accessing operation.
The present invention also proposes a kind of multi-core processor accidental validation device for supporting accurate memory access detection, including：
Verification vectors module is obtained, for user's constraint in multi-core processor to be verified to be combined with instruction database,
By concurrent program generator, generate there are the concurrent program of memory access conflict as verification vectors；It is handled in multinuclear to be verified
The verification vectors are run in device simulated environment, record the implementing result of the verification vectors and the temporal information of accessing operation；
Consistency check module is stored, for the temporal information according to the implementing result and the accessing operation, is carried out
Consistency design Correctness checking is stored, if the storage consistency design of the multi-core processor to be verified meets storage one
Cause property model, then into implementing result comparison module, otherwise find design mistake, stop this accidental validation and perform wrong tune
Examination；
Implementing result comparison module, for the temporal information of the verification vectors and the accessing operation to be sent into instruction-level
Simulator, described instruction grade simulator perform the verification vectors according to the time sequencing of accessing operation, and by result and multinuclear
Implementing result after processor simulation emulation is compared, if comparison result is consistent, this accidental validation passes through, and continues to hold
Otherwise row multi-core processor accidental validation carries out wrong debugging.
It is further included before the acquisition verification vectors module：
Global clock module is set, for setting global clock, for recording the temporal information of the accessing operation；
The concurrent program generator block is set, and for setting the concurrent program generator, support passes through pseudorandom
Method generates the verification vectors；
Entry time and submission time module, for recording the entry time of every accessing operation and submission time and being written
Into file；
It checks module, for passing through the file, carries out storage consistency design Correctness checking；
Improve instruction-level simulator module, for improving instruction-level simulator, enable described instruction grade simulator according to
The time sequencing of accessing operation performs the verification vectors, and by the execution knot after implementing result and multi-core processor analog simulation
Fruit is compared.
The verification vectors visit for checking module and including the multi-core processor to be verified in detection limited range
Whether the digraph for depositing sequence is acyclic, and judges whether the multi-core processor storage consistency design to be verified is correct.
The global clock includes the counter of setting one 64, and each timeticks increase 1 certainly since 0 moment.
The entry time includes monitoring the multi-core processor to be verified by gage system with submission time module
Each processor core every accessing operation entry time and submission time.
By above scheme it is found that the advantage of the invention is that：
The present invention proposes a kind of multi-core processor random verification method and its device for supporting accurate memory access detection, passes through
Comparison mechanism after global clock is set in accidental validation environment and is run, supports the accurate knot in multi-core processor accidental validation
Fruit is compared, and solves the problems, such as the accurate detection of mistake of long-standing problem multi-core processor accidental validation and positioning.
Description of the drawings
Fig. 1 is single core processor accidental validation system structure diagram in the prior art；
Fig. 2 is multi-core processor accidental validation environmental improvement flow example figure in the present invention；
Fig. 3 performs flow diagram for multi-core processor accidental validation in the present invention.
Specific embodiment
Present invention aim to address the precise results comparison problems in multi-core processor accidental validation, support multinuclear processing
The accurate detection of mistake and positioning of device accidental validation, in order to solve the above-mentioned technical problem, it is proposed that a kind of to support accurate memory access inspection
The multi-core processor random verification method and its device of survey.
In order to achieve the above object, the present invention proposes a kind of multi-core processor accidental validation side for supporting accurate memory access detection
Method and its device perform method two including multi-core processor accidental validation environmental improvement method and multi-core processor accidental validation
Point, it is achieved through the following technical solutions：
Multi-core processor accidental validation environmental improvement method, includes the following steps：
1. global clock is set in accidental validation test platform top-level module；
2. transforming the random generation engine in single core processor accidental validation environment as concurrent program generator, support to use
Pseudo-random method has the concurrent program of memory access conflict；
3. each processor core during setting is to multi-core processor to be verified in accidental validation test platform top-level module
The monitoring mechanism of accessing operation records the entry time of every accessing operation and submission time and is written in file；
4. increasing storage consistency design correctness testing mechanism in the results contrast of accidental validation environment, utilization is above-mentioned
The entry time of every accessing operation and the file of submission time are recorded, carries out storage consistency design Correctness checking；
5. improving instruction-level simulator, simultaneously stroke can be performed according to the accessing operation time sequencing recorded before this
Sequence, and result and the implementing result after multi-core processor analog simulation to be verified are compared.
Multi-core processor accidental validation performs method, includes the following steps：
1. user's constraint and instruction database are combined, by concurrent program generator, there is memory access with pseudo-random method generation
The concurrent program of conflict is as verification vectors；
2. running the aforementioned concurrent program for having memory access conflict in multi-core processor simulated environment to be verified, record is parallel
The implementing result of program and the temporal information of accessing operation；
3. according to the implementing result of aforementioned concurrent program and the temporal information of accessing operation, the design of storage consistency is being carried out just
True property inspection.If multi-core processor storage consistency different design to be verified closes the storage consistency mould of requirement profile requirement
Type then finds design mistake, stops this accidental validation and performs mistake debugging；Otherwise next step is continued to execute；
4. the temporal information of the aforementioned concurrent program for having memory access conflict and accessing operation is sent into instruction-level simulator, instruction
Grade simulator performs concurrent program, and result and multinuclear to be verified are handled according to the accessing operation time sequencing recorded before this
Implementing result after device analog simulation is compared, if comparison result is consistent, this analog simulation is verified, and continues to hold
Row multi-core processor accidental validation；If comparison result is inconsistent, design mistake is found, carry out wrong debugging.
The present invention is described in further detail with reference to the accompanying drawings and detailed description.
A kind of multi-core processor random verification method and its device for supporting accurate memory access detection, specific implementation flow include
Multi-core processor accidental validation environmental improvement flow and multi-core processor accidental validation perform flow two parts.
Multi-core processor accidental validation environmental improvement flow, as shown in Figure 2：
Step S201. sets global clock in accidental validation test platform top-level module.In the specific implementation, Ke Yi
In accidental validation test platform top-level module, the counter of setting one 64, each timeticks increase 1 certainly since 0 moment,
Global clock can be obtained；
Step S202. transform the random generation engine in single core processor accidental validation environment as concurrent program and generates
Device, support pseudo-random method have the concurrent program of memory access conflict.The memory address accessed in concurrent program is virtually
Location, and memory access conflict refers to the access to same physical memory address, needs in the actual motion of program identical memory access
Virtual address is mapped to same physical address, can just generate real conflict in this way, random in multi-core processor to be verified
There is no operating system support in verification environment, it in the specific implementation, can will be each in concurrent program in accidental validation environment
The code segment of process is assigned to different physical address, and the data segment of all processes is all assigned to identical physical address,
To generate real memory access conflict；
Step S203. each locates in being set in accidental validation test platform top-level module to multi-core processor to be verified
The monitoring mechanism of device core accessing operation is managed, record the entry time of every accessing operation and submission time and is written in file.
In the specific implementation, accidental validation test platform top-level module can monitor the visit of each processor core module by gage system
Information is deposited, such as：Monitoring of the setting to some processor core cache write operations, uses assign dcw_ in top-level module
Valid=top.cpu_core1......dcache_0.dcw_valid, other accessing operation listening modes can and so on；
Step S204. increases storage consistency design correctness testing mechanism in the results contrast of accidental validation environment,
Using the file of the above-mentioned entry time and submission time for recording every accessing operation, storage consistency design correctness inspection is carried out
It looks into.In the specific implementation, using multi-core processor concurrent program memory access sequence to be verified in traditional technique in measuring limited range
Digraph it is whether acyclic, and judge whether multi-core processor storage consistency design to be verified correct accordingly；
Step S205. improves instruction-level simulator, can be performed according to the accessing operation time sequencing recorded before this
Concurrent program, and result and the implementing result after multi-core processor analog simulation to be verified are compared.
Multi-core processor accidental validation performs flow, as shown in Figure 3：
User's constraint and instruction database are combined by step S301., by concurrent program generator, are generated with pseudo-random method
There is the concurrent program of memory access conflict as verification vectors；
Step S302. runs the aforementioned concurrent program for having memory access conflict in multi-core processor simulated environment to be verified,
Record the implementing result of concurrent program and the temporal information of accessing operation；
Step S303. store consistent according to the implementing result of aforementioned concurrent program and the temporal information of accessing operation
Property design Correctness checking；
Step S304. judges whether multi-core processor storage consistency design to be verified meets depositing for requirement profile requirement
Store up consistency model, if do not meet requirement profile requirement memory consistency model, find design mistake, stop this with
Machine verification performs, and carries out wrong debugging；Otherwise step S305 is performed；
The temporal information of the aforementioned concurrent program for having memory access conflict and accessing operation is sent into instruction level simulation by step S305.
Device；
Step S306. instruction-level simulators perform concurrent program according to the accessing operation time sequencing recorded before this, and will
As a result it is compared with the implementing result after multi-core processor analog simulation to be verified；
Step S307. judges whether aforementioned comparison result is consistent, if comparison result is consistent, performs step S308；Such as
Fruit comparison result is inconsistent, then finds design mistake, carries out wrong debugging；
This analog simulation of step 308 is verified, and continues to execute multi-core processor accidental validation.
The present invention also proposes a kind of multi-core processor accidental validation device for supporting accurate memory access detection, including：
Verification vectors module is obtained, for user's constraint in multi-core processor to be verified to be combined with instruction database,
By concurrent program generator, generate there are the concurrent program of memory access conflict as verification vectors；It is handled in multinuclear to be verified
The verification vectors are run in device simulated environment, record the implementing result of the verification vectors and the temporal information of accessing operation；
Consistency check module is stored, for the temporal information according to the implementing result and the accessing operation, is carried out
Consistency design Correctness checking is stored, if the storage consistency design of the multi-core processor to be verified meets storage one
Cause property model, then into implementing result comparison module, otherwise find design mistake, stop this accidental validation and perform wrong tune
Examination；
Implementing result comparison module, for the temporal information of the verification vectors and the accessing operation to be sent into instruction-level
Simulator, described instruction grade simulator perform the verification vectors according to the time sequencing of accessing operation, and by result and multinuclear
Implementing result after processor simulation emulation is compared, if comparison result is consistent, this accidental validation passes through, and continues to hold
Otherwise row multi-core processor accidental validation carries out wrong debugging.
It is further included before the acquisition verification vectors module：
Global clock module is set, for setting global clock, for recording the temporal information of the accessing operation；
The concurrent program generator block is set, and for setting the concurrent program generator, support passes through pseudorandom
Method generates the verification vectors；
Entry time and submission time module, for recording the entry time of every accessing operation and submission time and being written
Into file；
It checks module, for passing through the file, carries out storage consistency design Correctness checking；
Improve instruction-level simulator module, for improving instruction-level simulator, enable described instruction grade simulator according to
The time sequencing of accessing operation performs the verification vectors, and by the execution knot after implementing result and multi-core processor analog simulation
Fruit is compared.
The verification vectors visit for checking module and including the multi-core processor to be verified in detection limited range
Whether the digraph for depositing sequence is acyclic, and judges whether the multi-core processor storage consistency design to be verified is correct.
The global clock includes the counter of setting one 64, and each timeticks increase 1 certainly since 0 moment.
The entry time includes monitoring the multi-core processor to be verified by gage system with submission time module
Each processor core every accessing operation entry time and submission time.
Claims (10)
1. a kind of multi-core processor random verification method for supporting accurate memory access detection, which is characterized in that including：
Step 1, the user in multi-core processor to be verified is constrained and be combined with instruction database, by concurrent program generator,
It generates there are the concurrent program of memory access conflict as verification vectors；In multi-core processor simulated environment to be verified described in operation
Verification vectors record the implementing result of the verification vectors and the temporal information of accessing operation；
Step 2, according to the implementing result and the temporal information of the accessing operation, storage consistency design correctness inspection is carried out
It looks into, if the storage consistency design of the multi-core processor to be verified meets memory consistency model, performs step 3,
Otherwise it finds design mistake, stop this accidental validation and performs wrong debugging；
Step 3, the temporal information of the verification vectors and the accessing operation is sent into instruction-level simulator, described instruction grade mould
Intend device and perform the verification vectors according to the time sequencing of accessing operation, and by result and holding after multi-core processor analog simulation
Row result is compared, if comparison result is consistent, this accidental validation passes through, and continues to execute multi-core processor and tests at random
Otherwise card carries out wrong debugging；
Generation to be specifically included there are the concurrent program of memory access conflict as verification vectors wherein in step 1：In accidental validation environment
The middle code segment by process each in concurrent program is assigned to different physical address, and the data segment of all processes is all distributed
To identical physical address, to generate memory access conflict.
2. the multi-core processor random verification method of accurate memory access detection is supported as described in claim 1, which is characterized in that institute
It is further included before stating step 1：
Step 11, global clock is set, for recording the temporal information of the accessing operation；
Step 12, the concurrent program generator is set, supports to generate the verification vectors by pseudo-random method；
Step 13, the entry time of every accessing operation and submission time are recorded and is written in file；
Step 14, by the file, storage consistency design Correctness checking is carried out；
Step 15, instruction-level simulator is improved, described instruction grade simulator is enable to be performed according to the time sequencing of accessing operation
The verification vectors, and implementing result and the implementing result after multi-core processor analog simulation are compared.
3. the multi-core processor random verification method of accurate memory access detection is supported as claimed in claim 2, which is characterized in that institute
State step 14 include detection limited range in the multi-core processor to be verified the verification vectors memory access sequence it is oriented
Whether figure is acyclic, and judges whether the multi-core processor storage consistency design to be verified is correct.
4. the multi-core processor random verification method of accurate memory access detection is supported as claimed in claim 2, which is characterized in that institute
The counter that global clock includes setting one 64 is stated, each timeticks increase 1 certainly since 0 moment.
5. the multi-core processor random verification method of accurate memory access detection is supported as claimed in claim 2, which is characterized in that institute
Step 13 is stated to include monitoring every memory access behaviour of each processor core of the multi-core processor to be verified by gage system
The entry time and submission time of work.
6. a kind of multi-core processor accidental validation device for supporting accurate memory access detection, which is characterized in that including：
Verification vectors module is obtained, for user's constraint in multi-core processor to be verified to be combined with instruction database, is passed through
Concurrent program generator is generated there are the concurrent program of memory access conflict as verification vectors；It is imitated in multi-core processor to be verified
The verification vectors are run in true environment, record the implementing result of the verification vectors and the temporal information of accessing operation；
Consistency check module is stored, for the temporal information according to the implementing result and the accessing operation, is stored
Consistency designs Correctness checking, if the storage consistency design of the multi-core processor to be verified meets storage consistency
Model then into implementing result comparison module, otherwise finds design mistake, stops this accidental validation and performs wrong debugging；
Implementing result comparison module, for the temporal information of the verification vectors and the accessing operation to be sent into instruction level simulation
Device, described instruction grade simulator perform the verification vectors, and result and multinuclear are handled according to the time sequencing of accessing operation
Implementing result after device analog simulation is compared, if comparison result is consistent, this accidental validation passes through, and continues to execute more
Otherwise core processor accidental validation carries out wrong debugging；
Generation in verification vectors module is wherein obtained to specifically include as verification vectors there are the concurrent program of memory access conflict：With
The code segment of process each in concurrent program is assigned to different physical address in machine verification environment, and by the number of all processes
Identical physical address is all assigned to according to section, to generate memory access conflict.
7. the multi-core processor accidental validation device of accurate memory access detection is supported as claimed in claim 6, which is characterized in that institute
It states and is further included before obtaining verification vectors module：
Global clock module is set, for setting global clock, for recording the temporal information of the accessing operation；
The concurrent program generator block is set, and for setting the concurrent program generator, support passes through pseudo-random method
Generate the verification vectors；
Entry time and submission time module, for recording the entry time of every accessing operation and submission time and being written to text
In part；
It checks module, for passing through the file, carries out storage consistency design Correctness checking；
Instruction-level simulator module is improved, for improving instruction-level simulator, enables described instruction grade simulator according to memory access
The time sequencing of operation performs the verification vectors, and by the implementing result after implementing result and multi-core processor analog simulation into
Row compares.
8. the multi-core processor accidental validation device of accurate memory access detection is supported as claimed in claim 7, which is characterized in that institute
It states and checks that the verification vectors memory access sequence that module includes the multi-core processor to be verified in detection limited range has
It is whether acyclic to scheming, and judge whether the multi-core processor storage consistency design to be verified is correct.
9. the multi-core processor accidental validation device of accurate memory access detection is supported as claimed in claim 7, which is characterized in that institute
The counter that global clock includes setting one 64 is stated, each timeticks increase 1 certainly since 0 moment.
10. the multi-core processor accidental validation device of accurate memory access detection is supported as claimed in claim 7, which is characterized in that
The entry time includes monitoring each place of the multi-core processor to be verified by gage system with submission time module
Manage the entry time and submission time of every accessing operation of device core.
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| CN109032879B (en) * | 2017-06-09 | 2021-08-20 | 展讯通信（上海）有限公司 | Multi-core processor memory access data detection and verification system and method |
| EP3416254B1 (en) * | 2017-06-14 | 2020-04-22 | ABB Schweiz AG | Electronic protection device |
| CN112364600B (en) * | 2019-07-25 | 2022-06-17 | 中国科学院软件研究所 | Processor micro-architecture design verification method |
| CN110659172B (en) * | 2019-09-11 | 2022-12-27 | 上海高性能集成电路设计中心 | Instruction level checking method for microprocessor locking mechanism |
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| CN111047499A (en) * | 2019-11-18 | 2020-04-21 | 中国航空工业集团公司西安航空计算技术研究所 | Large-scale dyeing array robustness verification method |
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