CN111047499A - Large-scale dyeing array robustness verification method - Google Patents
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- 238000004043 dyeing Methods 0.000 title claims abstract description 27
- 238000002347 injection Methods 0.000 claims abstract description 14
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Abstract
The invention belongs to the field of computer graphics, and particularly relates to a large-scale dyeing array robustness verification method. The method comprises the following steps of S1: verifying the robustness of the instruction set; s2: verifying the robustness of the access resources; s3: verifying the robustness of the operation unit; s4: verifying the robustness of thread-level scheduling; s5: verifying task-level scheduling robustness; s6: robustness verification is typically applied. The invention takes the sub-module verification as a means and adopts the methods of random verification, pressure verification and fault injection verification, thereby comprehensively and reliably verifying the robustness of the dyeing array. The operability of the method has certain guiding significance for verifying the robustness of similar products.
Description
Technical Field
The invention belongs to the field of computer graphics, and can be widely applied to robustness verification of large-scale dyeing arrays.
Background
The large-scale dyeing array is used as the core of the GPU of the modern unified framework, the functional correctness of the large-scale dyeing array is a key functional component for drawing graphs and carrying out general calculation by the GPU, the design scale of the unified dyeing framework at present reaches 5000 dyeing core units, and the robustness of a calculation unit, a memory access unit, a scheduling unit and out-of-order execution of the unified dyeing framework is verified to be the core and the key of the verification of the large-scale dyeing array of the unified framework.
The invention content is as follows:
the purpose of the invention is as follows: the invention aims to provide a comprehensive robustness verification method, and provides a guidance method for robustness verification processes of similar products.
The technical scheme is as follows: a large-scale staining array robustness verification method is provided, and comprises the following steps:
s1: verifying the robustness of the instruction set;
s2: verifying the robustness of the access resources;
s3: verifying the robustness of the operation unit;
s4: verifying the robustness of thread-level scheduling;
s5: verifying task-level scheduling robustness;
s6: robustness verification is typically applied.
Further, the S1 includes:
the instructions cover all instruction sets of the current design; the method for verifying the robustness of the instruction set by adopting the random verification and the fault injection verification comprises the following steps:
s1.1: the instruction random verification, firstly, the random verification of the single instruction use method is carried out, and the functional state of the instruction when different registers and immediate numbers are randomly matched is verified; then verifying the random arrangement of the instructions, randomly arranging various instructions and verifying the correlation problem generated by the instruction arrangement;
s1.2: verifying the instruction fault injection, namely verifying the functional state of the wrong register address and data matched with the instruction;
s1.3: after the instruction verification is completed, the result is input to the operation unit S3 for verification.
Further, in S2, the access resource includes a resource in a local storage, a global storage, a constant storage, or a register; the method adopts the random verification and the pressure verification to verify the robustness of the access and storage resources, and comprises the following steps:
s2.1: the memory access random verification is that data is written and read to different addresses of the memory randomly so as to verify whether the data passing through the memory is correct;
s2.2: the memory access pressure verification is that the method of single read and single write and chip read and chip write is respectively adopted to repeatedly read and write all the memory spaces of the memory to ensure that the memory is in a full-load working state for a long time so as to verify whether the full-load working state of the memory is normal or not;
s2.3: after the access and storage verification is finished, the result is input into an S3 arithmetic unit for verification.
Further, the arithmetic unit in S3 includes a fixed point unit, a floating point unit, a control unit, and a storage loading unit, and the robustness of the arithmetic unit is verified by using methods of random verification, pressure verification, and fault injection verification, including the following steps:
s3.1: the arithmetic unit randomly verifies, randomly distributes different instructions of the unit to the arithmetic unit, and verifies the processing capacity of the unit;
s3.2: the pressure verification of the operation unit, preparing a large amount of instructions of the unit, enabling the unit to be in a full load working state for a long time, and verifying the performance of the unit;
s3.3: and (4) fault injection verification of the operation unit, wherein during verification, an error instruction and data are actively prepared for the operation unit, and the processing result of the operation unit is verified.
Further, in S4, the method of random verification and pressure verification is used to verify the robustness of thread scheduling, and the steps are as follows:
s4.1: the thread scheduling random verification, the number of the cores is controlled to be opened through the mask, the cores with different numbers are opened randomly, the distributed threads are executed, and the processing capacity of the corresponding threads is verified and checked;
s4.2: and verifying thread scheduling pressure, and distributing a large number of thread tasks to cores with different numbers in sequence to ensure that the cores are in a full-load running state for a long time.
Further, in S5, the method of random verification and pressure verification is used to verify the robustness of task scheduling, and the steps are as follows:
s5.1: the task scheduling is randomly verified, different numbers of task scheduling units are randomly started to distribute prepared tasks, and the scheduling capability of the units to the tasks is verified;
s5.2: and verifying the task scheduling pressure, namely starting different numbers of task scheduling units in sequence, distributing a large number of tasks and ensuring that the unit is in a full-load task scheduling state for a long time.
Further, in S6, the method of random verification and pressure verification is used to verify the robustness of the typical application, and the steps are as follows:
s6.1: randomly verifying a typical task, randomly preparing a graphic processing task and a general processing task, putting the graphic processing task and the general processing task into a dyeing array for execution, and verifying the robustness of the dyeing array to the processing capacity of typical application;
s6.2: and (3) typical task pressure verification, namely preparing a large number of graphic processing tasks and general processing tasks, putting the graphic processing tasks and the general processing tasks into a dyeing array for execution, and verifying the robustness of the dyeing array to the processing capacity of typical application in a long-time full-load state.
Has the advantages that:
the invention covers the robustness verification of basic resources from three aspects of instruction set verification, access resource verification and arithmetic unit verification, covers the robustness verification of task execution from two aspects of thread-level scheduling and task-level scheduling, and finally verifies the robustness verification of the operation of a dyeing array scene by typical application in a progressive mode. The hierarchical verification method ensures the correctness of the dyed array for executing various tasks from bottom to top, accelerates the functional verification of the dyed array and lays a good foundation for the verification of the unified architecture GPU.
The invention takes the sub-module verification as a means and adopts the methods of random verification, pressure verification and fault injection verification, thereby comprehensively and reliably verifying the robustness of the dyeing array.
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FIG. 1 is a schematic diagram of an embodiment of the present invention.
Detailed Description
The present invention is described in further detail below.
As shown in fig. 1, it is an implementation schematic diagram of a large-scale staining array robustness verification method, and the method includes the following steps:
s1: instruction set robustness verification:
the instructions cover all instruction sets of the current design; the method for verifying the robustness of the instruction set by adopting the random verification and the fault injection verification comprises the following steps:
s1.1: the instruction random verification, firstly, the random verification of the single instruction use method is carried out, and the functional state of the instruction when different registers and immediate numbers are randomly matched is verified; then verifying the random arrangement of the instructions, randomly arranging various instructions and verifying the correlation problem generated by the instruction arrangement; if the dyeing array has a double-transmitter mechanism, the double-transmitting instruction correlation in the unit and the double-transmitting instruction correlation between units can be verified;
s1.2: verifying the instruction fault injection, namely verifying the functional state of the wrong register address and data matched with the instruction;
s1.3: after the instruction verification is completed, the result is input to the operation unit S3 for verification.
S2: verifying the robustness of the access resources;
the memory access resources comprise resources in a local memory, a global memory, a constant memory and a register; the method adopts the random verification and the pressure verification to verify the robustness of the access and storage resources, and comprises the following steps:
s2.1: the memory access random verification is that data is written and read to different addresses of the memory randomly so as to verify whether the data passing through the memory is correct;
s2.2: the memory access pressure verification is that the method of single read and single write and chip read and chip write is respectively adopted to repeatedly read and write all the memory spaces of the memory to ensure that the memory is in a full-load working state for a long time so as to verify whether the full-load working state of the memory is normal or not;
s2.3: after the access and storage verification is finished, the result is input into an S3 arithmetic unit for verification.
S3: verifying the robustness of the operation unit;
the arithmetic unit in S3 comprises a fixed point unit, a floating point unit, a control unit and a storage loading unit, and the robustness of the arithmetic unit is verified by adopting methods of random verification, pressure verification and fault injection verification, and the method comprises the following steps:
s3.1: the arithmetic unit randomly verifies, randomly distributes different instructions of the unit to the arithmetic unit, and verifies the processing capacity of the unit;
s3.2: the pressure verification of the operation unit, preparing a large amount of instructions of the unit, enabling the unit to be in a full load working state for a long time, and verifying the performance of the unit;
s3.3: and (3) fault injection verification of the arithmetic unit, wherein during verification, an error instruction and data (such as a floating point number, a nonnumber and the like for a fixed point instruction) are actively prepared for the arithmetic unit, and a processing result of the arithmetic unit is verified.
S4: verifying the robustness of thread-level scheduling;
in the step S4, the method of random verification and pressure verification is used to verify the robustness of thread scheduling, and the steps are as follows:
s4.1: the thread scheduling random verification, the number of the cores is controlled to be opened through the mask, the cores with different numbers are opened randomly, the distributed threads are executed, and the processing capacity of the corresponding threads is verified and checked;
s4.2: and verifying thread scheduling pressure, and distributing a large number of thread tasks to cores with different numbers in sequence to ensure that the cores are in a full-load running state for a long time.
S5: verifying task-level scheduling robustness;
in the step S5, the robustness of task scheduling is verified by using a random verification method and a pressure verification method, and the steps are as follows:
s5.1: the task scheduling is randomly verified, different numbers of task scheduling units are randomly started to distribute prepared tasks, and the scheduling capability of the units to the tasks is verified;
s5.2: and verifying the task scheduling pressure, namely starting different numbers of task scheduling units in sequence, distributing a large number of tasks and ensuring that the unit is in a full-load task scheduling state for a long time.
S6: robustness verification is typically applied:
the robustness of typical application is verified by adopting a random verification method and a pressure verification method, and the method comprises the following steps:
s6.1: randomly verifying a typical task, randomly preparing a graphic processing task and a general processing task, putting the graphic processing task and the general processing task into a dyeing array for execution, and verifying the robustness of the dyeing array to the processing capacity of typical application;
s6.2: and (3) typical task pressure verification, namely preparing a large number of graphic processing tasks and general processing tasks, putting the graphic processing tasks and the general processing tasks into a dyeing array for execution, and verifying the robustness of the dyeing array to the processing capacity of typical application in a long-time full-load state.
Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (7)
1. A large-scale staining array robustness verification method is characterized by comprising the following steps:
s1: verifying the robustness of the instruction set;
s2: verifying the robustness of the access resources;
s3: verifying the robustness of the operation unit;
s4: verifying the robustness of thread-level scheduling;
s5: verifying task-level scheduling robustness;
s6: robustness verification is typically applied.
2. The large-scale staining array robustness verification method of claim 1, wherein the S1 comprises:
the instructions cover all instruction sets of the current design; the method for verifying the robustness of the instruction set by adopting the random verification and the fault injection verification comprises the following steps:
s1.1: the instruction random verification, firstly, the random verification of the single instruction use method is carried out, and the functional state of the instruction when different registers and immediate numbers are randomly matched is verified; then verifying the random arrangement of the instructions, randomly arranging various instructions and verifying the correlation problem generated by the instruction arrangement;
s1.2: verifying the instruction fault injection, namely verifying the functional state of the wrong register address and data matched with the instruction;
s1.3: after the instruction verification is completed, the result is input to the operation unit S3 for verification.
3. The large-scale dye array robustness verification method as claimed in claim 1, wherein in S2, the access resources include resources in local storage, global storage, constant storage, and registers; the method adopts the random verification and the pressure verification to verify the robustness of the access and storage resources, and comprises the following steps:
s2.1: the memory access random verification is that data is written and read to different addresses of the memory randomly so as to verify whether the data passing through the memory is correct;
s2.2: the memory access pressure verification is that the method of single read and single write and chip read and chip write is respectively adopted to repeatedly read and write all the memory spaces of the memory to ensure that the memory is in a full-load working state for a long time so as to verify whether the full-load working state of the memory is normal or not;
s2.3: after the access and storage verification is finished, the result is input into an S3 arithmetic unit for verification.
4. The robustness verification method of the large-scale dyeing array according to claim 1, wherein the arithmetic unit in S3 comprises a fixed point unit, a floating point unit, a control unit and a storage loading unit, and the robustness of the arithmetic unit is verified by using a method of random verification, pressure verification and fault injection verification, and the method comprises the following steps:
s3.1: the arithmetic unit randomly verifies, randomly distributes different instructions of the unit to the arithmetic unit, and verifies the processing capacity of the unit;
s3.2: the pressure verification of the operation unit, preparing a large amount of instructions of the unit, enabling the unit to be in a full load working state for a long time, and verifying the performance of the unit;
s3.3: and (4) fault injection verification of the operation unit, wherein during verification, an error instruction and data are actively prepared for the operation unit, and the processing result of the operation unit is verified.
5. The robustness verification method of the large-scale dye array as claimed in claim 1, wherein in the step S4, the robustness of thread scheduling is verified by using a random verification method and a pressure verification method, and the steps are as follows:
s4.1: the thread scheduling random verification, the number of the cores is controlled to be opened through the mask, the cores with different numbers are opened randomly, the distributed threads are executed, and the processing capacity of the corresponding threads is verified and checked;
s4.2: and verifying thread scheduling pressure, and distributing a large number of thread tasks to cores with different numbers in sequence to ensure that the cores are in a full-load running state for a long time.
6. The robustness verification method of the large-scale staining array according to claim 1, wherein in the step S5, the robustness of task scheduling is verified by using a random verification method and a pressure verification method, and the steps are as follows:
s5.1: the task scheduling is randomly verified, different numbers of task scheduling units are randomly started to distribute prepared tasks, and the scheduling capability of the units to the tasks is verified;
s5.2: and verifying the task scheduling pressure, namely starting different numbers of task scheduling units in sequence, distributing a large number of tasks and ensuring that the unit is in a full-load task scheduling state for a long time.
7. The method for verifying robustness of a large-scale staining array according to claim 1, wherein in the step S6, the robustness of a typical application is verified by using a random verification method and a pressure verification method, and the steps are as follows:
s6.1: randomly verifying a typical task, randomly preparing a graphic processing task and a general processing task, putting the graphic processing task and the general processing task into a dyeing array for execution, and verifying the robustness of the dyeing array to the processing capacity of typical application;
s6.2: and (3) typical task pressure verification, namely preparing a large number of graphic processing tasks and general processing tasks, putting the graphic processing tasks and the general processing tasks into a dyeing array for execution, and verifying the robustness of the dyeing array to the processing capacity of typical application in a long-time full-load state.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100107166A1 (en) * | 2008-10-23 | 2010-04-29 | Advanced Micro Devices, Inc. | Scheduler for processor cores and methods thereof |
| CN103294550A (en) * | 2013-05-29 | 2013-09-11 | 中国科学院计算技术研究所 | Heterogeneous multi-core thread scheduling method, heterogeneous multi-core thread scheduling system and heterogeneous multi-core processor |
| US20140375658A1 (en) * | 2013-06-25 | 2014-12-25 | Ati Technologies Ulc | Processor Core to Graphics Processor Task Scheduling and Execution |
| CN105677966A (en) * | 2016-01-05 | 2016-06-15 | 浪潮集团有限公司 | Method for carrying out data mining accelerated verification convergence on coverage rate |
| CN105930242A (en) * | 2016-05-06 | 2016-09-07 | 中国科学院计算技术研究所 | Random multi-core processor verification method and device supporting precise memory access detection |
| CN106709860A (en) * | 2016-12-12 | 2017-05-24 | 中国航空工业集团公司西安航空计算技术研究所 | Debugging structure for GPU unified dyeing processing array |
| CN106991071A (en) * | 2017-03-31 | 2017-07-28 | 联想(北京)有限公司 | kernel dispatching method and system |
| CN108021478A (en) * | 2017-11-24 | 2018-05-11 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of graphics processor robustness test method |
-
2019
- 2019-11-18 CN CN201911125799.6A patent/CN111047499A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100107166A1 (en) * | 2008-10-23 | 2010-04-29 | Advanced Micro Devices, Inc. | Scheduler for processor cores and methods thereof |
| CN103294550A (en) * | 2013-05-29 | 2013-09-11 | 中国科学院计算技术研究所 | Heterogeneous multi-core thread scheduling method, heterogeneous multi-core thread scheduling system and heterogeneous multi-core processor |
| US20140375658A1 (en) * | 2013-06-25 | 2014-12-25 | Ati Technologies Ulc | Processor Core to Graphics Processor Task Scheduling and Execution |
| CN105677966A (en) * | 2016-01-05 | 2016-06-15 | 浪潮集团有限公司 | Method for carrying out data mining accelerated verification convergence on coverage rate |
| CN105930242A (en) * | 2016-05-06 | 2016-09-07 | 中国科学院计算技术研究所 | Random multi-core processor verification method and device supporting precise memory access detection |
| CN106709860A (en) * | 2016-12-12 | 2017-05-24 | 中国航空工业集团公司西安航空计算技术研究所 | Debugging structure for GPU unified dyeing processing array |
| CN106991071A (en) * | 2017-03-31 | 2017-07-28 | 联想(北京)有限公司 | kernel dispatching method and system |
| CN108021478A (en) * | 2017-11-24 | 2018-05-11 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of graphics processor robustness test method |
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