CN110598320B - Instruction set simulator calibration method based on hardware simulation accelerator - Google Patents
Instruction set simulator calibration method based on hardware simulation accelerator Download PDFInfo
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- CN110598320B CN110598320B CN201910858569.4A CN201910858569A CN110598320B CN 110598320 B CN110598320 B CN 110598320B CN 201910858569 A CN201910858569 A CN 201910858569A CN 110598320 B CN110598320 B CN 110598320B
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Abstract
The invention relates to an instruction set simulator calibration method based on a hardware simulation accelerator, which comprises the following steps: operating system programs are run through a hardware simulation accelerator on the basis of the existing microprocessor design, and all simulation tracks are captured to serve as reference model tracks; running the operating system program on an instruction set simulator, and capturing all simulation tracks at the same time; and comparing the simulation track generated on the instruction set simulator with the track of the reference model one by one to realize the correction of the instruction set simulator. The invention can shorten repeated error checking time and improve verification efficiency.
Description
Technical Field
The invention relates to the technical field of chip verification, in particular to an instruction set simulator calibration method based on a hardware simulation accelerator.
Background
In the verification process of large-scale integrated circuit chips, a reliable instruction set simulator is often required to be built according to design specifications to verify a design to be tested. The instruction set simulator refers to an abstract model written in a high-level language C or C++ of a computer to realize the functions of a processor, and simulates the operation and flow of a real processor hardware design. However, in the implementation of an instruction set simulator, various errors may always occur in the implemented instruction set simulator due to the understanding of the design specifications by the verifier or under the influence of various factors, however, a reliable instruction set simulator is important for verification.
The correctness of the instruction set simulator is important according to the verification principle of automatic simulation verification. However, there is no very efficient verification method for the instruction set simulator itself. The conventional verification is that the design to be tested is compared with the instruction set simulator, and error correction is performed when the difference is found, and once the difference is found, both sides must confirm the reason for the difference, so that the time waste of one side is caused. And when comparing some instructions with unexpected results, the results generated by the instruction set simulator are also unexpected, which causes inconsistent results. For example, the design to be tested may process the interrupt processing flow correspondingly, but the processing result is often unpredictable, and the instruction set simulator cannot guarantee the consistency with the result of the design to be tested, so that the comparison is unequal. Therefore, how to quickly calibrate the instruction set simulator, such as the problem that unpredictable results of interrupt processing cannot be compared, is also needed to be solved in the verification process.
Disclosure of Invention
The invention aims to solve the technical problem of providing an instruction set simulator calibration method based on a hardware simulation accelerator, which can shorten repeated error checking time and improve verification efficiency.
The technical scheme adopted for solving the technical problems is as follows: the method for calibrating the instruction set simulator based on the hardware simulation accelerator comprises the following steps:
(1) Operating system programs are run through a hardware simulation accelerator on the basis of the existing microprocessor design, and all simulation tracks are captured to serve as reference model tracks;
(2) Running the operating system program on an instruction set simulator, and capturing all simulation tracks at the same time;
(3) And comparing the simulation track generated on the instruction set simulator with the track of the reference model one by one to realize the correction of the instruction set simulator.
The existing microprocessor in the step (1) is designed for the previous generation microprocessor.
In the step (1), when the hardware accelerator is powered on to run, the design to be tested automatically processes data generated by the operating system program, the obtained result is output at the test port, and then the PC value of each instruction and the instruction entry number pal_num are recorded and collected to be used as a reference model track.
And (3) capturing all simulation tracks by the hardware accelerator in the step (1) through a monitor component.
And (3) converting the collected reference model track into a binary file by the hardware accelerator in the step (1).
The instruction set simulator in the step (2) captures all simulation tracks generated on the instruction set simulator through a monitor component.
In the step (3), the simulation track generated on the instruction set simulator is compared with the track of the reference model one by one through diff_pc_palnum () function, which specifically comprises: the reference model track is collected by using a pointer, and then the reference model track is compared with the instruction entry number and pc value of the simulation track generated on the instruction set simulator.
If the comparison is not equal in the step (3), searching whether the same track exists in a preset range, and if so, continuing to compare; if not, positioning to the position of the instruction with unequal contrast, and performing error checking and modification on the instruction set simulator.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention obtains the reference model simulation track through the hardware simulation accelerator based on the mature design of the popular chips of the previous generation and the operating system program, the hardware simulation accelerator shows the high efficiency of calibration, and as the operating system program is equivalent to hundreds of millions of reliable test excitation, the error possibly existing in the instruction set simulator can be impacted to the maximum extent, and the reliability of calibration is improved. Meanwhile, the problem of verification of instructions with unpredictable results can be solved by using the syn synchronization function. Therefore, for the instruction set simulator, the method can be used for calibrating the instruction set simulator more quickly, so that the verification efficiency is improved.
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FIG. 1 is a flow chart of the present invention;
FIG. 2 is a schematic representation of the use of the present invention;
FIG. 3 is a flow chart of the comparison of command trajectories in the present invention;
FIG. 4 is a flow chart of generating a reference model trajectory in the present invention;
fig. 5 is a schematic diagram of the syn synchronization function in the present invention.
Detailed Description
The invention will be further illustrated with reference to specific examples. It is to be understood that these examples are illustrative of the present invention and are not intended to limit the scope of the present invention. Further, it is understood that various changes and modifications may be made by those skilled in the art after reading the teachings of the present invention, and such equivalents are intended to fall within the scope of the claims appended hereto.
The embodiment of the invention relates to an instruction set simulator calibration method based on a hardware simulation accelerator, which is shown in fig. 1 and 2 and comprises the following steps of:
step S1, operating system programs are run through a hardware simulation accelerator on the basis of the mature and reliable microprocessor design of the previous generation, and all simulation tracks are captured to serve as reference model tracks. The simulation speed of a hardware simulation accelerator is far greater than that of a simulation, and the main point is that the running time of the hardware simulation accelerator is basically the same relative to the running time of test excitation regardless of the scale and complexity of the design. As shown in FIG. 4, hardware simulation accelerator verification is the conversion of RTL designs after comprehensive compilation into logic that can run on the hardware simulation accelerator. When the accelerator is powered on, the design to be tested automatically processes data generated by the operating system program, the obtained result is output at the test port, and then the PC value (program counter register value) of each instruction and the instruction entry number pal_num are recorded and collected.
The output port after the operation of the hardware simulation accelerator is monitored through a component monitor. The Monitor component needs to collect data at any time, and in this embodiment, only the PC value and the instruction entry number pal_num in the data are collected. The generation of the binary file is then realized by the function $fopen (), and the reference simulation track is output and saved according to the binary format.
Step S2, simulating and running an operating system program on the instruction set simulator, and recording a PC value generated by each instruction and an instruction entry number pal_num.
The result generated after the simulation operation is monitored through a monitor component, and the monitor component is the same as that in the step 1, and only the PC value and the instruction entry number pal_num in the monitor component are required to be collected, so that the monitor component can be in one-to-one correspondence with the reference model tracks obtained in the step 1.
Step S3, as shown in FIG. 3, according to the simulation track generated on the instruction set simulator and the track of the reference model, the comparison function is realized through diff_pc_palnum () function. Wherein, the parameters include pal_num, pc value, iscmp. The reference model trajectory is first gathered using pointers and then compared to pal_num and pc values generated by the instruction set simulator. If the comparison is found to be unequal, stopping at the instruction, and printing out pal_num numbers and pc values of which the reference simulation track is unequal to the instruction set simulator.
Since interrupt processing is not implemented in the instruction set simulator, it is caused that the instruction set simulator and the hardware design are not consistent in the processing flow thereof in the interrupt type processing. When the reference model track encounters the interrupt processing part, the reference model track jumps to the related abnormal processing flow of interrupt processing to be executed, and jumps back to continue to be executed downwards after the related abnormal processing flow is completed. The instruction set simulator cannot jump to the related exception handling flow, but selects to directly execute the next instruction. Results from the instruction set simulator are not comparable to those of the reference model, but do not represent an instruction set simulator with errors.
In this embodiment, if the comparison is found to be different, it is explained that an unpredictable situation similar to interrupt processing or the like may occur, and at this time, synchronization may be performed first using the syn synchronization function. The syn-sync function is synchronized by inputting a command syn in the-debug environment, and syn is implemented by calling an interactive_syn () function. The function implementation method comprises the following steps: 1, judging the value of the input information pc and the maximum running number max_inst_num by using if sentences, and outputting 'ERROR' by printf if the input object is smaller than 2: wrong command-! The seehellp information "and back. 2, using max_inst_num as the maximum number of cycles by the for-loop statement. At this time, the corresponding pc values in the reference model track are searched one by one from the input pc value start address, if the input pc values are searched in the range of max_inst_num, the pal_num numbers in the reference model track are increased by corresponding amounts, and the target pc values and the number of entries tracked in the range of max_inst_num are printed out through printf. If no entered pc value is found within the max_inst_num range, then "no target pc value is found within the maximum range" is printed out by printf.
As shown in fig. 5, the syn function is to continue the comparison if the same track is searched within a certain range; if the same track is not found in a certain range, the instruction set simulator is indicated to have errors, then the instruction set simulator is positioned at the position of the instructions with unequal contrast, and the error checking and the modification are carried out on the instruction set simulator.
And step 4, repeating the step 3 until the test excitation is completely contrasted, and if all the instructions pass the comparison, printing the pal_num number and pc value of the last instruction.
It is readily seen that the present invention not only improves the efficiency of finding possible errors in an instruction set simulator, but also enables synchronous comparison in the face of problems in which unpredictable results may occur with respect to interrupt processing or the like. According to the invention, the instruction set simulator is calibrated rapidly, so that repeated error checking time is shortened, and verification efficiency is improved.
Claims (5)
1. An instruction set simulator calibration method based on a hardware simulation accelerator is characterized by comprising the following steps:
(1) Operating system programs are run through a hardware simulation accelerator on the basis of the existing microprocessor design, and all simulation tracks are captured to serve as reference model tracks; when the hardware simulation accelerator is powered on and runs, the design to be tested automatically processes data generated by an operating system program, an obtained result is output at a test port, and then the PC value of each instruction and the instruction entry number pal_num are recorded and collected to be used as a reference model track; the existing microprocessor is designed for the previous generation of microprocessors;
(2) Running the operating system program on an instruction set simulator, and capturing all simulation tracks at the same time;
(3) Comparing the simulation track generated on the instruction set simulator with the track of the reference model one by one to realize the correction of the instruction set simulator; if the comparison is unequal, searching whether the same track exists in a preset range, and if so, continuing to compare; if not, positioning to the position of the instruction with unequal contrast, and performing error checking and modification on the instruction set simulator.
2. The method of claim 1, wherein the hardware accelerator captures all simulation traces through monitor components in step (1).
3. The method for calibrating an instruction set simulator based on a hardware simulation accelerator according to claim 1, wherein the hardware accelerator in the step (1) converts the collected reference model trace into a binary file.
4. The method of claim 1, wherein the instruction set simulator captures all simulation traces generated on the instruction set simulator by monitor component in step (2).
5. The method for calibrating an instruction set simulator based on a hardware simulation accelerator according to claim 1, wherein the step (3) is implemented by using diff_pc_palnum () function to compare the simulation trace generated on the instruction set simulator with the trace of the reference model, specifically: the reference model track is collected by using a pointer, and then the reference model track is compared with the instruction entry number and pc value of the simulation track generated on the instruction set simulator.
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| US20100269103A1 (en) * | 2009-04-21 | 2010-10-21 | National Tsing Hua University | Method and device for multi-core instruction-set simulation |
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| US20100269103A1 (en) * | 2009-04-21 | 2010-10-21 | National Tsing Hua University | Method and device for multi-core instruction-set simulation |
| CN105930242A (en) * | 2016-05-06 | 2016-09-07 | 中国科学院计算技术研究所 | Random multi-core processor verification method and device supporting precise memory access detection |
| CN109726063A (en) * | 2018-12-19 | 2019-05-07 | 北京航空航天大学 | A kind of automation evaluation method of behavior based on instruction to the Verilog MIPS processor realized |
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