CN112001138A

CN112001138A - Efficient digital circuit algorithm verification device

Info

Publication number: CN112001138A
Application number: CN202010902796.5A
Authority: CN
Inventors: 孙晓霞; 张建伟
Original assignee: Shanghai Mingsi Microelectronics Co ltd
Current assignee: Shanghai Mingsi Microelectronics Co ltd
Priority date: 2020-09-01
Filing date: 2020-09-01
Publication date: 2020-11-27

Abstract

The invention provides a high-efficiency digital circuit algorithm verification device in order to improve the complexity and low efficiency in the algorithm verification of a digital circuit. The verification platform combines a systemverilog verification language, an algorithm tool Matlab and an automatic operation script Python, so that algorithm verification becomes intelligent and efficient.

Description

Efficient digital circuit algorithm verification device

Technical Field

The invention belongs to the technical field of integrated circuit chip design. And more particularly to a system and method for chip verification.

Background

What is the target of chip verification? If you think it is "find bug", it is only partially correct. The goal of verification is to ensure that the chip has been designed with a specific set of functions according to the design specifications. That is, whether the design has accurately reflected the design specifications.

The verifier faces different verification requirements according to different projects. Different verification methods need to be employed to implement the verification model. Neither is you building a verification platform with simple verilog, nor with complex UVM methodology, simply inputting stimuli and confirming whether the design is correct by simply checking the waveform output.

The invention aims at the algorithm verification method and explains how to realize an efficient digital circuit algorithm verification device. As shown in fig. 1, the existing verification device is very crude: generating a clock signal and a function (task) of some protocol layers based on tb.v (test bench) of verilog language; testcase.v calls task in tb.v, directionally inputting raw data to the design DUT. Moreover, the verification engineer needs to check the waveform file generated by the environment to determine whether the intermediate steps of the DUT are correct in the whole operation process, so that a lot of tests bring troubles in compiling a lot of test cases, and a lot of operations bring many headache to the verification engineer … ….

Algorithmic verification seeks therefore ways to improve the efficiency and accuracy of verification. And a set of verification models is established by using another description 'explanation' design, so that the verification automation and the scene randomization are achieved to a certain degree.

UVM is currently widely used in a variety of large verification environments, but for designs with less code, UVM is used in turn for some "chicken-killing knives". Therefore, how to make minimal changes to the original verification environment based on verilog language and use various "language" tools to serve the verification work can be just as innovative point.

Disclosure of Invention

The verification system and method provided by the invention are mainly designed for a chip with a certain algorithm quantity, and in a popular way, the chip processes data rather than a protocol layer. The algorithm is very complex and requires not only correct results but also correctness in the middle of the validation process. Thus, as shown in fig. 2, we provide an efficient digital circuit algorithm verification device: an algorithm tool is introduced to replace a manual algorithm; replacing the tedious test case generation process with a scripting tool; and an automatic detection means is used for replacing the complicated waveform detection.

The circuit device of the invention mainly comprises a plurality of parts:

1. data source text file. Simply tells the DUT the final data result that needs to be produced. The format requirements of the text are not limited as long as it is ensured that the text can be recognized by subsequent tools, such as whether the data in the text is 16 or 10, with or without an interpretation function. These can all be customized by the user.

2. And (5) writing an algorithm model. And writing a set of complete algorithm codes by using a Matlab algorithm tool according to the design algorithm document. This process requires documentation strictly by algorithms. And can also confirm the accuracy and some fuzzy zones with the algorithm engineer. This is the core of the overall design. Finally, the Matlab tool prints the key data in the whole set of algorithm into another text file for the test platform to call and compare with the output result of the DUT. The format of the text is consistent with that of the test platform, so that accurate numerical values can be read.

3. The automation script generates a test case. Sv is generated by Python tool from the input data source text file. Because the algorithm test involves a large amount of data input and output, the user can adapt the data source of the user into a beautiful test case according to the customized format with the help of the script tool. And the test can be modified by simply running the script each time the data source is modified. Thus, the places needing to be modified are not needed to be searched in a pile of test case sentences with great expense.

4. The Verilog language is replaced with SystemVerilog. The Verilog language is a hardware description language, and is used for building a verification platform, so that a lot of restrictions are brought. And SystemVerilog is more biased to the software idea, the language application is more flexible and changeable, and the arithmetic operator is simpler.

The DUT design feeds the verification platform handshake signals and its algorithm data. Coordinating with the DUT designer: each time the data value is changed, the verification platform is signaled with an indication signal. Such an interaction signal is essential for the automation of the authentication. The verification platform takes data from the text file of the algorithm expected value each time a rising edge of the indicator signal is taken and compares the data with the data of the DUT. This comparison determines the trend of the true authentication procedure.

6. The device of the invention comprises two circulation circuits and two comparison circuits. The first circulation circuit continuously reads the data source; the second loop circuit is responsible for reading both the expected value of the algorithm and the DUT input data, as well as for comparing the correctness of the data. When the first circulation circuit reads an original data, the first circulation circuit directly enters the second circulation circuit. And if the DUT is obtained and new data is generated, reading expected data generated by the Matlab algorithm tool and sampling DUT input data, and if the expected value is different from the value of the DUT, ending the simulation and checking the error reason. And when the two data are the same, judging whether the expected value is equal to the data source input to the DUT by the verification platform, if the two data are the same, indicating that the DUT acts correctly, jumping out of the second cycle, entering the first cycle, reading the second data source, and repeating the steps. If the two data are different, then wait for the next DUT's reminder and compare the data until the DUT outputs the same value as the data source.

Drawings

FIG. 1 is a diagram of an exemplary prior art algorithm verification device

FIG. 2 is an exemplary efficient algorithm verification device of the present invention

FIG. 3 is an exemplary input and output text example of the present invention

Sv text example fig. 4 is an example test _ case

FIG. 5 is an exemplary System Verilog code of the present invention

FIG. 6 is a schematic diagram of an exemplary circuit of the present invention

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples. The specific embodiments described herein are merely illustrative of the invention and are not intended to be limiting.

The invention provides a high-efficiency digital circuit algorithm verification device circuit which mainly comprises: :

as shown in fig. 3 and 6, the verified data source Input _ data.txt is not preceded by "0 x" in order to simplify the scripting, and the 4-bit data is a 16-bit number. After reading this Input data txt with Matlab tool, it is also necessary to convert this string into hexadecimal numbers because a large number of calculations cannot be operated on string basis. The specific algorithm is written and debugged according to the design of the chip. In fig. 3, the default initial data is 0x0000, converted to 0xAAAA, and the intermediate process data 0xAAA1, 0xAAA2, and 0xAAA3 are enumerated. By analogy, from 0xAA A to 0xBBBB, the intermediate data has 0xBBB1 and 0xBBB 2. When the first loop gets to 0xAAAA, the second loop is directly jumped in, and when the DUT detects the rising edge of output _ indt, the data in output _ data.txt generated by Matlab is read and compared in the comparator 1. If output _ data is equal to exp _ data, comparator 2 is enabled. The comparator 2 compares exp _ data with input _ data, and if the result is 1, the circuit jumps out of the second circulation circuit, reads the next data source, and enters the second circulation circuit again. If the result of comparator 2 is 0, it means that the data has not been converted to 0XAAAA for the first time, and the comparison needs to be continued until output _ data is 0 XAAAA.

Sv, as shown in table 4, is a text example of test _ case. Sv, the implementation of the task function for Send _ data is responsible for delivering the data source to the DUT. These codes have the same format but differ in the source of the data. The conversion from input _ data.txt to test _ case.sv can therefore be implemented with python scripts.

Fig. 5 shows an example of the systemvverilog code of the circuit of the present invention. The first while statement means that this loop statement is always executed if the end of input data. txt is not detected. The second while has no condition and always executes, and only if exp _ data is equal to input _ data, then the second while statement is jumped out.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. An efficient digital circuit algorithm verification device, characterized by: an algorithm tool is introduced to replace a manual algorithm; replacing the test case generation process with a scripting tool; and an automatic detection means is used for replacing the complicated waveform detection.

2. An efficient digital circuit algorithm verification device as claimed in claim 1, mainly comprising the following five parts as the premise of the verification platform: the method comprises the steps of compiling an algorithm model by a data source text file and a Matlab algorithm tool, generating a test case by an automatic script, replacing Verilog language with SystemVerilog, designing and transmitting a DUT to a verification platform to handshake signals and algorithm data thereof.

3. An efficient digital circuit algorithm verification device as claimed in claim 1, having two loop circuits and two comparison circuits. The first circulation circuit continuously reads the data source; the second loop circuit is responsible for reading both the expected value of the algorithm and the DUT input data, as well as for comparing the correctness of the data. When the first circulation circuit reads an original data, the first circulation circuit directly enters the second circulation circuit. And if the DUT is obtained and new data is generated, reading expected data generated by the Matlab algorithm tool and sampling DUT input data, and if the expected value is different from the actual DUT value, ending the simulation and checking the error reason. And when the two data are the same, judging whether the expected value is equal to the data source input by the verification platform to the DUT, if the two data are the same, indicating that the DUT acts correctly, jumping out of the second loop, entering the first loop, reading the second data source, and repeating the steps. If the two data are different, then wait for the next DUT's reminder and compare the data until the DUT outputs the same value as the data source.