CN117313431B - Excitation packaging method for MDIO interface verification - Google Patents
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Abstract
The invention discloses an excitation packaging method for MDIO interface verification, which belongs to the technical field of computer communication and comprises the steps of packaging a read-write function, and processing addresses of write operation or read operation to obtain a PHY base address, a page address and a register address; and converting addresses of write operations or read operations from parallel to serial; defining frame access logic, when the PHY base address is equal to 0 or global variable string_phy, representing a single frame access to the PHY address register; when the PHY base address is equal to the global variable string_mntad, it indicates that the multi-frame access extends space. The invention encapsulates the read-write function of single-frame access and multi-frame access, provides global variables for modifying MDIO establishment time and maintenance time, simplifies the processing of modifying address nodes by each access operation in the verification process, is convenient and quick to use, improves the verification efficiency, and has strong reusability.
Description
Technical Field
The invention relates to the technical field of computer communication, in particular to an excitation packaging method for MDIO interface verification.
Background
The management data input/Output (MDIO) interface is a serial bus interface dedicated to link layer (MAC layer) and physical layer (PHY layer) management, and when the interface is verified based on a general verification methodology (Universal Verification Methodology, UVM), an environment is required as a component (MASTER) for generating and managing transactions to simulate various scenes when actually used, which means that various stimuli, including stimuli in normal scenes and stimuli in abnormal scenes, are transmitted to a design under test (Design Under Test, DUT) through read/write frame operations when the simulation is performed. Because the number of PHY addresses accessed by a single read/write frame operation is 32 at maximum, if the physical layer (PHY) chip in the environment is in butt joint, the PHY address register is a basic space A, and 32 addresses can be accessed when the access of other nodes or expanding space addresses in the environment is supported; the basic space A is also attached with an expansion space which is a space B, four nodes, specifically a first node B1, a second node B2, a third node B3 and a fourth node B4, are arranged in the expansion space B, and each node has 65536 register addresses for access. In this case, the number of PHY register addresses exceeds 32, and a single read/write frame operation cannot meet the requirement, and access failure occurs, so that the MDIO interface needs to be encapsulated for access.
Disclosure of Invention
The invention aims to provide an excitation packaging method for MDIO interface verification.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
an excitation packaging method for MDIO interface verification comprises,
step S1, defining a global variable string_phyad and a global variable string_mntad in a UVM verification environment, assigning an initial value, wherein the value of the global variable string_phyad is 0-31, and the global variable string_phyad is assigned with a PHY base address, and assigning the global variable string_phyad with 0 to represent that the PHY base address is 0, so as to access a basic space; the global variable string_mntad is used for designating the base address of the expansion space, and the global variable string_mntad is assigned to be 1 to represent that the expansion space is accessed;
step S2, connecting a clock signal line, a data line and an enabling signal in an interface file to a design to be tested;
step S3, associating the register model, and obtaining the address and data of the register model through a reg2bus function built in a UVM environment;
step S4, defining a customized parameter macro variable in a macro definition file, and setting a mapping relation corresponding to the address converted by the register model;
s5, packaging a read-write function, and processing addresses of write operation or read operation according to the mapping relation set in the step S4 to obtain a PHY base address, a page address and a register address; and converting addresses of write operations or read operations from parallel to serial; the PHY base address points to the address of the basic space, the page address points to the address of a certain node in the expansion space, and the PHY register address points to the address of a certain register in the node;
the step S5 further comprises defining frame access logic, when performing read operation, encapsulating a subfunction mdio_read in the read function read, when the PHY base address PHY_ADDR is equal to 0 or global variable string_phy, representing single frame access PHY address register, converting the PHY base address PHY_ADDR and PHY register address PHY_REG_ADDR into serial bit data from parallel, respectively placing the serial bit data on PHY base address bit and register address bit of protocol frame format for output, releasing mdio bus in TA field segment, waiting for response reply of PHY chip, collecting serial data replied by PHY chip, and converting into parallel data for output;
when the PHY base address PHY_ADDR is equal to the global variable string_mntad, representing multi-frame access expansion space, the subfunction mdio_read of the first frame converts the PHY base address PHY_ADDR from parallel to serial and puts it on the PHY base address bit of protocol frame format, the register address bit is fixed as N, and the PAGE address page_ADDR is converted from parallel to serial and put it on the data bit and output; the subfunction mdio_read of the second frame converts the PHY base address PHY_ADDR from parallel to serial and places the converted PHY base address on PHY base address bits in protocol frame format, fixes the register address bit as M, and converts the PHY register address PHY_REG_ADDR from parallel to serial and places the converted PHY register address on data bits for output; the subfunction mdio_read of the third frame converts the PHY base address PHY_ADDR from parallel to serial, places the serial on PHY base address bit of protocol frame format, fixes the register address bit as L, releases mdio bus in TA field section, waits for response reply of PHY chip, collects serial data replied by PHY chip, and converts the serial data into parallel data for output;
when writing operation is carried out, a subfunction mdio_write is packaged in a write function write, when a PHY base address PHY_ADDR is equal to 0 or a global variable string_phy, a single-frame write PHY address register is indicated, the subfunction mdio_write converts PHY base address PHY_ADDR and PHY register address PHY_REG_ADDR into serial bit data from parallel, and the serial bit data are respectively output on PHY base address bits and register address bits in a protocol frame format, and the write data are converted from parallel to serial and are output on data bits;
when the PHY base address PHY_ADDR is equal to the global variable string_mntad, representing multi-frame access expansion space, converting the PHY base address PHY_ADDR from parallel to serial by a subfunction mdio_write of a first frame, placing the subfunction mdio_write on a PHY base address bit in a protocol frame format, fixing a register address bit to O, converting a PAGE address page_ADDR from parallel to serial, placing the subfunction mdio_write on a data bit, and outputting the PAGE address page_ADDR; the subfunction mdio_write of the second frame converts the PHY base address PHY_ADDR from parallel to serial and places it on PHY base address bit of protocol frame format, the register address bit is fixed as P, and the PHY register address PHY_REG_ADDR is converted from parallel to serial and places it on data bit and outputs it; the subfunction mdio_write of the third frame converts the PHY base address PHY_ADDR from parallel to serial and places the same on PHY base address bit of protocol frame format, the register address bit is fixed as Q, the write data is converted from parallel to serial and placed on data bit and output, the value range of M, N, L is 0-31, and the value ranges of O and P, Q are 0-31.
Further, the step S4 includes defining a data bit width of the MDIO interface, defining a bit width of the MDIO interface address, defining a high-efficient bit and a low-efficient bit of the PHY base address, defining a high-efficient bit and a low-efficient bit of the page address, and defining a high-efficient bit and a low-efficient bit of the PHY register address.
Further, the read function obtains a 64-bit address addr and 32-bit data corresponding to the address addr, wherein the address addr and the data come from the address and the data of the register model.
Further, the write function obtains the 64-bit address addr and the corresponding 32-bit data, which are required to be written, wherein the address addr is from the address of the register model, and the data is from the data which the user wants to configure to write.
Further, the step S1 further includes defining a global variable mdio_set_time, a global variable mdio_hold_time, a global variable mdio_pre_num, a global variable mdio_st, and a global variable mdio_write_op in the UVM verification environment; the global variable mdio_set_time represents the setup time; the global variable mdio_hold_time represents the hold time; the global variable mdio_pre_num represents a frame format preamble; the global variable mdio_st represents the start domain; the global variable mdio_write_op represents the read and write operation type.
Further, in the above step S5, the set-up time is defined to be equal to the global variable mdio_set_time, the hold time hold_on_time is defined to be equal to the global variable mdio_hold_time, the definition parameter pre is defined to be equal to the global variable mdio_pre_num, the definition parameter st is defined to be equal to the global variable mdio_st, and the definition parameter op is defined to be equal to the global variable mdio_write_op.
Further, the invention relates to an excitation packaging method for MDIO interface verification, which further comprises the following steps,
step S6, importing an interface file, a macro definition file and a packaging read-write function in a UVM verification environment, and declaring an instantiated packaged class file;
step S7, before the simulation starts, assigning values to a global variable mdio_set_time, a global variable mdio_hold_time, a global variable mdio_pre_num, a global variable mdio_st, a global variable mdio_write_op, a global variable strap_phyad and a global variable strap_mntad according to actual needs by transmitting parameters in a connection stage;
step S8, simulation is started.
Further, if the PHY address register is required to be accessed, assigning a value to the global variable string_phy, and if the value is not assigned, defaulting the global variable string_phy to 0; if the extension space needs to be accessed, the global variable string_mntad is assigned to be 1.
The invention also provides an electronic device comprising: a processor and a memory storing computer program instructions; and when the processor executes the computer program instructions, the excitation packaging method for MDIO interface verification is realized.
The invention also provides a computer readable storage medium, wherein the computer readable storage medium is stored with computer program instructions, and the computer program instructions realize the excitation packaging method for MDIO interface verification when being executed by a processor.
The method has the beneficial effects that the excitation packaging method for the MDIO interface verification packages the read-write functions of single-frame access and multi-frame access, and simplifies the processing of modifying the address node by each access operation in the verification process; by means of reserving an interface and setting a global variable, a frame format preamble, a start mark and a read-write operation type to be transmitted currently can be modified in real time through transfer parameters, so that abnormal excitation is sent, and single-frame direct access or multi-frame indirect access is distinguished; supporting modification of the setup time and the hold time; the method can be matched with a register model to send a test for basic reading and writing of the register, is convenient and quick to use, improves verification efficiency, and is high in reusability.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram of a physical layer chip including PHY address registers and an expansion space.
Fig. 2 is a flow chart of an excitation packaging method for MDIO interface verification according to the present invention.
Detailed Description
In order to make the purpose and technical solutions of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention.
Fig. 2 is a flow chart of an excitation packaging method for MDIO interface verification according to the present invention. As shown in FIG. 2, the excitation packaging method for MDIO interface verification of the invention comprises the following steps.
Step S1, defining a global variable mdio_set_time, a global variable mdio_hold_time, a global variable mdio_pre_num, a global variable mdio_st, a global variable mdio_write_op, a global variable strap_phyad and a global variable strap_mntad in a UVM verification environment, and assigning initial values to each global variable.
More specifically, the global variable mdio_set_time represents the setup time; the global variable mdio_hold_time represents the hold time; the global variable mdio_pre_num represents a frame format preamble; the global variable mdio_st represents the start domain; the global variable mdio_write_op represents the read-write operation type; the global variable string_phy d is used for designating the PHY base address, and if the global variable string_phy d is assigned to 0, the PHY base address is 0, and the basic space A is accessed; the global variable string_mntad is used for designating the accessed extended space base address, and if the global variable string_mntad is assigned to 1, the access to the extended space B is indicated.
In a specific embodiment, the global variable string_phyad may have a value of 0-31, which indicates that up to 32 spaces as shown in fig. 1, which are formed by combining the basic space a and the extended space B, may be accessed; the global variable string_phyad defaults to 0, indicating that the first space combined by the base space A and the extension space B is accessed; the global variable string_phyad is 1, which means that the second space formed by combining the basic space A and the expansion space B is accessed; similarly, the global variable string_phy is 31, indicating that the 32 nd space composed of the basic space a and the extended space B is accessed.
In a specific embodiment, the global variable string_mntad is used to specify an extended spatial base address of PHY, and is generally set to add 1 to the PHY base address, or defined according to the traffic scenario requirement, for example: the value of the global variable string_phyad is 0, which indicates that the basic space is accessed; the global variable string_mntad is assigned to 1, indicating that the extension space is accessed.
More specifically, in the UVM verification environment, the global variables may be assigned by passing parameters, and during the use, the global variables may be modified by use of examples to send out some abnormal frames, and if not, the frames conforming to the protocol standard are fixedly sent out.
In step S2, the clock signal line (MDC), the data line (MDIO) and the enable signal mdio_ena in the interface file are connected to the design under test.
The design to be tested may be a design to be tested, generally referred to as a physical layer (PHY) chip; the interface file comprises a clock signal line (MDC), a data line (MDIO) and an enabling signal MDIO_ENA, and defines interfaces of the UVM verification environment and the interfaces of the design to be tested in a one-to-one correspondence manner and is used for connecting the UVM verification environment and the design to be tested.
More specifically, the enable signal mdio_ena is used to control the enabling or enabling of the MDIO interface, and the enable signal mdio_ena indicates whether the device allows the MDIO operation to be performed on the connected PHY (Physical Layer) device.
And step S3, associating the register model, and obtaining the address and data of the register model through a reg2bus function built in the UVM environment.
And S4, defining the customized parameter macro variable in a macro definition file, and setting a mapping relation corresponding to the address converted by the register model. More specifically, a DATA bit WIDTH mdio_data_width of the MDIO interface, a bit WIDTH mdio_addr_width of the MDIO interface address, high-order bits phy_addr_hsb and low-order bits phy_addr_lsb of the PHY base address, high-order bits page_addr_hsb and low-order bits page_addr_lsb of the PAGE address, and high-order bits phy_reg_addr_hsb and low-order bits phy_reg_addr_lsb of the PHY register address are defined.
In one embodiment, step S4 specifically includes defining the DATA bit WIDTH mdio_data_width of the MDIO interface as 32 bits (bit), which indicates that the number of DATA bits to be transferred in each MDIO DATA transfer period is 32 bits; the bit WIDTH MDIO_ADDR_WIDTH defining the MDIO address is 64 bits (bits), indicating that the number of bits used for addressing in the MDIO interface is 64 bits; the high-efficient bit PHY_ADDR_HSB of the PHY base address is defined as 63, the low-efficient bit PHY_ADDR_LSB of the PHY base address is defined as 56, and the 56 th bit to the 63 th bit in the obtained address of the register model are defined as PHY base addresses; defining the high-effective bit PAGE_ADDR_HSB of the PAGE address as 55, and defining the low-effective bit PAGE_ADDR_LSB as 48, wherein the 48 th bit to the 55 th bit in the obtained register model address are PAGE addresses; the high-significant bit phy_reg_addr_hsb defining the PHY register address is 15, and the low-significant bit phy_reg_addr_lsb defining the PHY register address is 0, indicating that bits 0 to 15 in the addresses of the acquired register model are PHY register addresses.
Step S5, packaging a read-write function, and processing addresses of write operation or read operation according to the mapping relation set in the step S4 to obtain PHY base address PHY_ADDR, PAGE address PAGE_ADDR and PHY register address PHY_REG_ADDR; and converting addresses of write operations or read operations from parallel to serial.
Wherein the PHY base address phy_addr points to the address of the base space, i.e. base space a in fig. 1; PAGE address page_addr points to the address of a node in expansion space, PAGE address page_addr points to the address of first node B1, second node B2, third node B3 or fourth node B4 in fig. 1; the PHY register address phy_reg_addr points to the address of a certain register in the node.
The read function is in the form of read (input bit [63:0] addr, input bit [31:0] data), which means that the 64-bit address addr and the corresponding 32-bit data of the read operation are obtained, and the address addr and the data come from the address and the data of the register model.
The write function is in the form of write (input bit [63:0] addr, input bit [31:0] data), which means that the 64-bit address addr and the corresponding 32-bit data of the write operation are obtained, the address addr is from the address of the register model, and the data is from the data which the user wants to configure to write.
Further, in step S5, the set-up_time is defined to be equal to the global variable mdio_set_time, the hold time hold_on_time is defined to be equal to the global variable mdio_hold_time, and the global variable mdio_set_time and all the variables mdio_hold_time can be respectively changed according to the actual requirement in the environment or the test case by the external reserved interface, that is, the global variable mdio_set_time and the global variable mdio_hold_time through the transfer parameters according to the simulation requirement, so as to change the set-up_time and the hold time hold_on_time.
Further, in step S5, the definition parameter pre is equal to the global variable mdio_pre_num, representing the frame format preamble.
Further, in step S5, the definition parameter st is equal to the global variable mdio_st, representing a start flag.
Further, in step S5, the definition parameter op is equal to the global variable mdio_write_op, indicating the type of read/write operation.
Further, defining the frame access logic in step S5 specifically includes, when performing the read operation, encapsulating a subfunction mdio_read in the read function read, where the subfunction mdio_read performs logic judgment processing on the obtained PHY base address phy_addr, PAGE address page_addr, and PHY register address phy_reg_addr. When PHY base address phy_addr is equal to 0 or global variable string_phy d, it means that a single frame accesses PHY address register, i.e. accesses basic space a of fig. 1, subfunction mdio_read converts PHY base address phy_addr and PHY register address phy_reg_addr from parallel to serial bit data, and means that a certain register accessing basic space a is placed on PHY base address bits and register address bits in protocol frame format respectively and output, and in Turn Around (TA) field section releases mdio bus, waits for PHY chip response reply, and collects serial data replied by PHY chip and converts it to parallel data output.
When the PHY base address phy_addr is equal to the global variable string_mntad, it indicates that the multi-frame access expansion space needs to be transmitted for the multi-frame. In a specific embodiment, three frames are required to access the first node B1 in fig. 1, where the subfunction mdio_read of the first frame converts the PHY base address phy_addr from parallel to serial and places it on the PHY base address bits in the protocol frame format, which represents the extended space B accessing the base space a, the register address bit is fixed to N, and the PAGE address page_addr is converted from parallel to serial and placed on the data bits and output, which represents a certain node accessing the extended space B, here the first node B1. The subfunction mdio_read of the second frame converts the PHY base address phy_addr from parallel to serial and places it on PHY base address bits in protocol frame format, indicating that the extended space B of the base space a is accessed, the register address bits are fixed to M, and converts the PHY register address phy_reg_addr from parallel to serial and places it on data bits for output, indicating that a certain register of the first node B1 is accessed. The subfunction mdio_read of the third frame converts the PHY base address phy_addr from parallel to serial and places the converted PHY base address on PHY base address bits in protocol frame format, which means that the expansion space B of the base space a is accessed, the register address bits are fixed to L, the mdio bus is released in the TA field segment, the response reply of the PHY chip is waited, the serial data replied by the PHY chip is collected, and then the converted PHY base address phy_addr is converted to parallel data output, so that the value of a certain register of the first node B1 is read.
The value of the register address bit is generally 0-31, the value ranges of M and N, L are 0-31, and M, N, L are not equal. Alternatively, M has a value of 29, N has a value of 30, and L has a value of 26.
When performing a write operation, the write function write encapsulates the subfunction mdio_write, and the subfunction mdio_write performs logic judgment processing on the obtained PHY base address phy_addr, PAGE address page_addr, and PHY register address phy_reg_addr. When PHY base address phy_addr is equal to 0 or global variable string_phy d, it means that a single frame writes PHY address register, i.e. writes to base space a of fig. 1, and subfunction mdio_write converts PHY base address phy_addr and PHY register address phy_reg_addr from parallel to serial bit data, which means that a certain register of base space a is accessed, and the registers are respectively put on PHY base address bits and register address bits of protocol frame format for output, and write data is converted from parallel to serial for output.
When the PHY base address phy_addr is equal to the global variable string_mntad, it indicates that the multi-frame access expansion space needs to be transmitted for the multi-frame. In a specific embodiment, three frames are required to access the first node B1 in fig. 1, where the subfunction mdio_write of the first frame converts the PHY base address phy_addr from parallel to serial and places it on the PHY base address bits in the protocol frame format, which represents the extended space B accessing the base space a, the register address bits are fixed to O, and the PAGE address page_addr is converted from parallel to serial and placed on the data bits and output, which represents a certain node accessing the extended space B, here the first node B1. The subfunction mdio_write of the second frame converts the PHY base address phy_addr from parallel to serial and places it on PHY base address bits in protocol frame format, indicating that the extended space B of the base space a is accessed, the register address bits are fixed to P, and converts the PHY register address phy_reg_addr from parallel to serial and places it on data bits for output, indicating that a certain register of the first node B1 is accessed. The subfunction mdio_write of the third frame converts the PHY base address phy_addr from parallel to serial and places it on PHY base address bits of protocol frame format, which represents the extended space B accessing the base space a, the register address bits are fixed to Q, and the write data is converted from parallel to serial and placed on the data bits and outputted, thereby realizing writing to a certain register of the first node B1.
The value of the register address bit is generally 0-31, the value ranges of O and P, Q are 0-31, and O, P, Q are not equal. Optionally, O has a value of 29, p has a value of 30, and q has a value of 31.
The above describes a specific embodiment requiring three frame access nodes, and the case of four frame access is needed according to the actual situation, and so on, which will not be described herein.
The frame access logic accessing the second node B2, the third node B3, the fourth node B4 and so on.
In a particular embodiment, the multi-frame access includes transmitting 3 or 4 frames at a time for access.
Further, in practical application, the excitation packaging method for MDIO interface verification further comprises step S6, wherein an interface file, a macro definition file and a packaging read-write function are imported in a UVM verification environment, and an instantiation of a packaged class file is declared.
Step S7, before the simulation starts, the connection stage (ConnectPhase) assigns values to the global variable mdio_set_time, the global variable mdio_hold_time, the global variable mdio_pre_num, the global variable mdio_st, the global variable mdio_write_op, the global variable strap_phy and the global variable strap_mntad through transfer parameters according to actual needs.
By assigning the global variable, the excitation under the normal scene can be set, and the excitation under the abnormal scene can be set, so that various test requirements are met.
More specifically, if the PHY address register needs to be accessed, the global variable string_phy d is assigned, and if the global variable string_phy d is not assigned, the global variable string_phy is defaulted to 0; if the extension space needs to be accessed, the global variable string_mntad is assigned to be 1.
Step S8, simulation is started.
Optionally, the excitation packaging method for MDIO interface verification further includes randomly inputting 0, 1 and X to the clock signal line and the data line when the bus is idle, that is, when no read-write operation is input, and detecting whether hang-up occurs.
The invention also provides an electronic device, which comprises a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program realizes the steps of the MDIO interface verification excitation packaging method when being executed by the processor, and can achieve the same technical effect.
The invention also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the excitation packaging method for MDIO interface verification, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here. Among them, the computer-readable storage medium includes, for example, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or the like.
The invention solves the problem of accessing registers by single frame and multiple frames, and solves the problem of abnormal excitation encapsulation; meanwhile, the establishment time and the holding time can be modified, and the problem of time sequence verification in the simulation stage after verification is solved; all scene excitations are concentrated into one file, and different excitations are not required to be constructed for debugging through different use cases in the verification process, so that the time of the verification process is saved, and the verification efficiency is improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather is capable of modification and variation without departing from the spirit and scope of the present invention.
Claims (10)
1. An excitation packaging method for MDIO interface verification is characterized by comprising the following steps of,
step S1, defining a global variable string_phyad and a global variable string_mntad in a UVM verification environment, assigning an initial value, wherein the value of the global variable string_phyad is 0-31, and the global variable string_phyad is assigned with a PHY base address, and assigning the global variable string_phyad with 0 to represent that the PHY base address is 0, so as to access a basic space; the global variable string_mntad is used for designating the base address of the expansion space, and the global variable string_mntad is assigned to be 1 to represent that the expansion space is accessed;
step S2, connecting a clock signal line, a data line and an enabling signal in an interface file to a design to be tested;
step S3, associating the register model, and obtaining the address and data of the register model through a reg2bus function built in a UVM environment;
step S4, defining a customized parameter macro variable in a macro definition file, and setting a mapping relation corresponding to the address converted by the register model;
s5, packaging a read-write function, and processing addresses of write operation or read operation according to the mapping relation set in the step S4 to obtain a PHY base address, a page address and a register address; and converting addresses of write operations or read operations from parallel to serial; the PHY base address points to the address of the basic space, the page address points to the address of a certain node in the expansion space, and the PHY register address points to the address of a certain register in the node;
the step S5 further comprises defining frame access logic, when a read operation is performed, encapsulating a subfunction mdio_read in the read function read, when a PHY base address PHY_ADDR is equal to 0 or a global variable string_phy, representing that a single frame accesses a PHY address register, converting the PHY base address PHY_ADDR and the PHY register address PHY_REG_ADDR into serial bit data from parallel, respectively placing the serial bit data on PHY base address bits and register address bits in a protocol frame format for output, releasing an mdio bus in an interface direction conversion field section, waiting for response reply of a PHY chip, collecting serial data replied by the PHY chip, and converting the serial data into parallel data for output;
when the PHY base address PHY_ADDR is equal to the global variable string_mntad, representing multi-frame access expansion space, the subfunction mdio_read of the first frame converts the PHY base address PHY_ADDR from parallel to serial and puts it on the PHY base address bit of protocol frame format, the register address bit is fixed as N, and the PAGE address page_ADDR is converted from parallel to serial and put it on the data bit and output; the subfunction mdio_read of the second frame converts the PHY base address PHY_ADDR from parallel to serial and places the converted PHY base address on PHY base address bits in protocol frame format, fixes the register address bit as M, and converts the PHY register address PHY_REG_ADDR from parallel to serial and places the converted PHY register address on data bits for output; the subfunction mdio_read of the third frame converts the PHY base address PHY_ADDR from parallel to serial, places the serial on PHY base address bit of protocol frame format, fixes the register address bit as L, releases mdio bus in TA field section, waits for response reply of PHY chip, collects serial data replied by PHY chip, and converts the serial data into parallel data for output;
when writing operation is carried out, a subfunction mdio_write is packaged in a write function write, when a PHY base address PHY_ADDR is equal to 0 or a global variable string_phy, a single-frame write PHY address register is indicated, the subfunction mdio_write converts PHY base address PHY_ADDR and PHY register address PHY_REG_ADDR into serial bit data from parallel, and the serial bit data are respectively output on PHY base address bits and register address bits in a protocol frame format, and the write data are converted from parallel to serial and are output on data bits;
when the PHY base address PHY_ADDR is equal to the global variable string_mntad, representing multi-frame access expansion space, converting the PHY base address PHY_ADDR from parallel to serial by a subfunction mdio_write of a first frame, placing the subfunction mdio_write on a PHY base address bit in a protocol frame format, fixing a register address bit to O, converting a PAGE address page_ADDR from parallel to serial, placing the subfunction mdio_write on a data bit, and outputting the PAGE address page_ADDR; the subfunction mdio_write of the second frame converts the PHY base address PHY_ADDR from parallel to serial and places it on PHY base address bit of protocol frame format, the register address bit is fixed as P, and the PHY register address PHY_REG_ADDR is converted from parallel to serial and places it on data bit and outputs it; the subfunction mdio_write of the third frame converts the PHY base address PHY_ADDR from parallel to serial and places the same on PHY base address bit of protocol frame format, the register address bit is fixed as Q, the write data is converted from parallel to serial and placed on data bit and output, the value range of M, N, L is 0-31, and the value ranges of O and P, Q are 0-31.
2. The method of claim 1, wherein step S4 includes defining a data bit width of the MDIO interface, defining a bit width of the MDIO interface address, defining high-significant bits and low-significant bits of the PHY base address, defining high-significant bits and low-significant bits of the page address, and defining high-significant bits and low-significant bits of the PHY register address.
3. The method of claim 2, wherein the read function obtains a 64-bit address addr and 32-bit data corresponding to the address addr, the address addr and the data coming from a register model.
4. The method of claim 3, wherein the write function obtains a 64-bit address addr and 32-bit data corresponding to the address addr, the address addr being from an address of the register model, the data being from data that the user wants to configure for writing.
5. The excitation packaging method for MDIO interface verification according to claim 1, wherein said step S1 further comprises defining a global variable mdio_set_time, a global variable mdio_hold_time, a global variable mdio_pre_num, a global variable mdio_st and a global variable mdio_write_op in a UVM verification environment; the global variable mdio_set_time represents the setup time; the global variable mdio_hold_time represents the hold time; the global variable mdio_pre_num represents a frame format preamble; the global variable mdio_st represents the start domain; the global variable mdio_write_op represents the read and write operation type.
6. The method according to claim 5, wherein in the step S5, the set-up time is defined to be equal to the global variable mdio_set_time, the hold time hold_on_time is defined to be equal to the global variable mdio_hold_time, the definition parameter pre is defined to be equal to the global variable mdio_pre_num, the definition parameter st is defined to be equal to the global variable mdio_st, and the definition parameter op is defined to be equal to the global variable mdio_write_op.
7. The stimulus packaging method for MDIO interface verification of claim 1, further comprising,
step S6, importing an interface file, a macro definition file and a packaging read-write function in a UVM verification environment, and declaring an instantiated packaged class file;
step S7, before the simulation starts, assigning values to a global variable mdio_set_time, a global variable mdio_hold_time, a global variable mdio_pre_num, a global variable mdio_st, a global variable mdio_write_op, a global variable strap_phyad and a global variable strap_mntad according to actual needs by transmitting parameters in a connection stage;
step S8, simulation is started.
8. The excitation packaging method for MDIO interface verification of claim 7, wherein if the PHY address register is required to be accessed, the global variable string_phy is assigned, and if not, the global variable string_phy defaults to 0; if the extension space needs to be accessed, the global variable string_mntad is assigned to be 1.
9. An electronic device, the device comprising: a processor and a memory storing computer program instructions; the processor, when executing the computer program instructions, implements an excitation encapsulation method for MDIO interface verification according to any one of claims 1-8.
10. A computer readable storage medium, wherein computer program instructions are stored on the computer readable storage medium, which when executed by a processor, implement an excitation encapsulation method for MDIO interface verification according to any one of claims 1-8.
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