CN115632976A - PCIE transaction layer message generation method, device and storage medium - Google Patents
PCIE transaction layer message generation method, device and storage medium Download PDFInfo
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Abstract
The invention discloses a PCIE transaction layer message generating method, a device and a storage medium, wherein the method comprises the following steps: acquiring input excitation, constraining the input excitation through different configuration options, and generating message data; calculating a message header of a transaction layer according to the message type of the input excitation after the constraint; and combining the transaction layer message header and the message data to generate a transaction layer message, wherein the configuration options comprise a message type, a read-write type, a message address and byte valid bit, a target device number and register address, a message type and message data. The invention supports various message types, and the verifier does not need to package the test excitation according to a specific format according to different message types, and only needs to configure the message type and the destination address of the test excitation, thereby reducing the working intensity of the verifier and shortening the verification period.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a PCIE transaction layer message generation method, a PCIE transaction layer message generation device and a storage medium.
Background
With the development of integrated circuit manufacturing technology, the chip scale is getting larger and the complexity is getting higher, and the Verification accounts for a higher proportion in chip development, and in the Verification of large-scale chip design, in order to reduce the Verification workload and improve the Verification efficiency, it is increasingly important to use mature and reliable VIP (Verification IP) for Verification.
When designing protocol verification, most of the existing PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) uses VIP to send input excitation, and verification personnel use a function encapsulated by VIP and input a PCIE transaction layer header and message data as function parameters. However, since the message header of the PCIE transaction layer is composed of many field segments, the verifier needs to encapsulate the excitation according to a specific format according to different message types, which is a way of this kind of method, and thus the workload is large and the verification period is long. Therefore, how to shorten the verification period, implement automatic encapsulation of PCIE packets, and reduce the working strength of the verification personnel is an urgent problem to be solved.
Disclosure of Invention
The invention provides a PCIE transaction layer message generation method, a device and a storage medium, which are used for solving the problems of shortening the verification period, realizing the automatic encapsulation of PCIE messages and lightening the working strength of verification personnel.
In order to solve the technical problem, the invention provides a method for generating a PCIE transaction layer packet, including:
acquiring input excitation, constraining the input excitation through different configuration options, and generating message data;
calculating a message header of a transaction layer according to the message type of the input excitation after constraint;
and combining the transaction layer message header and the message data to generate a transaction layer message.
Further, the obtaining of the input stimulus, constraining the input stimulus by different configuration options, and generating the message data includes:
the configuration options comprise message types, read-write types, message addresses, byte valid bits, target equipment numbers, register addresses, message types and message data;
constraining the input excitation through different Configuration options to generate a specific Message type, wherein the generated Message type comprises at least one Message type of IO, memory, configuration and Message;
and generating message data according to the restrained message type of the input excitation.
Further, when the message type of the input excitation after the constraint is a write type message, inputting the message data of the input excitation;
and when the message type of the input excitation after the constraint is a read type message, randomly generating the message data of the input excitation.
Further, the calculating a transaction layer packet header according to the constrained packet type of the input stimulus includes:
calculating fmt and type according to the message type of the input excitation after the restraint;
judging whether the Message type of the input excitation after constraint is a Message type Message, and if the Message type is the Message type Message, calculating a domain Message _ code of the Message type Message;
if the Message type Message is not a Message type Message, judging whether the Message type of the input excitation after the constraint is a Memory type Message, and if the Message type is the Memory type Message, setting the Memory type Message in a 4K boundary according to the initial address and the Message length of the Memory type Message;
if not, calculating the field and the byte valid bit of the message according to the restrained message type of the input excitation;
the transaction layer message header comprises fmt, type, message _ code, field and byte valid bit.
Further, setting the Memory type packet within a 4K boundary according to the initial address and the packet length of the Memory type packet includes:
and when the Memory type message crosses the 4K boundary is judged according to the message address and the message length of the Memory type message, dividing the Memory type message into two segments of messages which are both arranged in the 4K boundary according to a PCIE protocol.
Further, still include: and processing the generated byte valid bit according to a PCIE protocol to ensure that the byte valid bit meets the DW alignment requirement.
The invention also provides a PCIE transaction layer message generating device, which comprises a message configuration module and a message generating module;
the message configuration module is used for acquiring input excitation, constraining the input excitation through different configuration options and generating message data;
the message generation module is used for calculating a message header of a transaction layer according to the message type of the input excitation after constraint;
the message generating module is further configured to combine the transaction layer message header and the message data to generate a transaction layer message.
Furthermore, the device also comprises a message query module;
the message query module is used for querying the generated transaction layer message and modifying the generated transaction layer message as required.
The invention also provides a device for generating the PCIE transaction layer message, which comprises a processor and a memory, wherein:
the memory is used for storing a computer program;
the processor is configured to read the computer program in the memory, and execute the steps of any PCIE transaction layer packet generation method described above.
The invention also provides a computer readable storage medium, on which a readable computer program is stored, which when executed by a processor, implements the steps of any of the above PCIE transaction layer message generation methods.
Compared with the prior art, the method, the device and the storage medium for generating the PCIE transaction layer message provided by the invention support various message types, the verifying personnel only need to configure the message type and the destination address of the test excitation without packaging the test excitation according to a specific format according to different message types, so that the working strength of the verifying personnel is reduced, the verifying period is shortened, the error injection is supported, the test safety is high, the query of the transaction layer message is also supported, the modification of a specific field section in the transaction layer message can be realized, the flexible query and the configuration of the transaction layer message are realized, and the test efficiency is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only a part of the embodiments of the present invention, but not all embodiments, and other drawings obtained from these drawings will belong to the protection scope of the present application without creative efforts for those skilled in the art.
Fig. 1 is a flowchart of a PCIE transaction layer message generation method provided in an embodiment of the present invention;
fig. 2 is a flowchart of computing a transaction layer packet header in a PCIE transaction layer packet generation method provided in the embodiment of the present invention;
fig. 3 is a flowchart for adjusting a Memory type message not to cross a 4K boundary in a PCIE transaction layer message generation method provided in the embodiment of the present invention;
fig. 4 is a schematic structural diagram of a transaction layer packet in a PCIE transaction layer packet generation method provided in the embodiment of the present invention;
fig. 5 is a schematic module diagram of a device for a PCIE transaction layer packet generation method according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a PCIE transaction layer message generation device according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In order to make the description of the present disclosure more complete and complete, the following description is given for illustrative purposes with respect to the embodiments and examples of the present invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The embodiments are intended to cover the features of the various embodiments as well as the method steps and sequences for constructing and operating the embodiments. However, other embodiments may be utilized to achieve the same or equivalent functions and step sequences. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.
In the description of the embodiments of the present invention, "/" indicates an OR meaning unless otherwise specified, for example, A/B may indicate A or B; "and/or" in the text is only an association relationship describing an associated object, and means that three relationships may exist, for example, a and/or B may mean: in the description of the embodiments of the present application, "a" or "a" refers to two or more, and other terms and the like should be understood similarly, the preferred embodiments described herein are only for illustrating and explaining the present invention, and are not intended to limit the present invention, and features in the embodiments and examples of the present application may be combined with each other without conflict.
The embodiment of the invention provides a PCIE transaction layer message generating method which can be applied between a host and a PCIe device or between the PCIe device and the device; the host computer can be a computer, or a single network server, a server group consisting of a plurality of network servers, or a cloud based on cloud computing and consisting of a large number of host computers or network servers, wherein the cloud computing is one of distributed computing and is a super virtual computer consisting of a group of loosely coupled computer sets; the PCIe devices may be Root Complex (RC), generating transaction requests on behalf of the processors, interconnected by a local bus, may be switches or endpoint devices, providing expansion or aggregation capabilities, and allowing more devices to be connected; the device is a device capable of automatically performing numerical calculation and/or information processing according to instructions set in advance or stored in advance, and the hardware includes, but is not limited to, a microprocessor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Programmable Gate Array (FPGA), an embedded device, and the like.
It should be understood that the foregoing application scenarios are only examples, and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of the present application, and the technical solutions of the present application may also be applied to other scenarios.
Please refer to fig. 1-4, which are used to solve the problems of how to shorten the verification period, implement automatic encapsulation of PCIE packets, and reduce the working strength of the verification personnel. As shown in fig. 1, an embodiment of the present invention provides a flowchart of a PCIE transaction layer packet generation method, where the method includes:
step S1: acquiring input excitation, constraining the input excitation through different configuration options, and generating message data;
as an optional implementation, the obtaining the input stimulus, constraining the input stimulus by different configuration options, and generating the message data includes:
the configuration options comprise a message type, a read-write type, a message address and byte valid bit, a target device number and a register address, a message type and message data;
constraining the input excitation through different Configuration options to generate a specific Message type, wherein the generated Message type comprises at least one Message type of IO, memory, configuration and Message;
and generating message data according to the restrained message type of the input excitation.
As an optional implementation manner, the generating message data according to the message type of the constrained input excitation includes:
when the message types of the input excitation after the constraint are a Configuration type message and a Memory type message, input message data are specified;
and when the restrained Message types of the input excitation are IO type messages and Message type messages, randomly generating Message data.
In this embodiment, first, an input stimulus to be tested is obtained, and a required message type is generated for configuration options with different input stimulus constraints, where the selectable configuration options include the following options:
the message type is as follows: generating a specific Message type by configuring the pkt _ type, wherein the specific Message type specifically includes at least one Message type of IO (I/otansations, I/o transactions), memory (Memory transactions), configuration (Configuration transactions), and Message (Message transactions); the Memory includes two message types, memory32 and Memory64, and the Configuration includes two message types, configuration0 and Configuration1, so that the total message types that can be generated include the above six message types.
In the embodiment of the present invention, it is allowed to constrain the message type of the input excitation to one or more message types among the six message types, and if the constraint is selected to be multiple message types, the various message types may be generated randomly or alternately, where specific generated message types and random manners are not particularly limited.
And (3) reading and writing types: when the generated message types are IO, memory, and Configuration message types, the read-write type of the message of the type needs to be specified, and the read-write type may be set as a read type or a write type.
Message address and byte valid bit: when the generated message type is an IO and Memory message type, a message address or an address range of the message of the type needs to be specified, the default is random, of course, the first and LastDw (byte valid bits) can be manually adjusted according to the message address and the start address as required, wherein the first DW is used for limiting valid bytes in the first DW data, the LastDw is used for limiting valid bytes in the last DW data, and if the manual adjustment is not performed, the first and LastDw are generated according to the PCIE protocol specification according to the message address and the start address of the message of the type by default.
Target device number and register address: when the generated packet type is a Configuration packet type, the destination device number and the register address of the packet of the type need to be specified.
Message type: the following eight message messages are supported, and the message specifically comprises the following steps: INTx Interrupt Signaling (INTx Interrupt signal), power Management (Power Management), error Signaling (Error signal), locked Transaction Support (lock Transaction Support), slot Power Limit Support (Slot Power Limit Support), vendor-Defined Messages (Vendor Defined message), ignored Messages, related to Hot Plug Support in spec view 1.1 (ignore message, related to Hot Plug Support in PCIE 1.1), LTR (delay Tolerance Reporting).
In addition, for different message packets, specific types thereof may be specified, such as the above-mentioned intxmirutruptsignaling type message packet, and types of inta/b/c/d and its Assert/Deassert may be specified, for example, types of Assert _ inta, deassert _ intb, etc. it should be noted that the above examples are merely for explanation, and specific specified types thereof are not specifically limited here; for example, for the error signaling type message, a Cor/total/Nonfatal type, for example, err _ Cor, err _ total, err _ Nonfatal, or the like may be specified, and if the specific type of the message is not specified, the specific type is randomly specified within a range allowed by PCIE protocol specifications.
Message data: taking the configuration and memory type messages as examples, when the configuration and memory type messages are set as writing types, the data content needs to be input manually; specifically, when the packet type is a Configuration packet type, 4 bytes of data content may be specified, and when the generated specific packet type is a Memory packet type, the specific data content may be input in a form of a queue, and if a read-write type is not specified or a read-type packet is specified, the data content may be randomly generated, that is, the packet data is generated.
It should be noted that the configuration options provided in the embodiment of the present invention include a packet type, a read-write type, a packet address and byte valid bit, a target device number and register address, a message packet type, and packet data, where the packet type is a configuration option that must be constrained, and for all the above configuration options except the packet type, it is necessary to perform selective configuration as needed according to a specific packet type of the generated packet, so as to generate a packet type that meets a requirement.
Step S2: calculating a message header of a transaction layer according to the message type of the input excitation after constraint;
as an optional implementation manner, please refer to fig. 2, which is a flowchart for calculating a packet header of a transaction layer in a PCIE transaction layer packet generation method according to an embodiment of the present invention, where the calculating a packet header type and each field segment according to a constrained packet type includes:
s201: calculating fmt and type according to the message type of the input excitation after the constraint;
s202: judging whether the Message type of the input excitation after constraint is a Message type Message, and if the Message type is the Message type Message, calculating a domain Message _ code of the Message type Message;
s203: if the Message type Message is not a Message type Message, judging whether the Message type of the input excitation after the constraint is a Memory type Message, and if the Message type is the Memory type Message, setting the Memory type Message in a 4K boundary according to the initial address and the Message length of the Memory type Message;
s204: if the message is not a Memory type message, calculating the field and the byte valid bit of the message according to the restrained message type of the input excitation;
the transaction layer message header comprises fmt, type, message _ code, field and byte valid bit.
As an optional implementation manner, the setting the Memory type packet within the 4K boundary according to the start address and the packet length of the Memory type packet includes:
and when the Memory type message crosses the 4K boundary is judged according to the message address and the message length of the Memory type message, dividing the Memory type message into two segments of messages which are both arranged in the 4K boundary according to a PCIE protocol.
In the embodiment of the present invention, two fields, fmt (Format of Transaction Layer Package, transaction Layer Package Format) and type, are calculated according to the constrained message type, that is, the message type of the specific Transaction Layer generated in step S1, and the two fields, fmt and type, corresponding to different message types are unique.
Further, judging whether the Message type after the restriction is a Message type Message, if so, calculating a Message _ code (Message identification code) of the Message according to the specific type of the Message type Message; judging whether the message type after the restriction is a Memory type message, and when the message type and the byte valid bit are introduced in the step S1, when the message type and the byte valid bit are mentioned, specifying the message address and the address range of the Memory message type is required, and judging whether the Memory type message crosses the address range according to the message length and the initial address of the Memory type message; referring to fig. 3, it is a flowchart for adjusting that a Memory type packet does not cross a 4K boundary in a PCIE transaction layer packet generation method provided in the embodiment of the present invention, specifically, if the 4K boundary is crossed, the Memory type packet needs to be divided into two segments of data according to a PCIE protocol specification again, and the Memory type packet is ensured to be set within the 4K boundary according to an initial address and a packet length of the Memory type packet.
It should be noted that, according to the message length and the start address, the PCIE protocol specifies that the message should not cross a 4K boundary (4 KB boundary), assuming that the start address of the message after a certain constraint is 0xFF0 and the message length is 64DW, the end address of the message is 0x10F0, which obviously does not meet the specification of the PCIE protocol, at this time, the message is divided into two-end data by taking the 4K boundary as a limit, and the generated first message address is 0xFF0, the length is 4DW, the second message address is 0x1000, and the length is 60DW, which ensures that the message is set within the 4K boundary.
Further, when the Message type after the restriction is neither a Message type Message nor a Memory type Message, calculating a Length (byte Length), a first Dw and a LastDw according to the Message type; in addition, when describing the message address and the byte valid bit in step S1, it is mentioned that for IO and Memory message types, the FirstDw and LastDw of the above type of message have already been configured, so when calculating the FirstDw and LastDw thereof, the byte valid bit can be configured manually, for example, by manually setting a byte valid bit to control a certain byte of the register, with the input value in step S1 as the reference; for example, the Configuration type message is used for writing a register, and the length of the register is 4 bytes, so if only one Byte in the register is to be configured, the Configuration can be implemented by manually setting a Byte valid bit to control the one Byte of the register, and if the Byte valid bit is not manually set, the Configuration can be randomly configured according to the PCIE protocol specification.
It should be noted that, when computing the FirstDw and the LastDw, the byte valid bits need to be processed according to the PCIE protocol specification, so that the final computation result meets the DW alignment requirement; because the unit of Data Payload in PCIE is DW, DW defines 16-bit Data, each Data needs two units to be stored, high 8-bit Data bytes are stored in low address bytes first, and low 8-bit Data bytes are stored in high address bytes; the above-mentioned final calculation result meets the DW alignment requirement, that is, the data size of the Byte valid bit needs to be aligned by taking the DW as a unit and should be an integer multiple of the DW, so a Byte Enable (Byte Enable field) is introduced in the embodiment of the present invention to solve this problem, and how to introduce the Byte Enable to solve the problem that the data size is not an integer multiple of the DW, that is, does not meet the DW alignment requirement is a prior art widely applied in the field, and is not described herein again.
Further, the embodiment of the present invention also supports injecting errors, and because such an error scenario does not easily occur when an edge condition test needs to be performed, an error needs to be directly injected into a program in a fast manner so as to perform the edge condition test, and specifically, when an error needs to be injected, the method can be implemented by setting an EP value in a packet header of a PCIE transaction layer to 1.
It should be noted that the method of the present invention is not limited to the sequence of the steps S201 to S204, and in a specific implementation, the sequence of S201 to S204 may be adjusted according to an actual situation, for example, it is determined whether the Message is a Memory type Message, and then determined whether the Message is a Message type Message, which is not limited in this order.
And step S3: and combining the transaction layer message header and the message data to generate a transaction layer message.
In the embodiment of the present invention, since each field segment has been calculated according to the message type of the input excitation after the constraint in step S2, each field segment includes fmt, type, message _ code, length, firstDw, and LastDw, and is collectively referred to as a transaction layer header.
Further, regarding the above-mentioned message data, the message data has been input or generated in the configuration option message data in step S1, and the transaction layer header is generated in step S2, so that the above-mentioned message data and the generated transaction layer header are used to generate the transaction layer message according to a certain combination manner, please refer to fig. 4, which is a schematic diagram of the structure of the transaction layer message in the PCIE transaction layer message generation method according to the embodiment of the present invention, and as for the specific arrangement manner of fmt, type, message _ code, length, firstDw, and LastDw in the transaction layer header, it is common knowledge known by those skilled in the art, and details are not repeated here.
Furthermore, the embodiment of the present invention also provides query and modification functions of each domain segment of the transaction layer packet, and the specified domain segment of the transaction layer packet can be obtained through a specified query function, and the query supported contents include: the message header, the message type, the message data and each domain section of the complete transaction layer message are inquired to obtain the return data, the return data is compared with the expected data, and each specific domain section in the transaction layer message can be accurately modified according to the requirement.
Specifically, the whole transaction layer message header, the fmt domain segment, the Length domain segment and the message data of the transaction layer message can be returned by calling display _ header, display _ fmt/display, length and display _ data; and modifying the message header of the transaction layer, the fmt field segment, the target equipment address and the target register address of the Configuration and the like by calling set _ header, set _ fmt, set _ bdf and set _ reg _ addr.
Further, in the verification of large-scale chip design, in order to reduce the verification workload and improve the verification efficiency, a mature and reliable VIP is required to be used for verification, so in the actual verification process, the VIP sends transaction layer excitation to the design to be tested, the transaction layer excitation is the transaction layer message generated by the method, and the verification personnel transmit the transaction layer message to the VIP as a parameter for subsequent verification.
Based on the PCIE transaction layer message generating method, as shown in fig. 5, an embodiment of the present invention further provides a PCIE transaction layer message generating method apparatus, where the apparatus includes a message configuration module 501, a message generating module 502, and a message querying module 503;
the message configuration module 501 is configured to obtain an input stimulus, constrain the input stimulus by different configuration options, and generate message data;
the message generating module 502 is configured to calculate a transaction layer message header according to the constrained message type of the input excitation;
the message generating module 502 is further configured to combine the transaction layer message header and the message data to generate a transaction layer message;
the message query module 503 is configured to query the generated transaction layer message, and modify the generated transaction layer message as needed.
For other details of implementing the above technical solution by each module in the PCIE transaction layer packet generation apparatus, refer to the description in the PCIE transaction layer packet generation method provided in the foregoing embodiment of the present invention, and are not described herein again.
Based on the above PCIE transaction layer packet generation method, as shown in fig. 6, an embodiment of the present invention further provides a schematic structural diagram of a PCIE transaction layer packet generation device, where the identification device includes a processor 601 and a memory 602 coupled to the processor 601. The memory 602 stores a computer program, and when the computer program is executed by the processor 601, the processor 601 executes the steps of the PCIE transaction layer packet generation method in the foregoing embodiment.
For other details of implementing the above technical solution by the processor 601 in the PCIE transaction layer packet generation device, refer to the description in the PCIE transaction layer packet generation method provided in the foregoing embodiment of the present invention, and are not described herein again.
The processor 601 may also be referred to as a Central Processing Unit (CPU), and the processor 601 may be an integrated circuit chip having signal processing capability; the processor 601 may also be a general purpose processor, a DSP (Digital Signal processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable gate Array) or other Programmable logic device, discrete gate or transistor logic, discrete hardware modules, wherein the general purpose processor may be a microprocessor or the processor 601 may be any conventional processor, etc.
As shown in fig. 7, an embodiment of the present invention further provides a schematic structural diagram of a computer-readable storage medium, where the storage medium stores a readable computer program 701; the computer program 701 may be stored in the storage medium in the form of a software product, and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a portable hard disk, a magnetic or optical disk, a ROM (Read-Only Memory), a RAM (Random Access Memory), etc., or terminal devices, such as a computer, a server, a mobile phone, a tablet, etc.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus, device and method can be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The PCIE transaction layer message generation method, the device and the storage medium provided by the invention support various message types, the verifier does not need to package the test excitation according to a specific format according to different message types, only needs to configure the message type and the destination address of the test excitation, reduces the working strength of the verifier, shortens the verification period, supports error injection, has high test safety, also supports inquiring the transaction layer message, can modify a specific field section in the transaction layer message, realizes flexible inquiry and configuration of the transaction layer message, and further improves the test efficiency.
It should be noted that the aforementioned destination address includes a register address specified for a Configuration message type when the target device number and the register address are introduced in step S1, and further includes a message address specified for IO and Memory message types when the message address and the byte valid bit are introduced in step S1.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A PCIE transaction layer message generating method is characterized by comprising the following steps:
acquiring input excitation, constraining the input excitation through different configuration options, and generating message data;
calculating a message header of a transaction layer according to the message type of the input excitation after the constraint;
and combining the transaction layer message header and the message data to generate a transaction layer message.
2. The method of claim 1, wherein the obtaining input stimuli, constraining the input stimuli by different configuration options, and generating packet data comprises:
the configuration options comprise a message type, a read-write type, a message address and byte valid bit, a target device number and a register address, a message type and message data;
constraining the input excitation through different Configuration options to generate a specific Message type, wherein the generated Message type comprises at least one Message type of IO, memory, configuration and Message;
and generating message data according to the message type of the input excitation after the constraint.
3. The method of claim 2, wherein when the message type of the input stimulus after constraint is a write-type message, the message data of the input stimulus is input;
and when the message type of the input excitation after the constraint is a read type message, randomly generating the message data of the input excitation.
4. The method of claim 2, wherein the calculating a transaction layer header according to the constrained message type of the input stimulus comprises:
calculating fmt and type according to the message type of the input excitation after the restraint;
judging whether the Message type of the input excitation after constraint is a Message type Message, and if the Message type is the Message type Message, calculating a domain Message _ code of the Message type Message;
if the Message type Message is not a Message type Message, judging whether the Message type of the input excitation after the constraint is a Memory type Message, and if the Message type is the Memory type Message, setting the Memory type Message in a 4K boundary according to the initial address and the Message length of the Memory type Message;
if not, calculating the field and the byte valid bit of the message according to the restrained message type of the input excitation;
the transaction layer message header comprises fmt, type, message _ code, field and byte valid bit.
5. The method of claim 4, wherein setting the Memory type packet within a 4K boundary according to the initial address and packet length of the Memory type packet comprises:
and when the Memory type message crosses the 4K boundary is judged according to the message address and the message length of the Memory type message, dividing the Memory type message into two segments of messages which are both arranged in the 4K boundary according to a PCIE protocol.
6. The method for generating a PCIE transaction layer packet according to claim 4, further comprising:
and processing the generated byte valid bit according to a PCIE protocol to ensure that the byte valid bit meets the DW alignment requirement.
7. A PCIE transaction layer message generating device is characterized by comprising: the message configuration module and the message generation module;
the message configuration module is used for acquiring input excitation, constraining the input excitation through different configuration options and generating message data;
the message generation module is used for calculating a message header of a transaction layer according to the message type of the input excitation after constraint;
the message generating module is further configured to combine the transaction layer message header and the message data to generate a transaction layer message.
8. The PCIE transaction layer packet generation apparatus of claim 7, further comprising a packet query module;
the message query module is used for querying the generated transaction layer message and modifying the generated transaction layer message as required.
9. A PCIE transaction layer message generating device comprises a processor and a memory, wherein:
the memory is used for storing a computer program;
the processor is configured to read the computer program in the memory, and execute the steps of the PCIE transaction layer packet generation method according to any one of claims 1 to 6.
10. A computer readable storage medium, on which a readable computer program is stored, which when executed by a processor, implements the steps of the PCIE transaction layer packet generation method according to any one of claims 1 to 6.
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