CN115828839A - System-level verification system and method for SOC (System on chip) - Google Patents

Abstract

The invention provides a system level verification system and a method of an SOC chip, which comprises the following steps: a hardware platform top layer, a verification platform and a script file; the verification platform is connected with the top layer of the hardware platform through a GPI interface, completes the excitation drive of the verification platform on hardware in the SOC chip system to be tested, and acquires hardware data; the script file specifies a design code and a verification code in the SOC chip system to be tested and specifies a simulation type; and the top layer of the hardware platform is used for operating hardware in the SOC chip system to be tested. The verification system and the test case are both realized by Python without introducing other languages and scripts, the establishment of a complex UVM verification environment is omitted, the environment is easy to establish, a test method with bus behavior as an excitation inlet and a test method with c program as an excitation inlet can be realized simultaneously, the verification method takes random constraint and coverage rate drive as principles, and the method has the characteristics of flexibility, high efficiency, rapid convergence and high verification efficiency.

Description

System-level verification system and method for SOC (System on chip)

Technical Field

The present invention relates to a system and method for verifying, and more particularly, to a system on a chip (SOC) system level verification system and method.

Background

IP multiplexing makes SOC design simpler, swift, still needs verify at the system level, and traditional testbench can't realize nimble random constraint and result self-checking, builds UVM from 0 and verifies that the environment needs consume a large amount of time earlier and builds verification platform.

Disclosure of Invention

The invention aims to: the invention provides a system-level verification system and method of an SOC chip, aiming at the defects of the prior art.

In order to solve the technical problem, the invention discloses a system-level verification system and a method of an SOC chip, which comprises the following steps: a hardware platform top layer, a verification platform and a script file;

the verification platform is connected with the top layer of the hardware platform through a GPI interface, completes the excitation drive of the verification platform on hardware in the SOC chip system to be tested, and acquires hardware data; the script file specifies a design code and a verification code in the SOC chip system to be tested and specifies a simulation type; and the top layer of the hardware platform is used for operating hardware in the SOC chip system to be tested.

The hardware platform top layer comprises: the design to be tested is an SOC chip system to be tested and an external equipment model; the top layer of the hardware platform runs in an emulator.

The verification platform comprises: test cases, excitation models, and scoreboards.

The test case comprises two types of coroutines, namely a coroutine with public configuration and a coroutine with specific function correlation: according to the workflow in-stroke configuration of different functional modules, the coroutine completes the driving and the acquisition of hardware signals by accessing the hierarchical path of the hardware signals in the top layer of the hardware platform, and the hardware platform is usually communicated with the signal level;

the excitation model is used for signal beams following a set protocol: and the communication bus completes the driving of excitation and the acquisition of response according to an interface protocol and performs signal beam level communication with the hardware platform.

And the scoring board judges whether the response data is correct or not by comparing the difference and the similarity between the response data acquired from the SOC chip system to be tested and the expected value, gives a mark indicating whether the test case passes or not, and prints a conclusion.

The script file is used for setting test parameters, and comprises the following steps: designing codes are designated by setting a top module of the SOC chip system to be tested and a file list containing all the codes; specifying verification codes participating in simulation by defining names of test cases; the simulation types are distinguished through the definition of global variables.

The test parameters set by the script file comprise: pre-simulation, post-simulation, whether a waveform file needs to be reserved, and the scale of the regression test.

The test cases are classified according to scenes, and the specific method comprises the following steps:

validating processor-related scenarios: respectively constructing the operation of a software part and the excitation of a hardware part by using a C language and a Python language in a C + Python mode;

ignoring processor participation scenarios: and skipping a cpu starting program in the SOC chip system to be tested, and only using the random constraint characteristics of the cocotb verification framework to construct the excitation of the hardware part.

A system-level verification method of an SOC chip adopts an SOC chip system-level verification system to carry out verification, and comprises the following steps:

the method comprises the following steps: the test case is designated by assigning a global variable, and the operation is started; compiling an RTL code in the SOC chip system to be tested by using a simulation tool; running the compiling code to start simulation, and performing simulation control on a hardware platform by using a GPI interface;

step two: if the global variable is defined as a CPU participation value, the CPU loads an instruction of a corresponding test case through flash after being electrified and converts the instruction into a hardware behavior; otherwise, resetting the CPU to stop working, directly executing Python codes in the test case, and exciting the source to simulate the behavior of the CPU by the bus model;

step three: if the CPU participates, controlling the CPU to configure related functions of the design to be tested in the SOC chip system to be tested according to the verification scene, and responding feedback information of other equipment by the CPU; if the CPU control is not needed, the SOC chip system to be tested enters a working mode required by the verification scene through bus configuration in a Python test case;

step four: signal level excitation generation and transmission: generating random data according to the scene and function requirements, and sending the random data to a hardware interface through a layering path of signals in a hardware platform;

step five: signal beam excitation generation and transmission: generating random data for each signal in the signal beam according to the scene and function requirements, and driving the excitation data to a hardware interface corresponding to the signal beam according to the behavior time sequence requirement defined in the excitation model so as to enable the hardware interface to meet the behavior specification of the interface;

step six: and response collection and judgment, collecting a response according to a time sequence requirement by the excitation model, judging whether the response is expected data in the score board, if so, giving a mark that the test case passes, waiting for finishing simulation after all codes are executed, and if not, printing error information and finishing simulation.

Has the advantages that:

the verification system and the test case are both realized by Python without introducing other languages and scripts, the establishment of a complex UVM verification environment is omitted, the environment is easy to establish, a test method with bus behavior as an excitation inlet and a test method with c program as an excitation inlet can be realized simultaneously, the verification method takes random constraint and coverage rate drive as principles, and the method has the characteristics of flexibility, high efficiency, rapid convergence and high verification efficiency.

1) The verification system achieves the purpose of SOC verification based on the python language and the cocotb verification framework, a verifier does not need to have an SV/UVM verification background, the python/cocotb learning period is short, and verification is more efficient.

2) The test cases are divided into two types according to the functional characteristics of verification, cases which do not need to participate in the CPU use bus behavior as injection excitation, otherwise, the injection excitation is converted into SOC hardware behavior by reading c program, and the former skips the CPU starting process, thereby improving the verification efficiency.

3) And aiming at the SOC top layer interface establishment class, the test case is directly instantiated to realize the driving or the acquisition of signals, and compared with interface transmission in UVM, the test case is simpler and more efficient.

4) The developed script file can realize a plurality of functions, such as appointing design codes, verification codes and entries of a hardware platform, distinguishing simulation types, such as front simulation and rear simulation, other behaviors for saving resources, such as whether a waveform file needs to be reserved or not, the scale of regression testing and the like, and can realize the efficient utilization of the resources on the premise of realizing the verification purpose.

5) When the IP level verification environment is absent, the verification method can realize the rapid verification of the functions of bus connection, concurrent access, interrupt connection, interrupt response, clock, reset and the like.

6) The system takes the random constraint and coverage rate driving technology as the principle, and has the characteristics of flexibility, high efficiency, rapid convergence and high verification efficiency.

Drawings

The foregoing and/or other advantages of the invention will become further apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a schematic diagram of a system architecture according to the present invention.

FIG. 2 is a flow chart of a verification method according to the present invention.

Detailed Description

The invention provides a system-level verification system and a method of an SOC chip, wherein the system-level verification system comprises the following steps:

1. verification system, as shown in fig. 1:

the system comprises a hardware platform top layer, a verification platform and a script file, wherein the verification platform is connected with the hardware platform top layer through a GPI interface to realize the excitation drive of hardware and obtain hardware data, and the script file specifies the design code and the verification code of the SOC to be tested and specifies the simulation type;

1) The top layer of the hardware platform includes a design to be tested (i.e. SOC chip system to be tested) and an external device model, and the whole top layer of the hardware platform runs in the emulator (generally, the verification platform and the hardware platform run in the emulator, so that a party code needs to be recompiled after being modified), for example: the VCS. In the present invention, it is verified that the modification of the code does not result in the recompilation of the entire system.

2) The verification platform is written in Python code and comprises the following steps: the system comprises a test case, an excitation model and a scoring board for result inspection; the test case comprises a plurality of coroutines, which are mainly divided into a commonly configured coroutine and a coroutine related to a specific function: the cooperation program can realize the driving and the acquisition of hardware signals by accessing the hierarchical path of the hardware signals in the hardware platform, and the hardware platform is usually communicated with the signal level; the excitation model is for a signal beam that follows a particular protocol: and the communication bus is used for finishing the drive of excitation and the collection of response according to an interface protocol, the score board judges whether the response data is correct or not by comparing the difference and the similarity between the response data collected from the SOC chip system to be tested and an expected value, and gives a mark and a conclusion of whether the test case passes or not to be printed.

3) The script file specifies design codes by setting a top module of the SOC chip system to be tested and a file list containing all the codes, specifies verification codes participating in simulation by defining the names of test cases, and distinguishes simulation types by defining global variables, such as front simulation, back simulation, whether a waveform file needs to be reserved, the scale of regression test and the like.

2. Test case classification to improve verification efficiency

1) Validating processor-related scenarios: and when the scene related to the processor is verified in a C + Python mode, the C language and the Python language are used for respectively constructing the excitation of the hardware part and the operation of the software part.

2) Scenarios where processor involvement may be ignored: skipping the cpu initiator, only the random constraint properties that cocotb has are used to construct a random verification use case.

3. The verification method, as shown in fig. 2:

the method comprises the following steps: the test case is designated by assigning a global variable, and the operation is started; compiling the RTL code of the SOC to be tested by using a simulation tool; running a compiling code to start simulation, and performing simulation control on a hardware platform by using a GPI interface in the first graph;

step two: if the global variable is defined as a CPU participation value, the CPU loads an instruction of a corresponding test case through flash after being electrified and converts the instruction into a hardware behavior; otherwise, resetting the CPU to stop working, directly executing codes in the test case, and simulating the behavior of the CPU for the bus model by the excitation source;

step three: if the CPU participates, controlling the CPU to configure related functions of the design to be tested according to the verification scene, and responding feedback information (such as interruption) of other equipment by the CPU; if the CPU control is not needed, the SOC to be tested enters a working mode required by the verification scene through bus configuration in a Python test case;

step four: signal level excitation generation and transmission: generating random data in a certain range according to the scene and function requirements, and sending the random data to a hardware interface through a layering path of signals in a hardware platform;

step five: signal beam excitation generation and transmission: according to the scene and function requirements, random data in a certain range is generated for each signal in the signal beam, and the excitation data is sequentially or simultaneously driven to a plurality of hardware interfaces corresponding to the signal beam according to the behavior time sequence requirement defined in the excitation model so as to enable the hardware interfaces to meet the behavior specification of the interfaces, such as the communication protocol of a bus.

Step six: and response collection and judgment, collecting a response according to a time sequence requirement by the excitation model, judging whether the response is expected data in the score board, if so, giving a mark that the test case passes, waiting for finishing simulation after all codes are executed, and if not, printing error information and finishing simulation.

A system-level verification system and a method of an SOC chip are disclosed, wherein the verification system is based on an open source framework of COCOTB, is realized by Python, is easy to build, and does not need to build a complex UVM verification environment.

The system can use the bus behavior for injecting excitation or reading c program injecting excitation through different test cases, and can compare bus models, clock models, reset models and the like developed in the system as reference models when verifying functions of bus connection, concurrent access, interrupt connection, interrupt response, clock, reset and the like in the system on the premise of no IPlevel verification environment and relevant tests.

The system traverses all state spaces by using a random constrained function, and establishes a functional coverage rate model to converge the coverage rate to reach a delivery level.

(1) The verification system comprises:

part of dut rtl File and filelist

Python moiety: the method is used for testing the use cases with different functions, and the flow of repeated configuration in different test use cases forms the class of the environment component.

Other models are as follows: external device model for simulation

Makefile: and (4) guiding compiling and simulation, and distinguishing front simulation, rear simulation and regression behavior.

(2) Flow of verification

1. Verification environment construction

2. Script development: front simulation, back simulation, regression test

3. Verification plan

4. Test case development and pre-simulation

5. Regression testing

6. Post simulation

In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, where the computer storage medium is capable of storing a computer program, and the computer program may run the inventive content of the SOC chip system-level verification system and method provided by the present invention and some or all of the steps in each embodiment when executed by the data processing unit. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like.

It is clear to those skilled in the art that the technical solutions in the embodiments of the present invention can be implemented by means of a computer program and its corresponding general-purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a computer program, that is, a software product, which may be stored in a storage medium and includes several instructions to enable a device (which may be a personal computer, a server, a single chip, an MUU, or a network device) including a data processing unit to execute the method in each embodiment or some parts of the embodiments of the present invention.

The present invention provides a system-on-chip (SOC) system-level verification system and method, and a plurality of methods and approaches for implementing the technical solution, and the above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and modifications may be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention. All the components not specified in the present embodiment can be realized by the prior art.

Claims (10)

1. An SOC chip system-on-a-chip verification system, comprising: a hardware platform top layer, a verification platform and a script file;

the verification platform is connected with the top layer of the hardware platform through a GPI interface, completes the excitation drive of the verification platform on hardware in the SOC chip system to be tested, and acquires hardware data; the script file specifies a design code and a verification code in the SOC chip system to be tested and specifies a simulation type; and the top layer of the hardware platform is used for running hardware in the SOC chip system to be tested.

2. The SOC chip system-on-a-chip verification system of claim 1, wherein the hardware platform top layer comprises: the design to be tested is an SOC chip system to be tested and an external equipment model; the top layer of the hardware platform runs in an emulator.

3. The SOC chip system-on-verification system of claim 2, wherein the verification platform comprises: test cases, excitation models, and scoreboards.

4. An SOC system-on-chip verification system according to claim 3, wherein the test cases include two types of coroutines, namely a commonly configured coroutine and a function-specific coroutine: according to the workflow progress configuration of different functional modules, the coroutine completes the drive and acquisition of hardware signals by accessing the hierarchical path of the hardware signals in the top layer of the hardware platform, and the hardware platform is usually communicated with the signal level.

5. The SOC chip system-on-chip verification system according to claim 4, wherein the excitation model is used for signal beams following a set protocol: and the communication bus completes the driving of excitation and the acquisition of response according to an interface protocol and performs signal beam level communication with the hardware platform.

6. The SOC chip system-in-a-chip verification system according to claim 5, wherein the scoreboard determines if the response data is correct by comparing the difference between the response data collected from the SOC chip system under test and the expected value, gives an indication of whether the test case passed or not, and prints the conclusion.

7. The SOC chip system-on-chip verification system according to claim 6, wherein the script file is used to set test parameters, including: designing codes are designated by setting a top module of the SOC chip system to be tested and a file list containing all the codes; specifying verification codes participating in simulation by defining names of test cases; the simulation types are distinguished through the definition of global variables.

8. The system-on-a-chip verification system of claim 7, wherein the test parameters set by the script file comprise: pre-simulation, post-simulation, whether a waveform file needs to be reserved, and the scale of the regression test.

9. The SOC chip system-in-a-level verification system according to claim 8, wherein the test cases are classified according to scenes by the following specific method:

validating processor-related scenarios: respectively constructing the operation of a software part and the excitation of a hardware part by using a C language and a Python language in a C + Python mode;

ignoring the processor participation scenario: and skipping a cpu start program in the SOC chip system to be tested, and only using the random constraint characteristics of the cocotb verification framework to construct the excitation of the hardware part.

10. An SOC-chip system-in-verification method, characterized in that a SOC-chip system-in-verification system as claimed in claim 9 is used for verification, comprising the steps of:

the method comprises the following steps: the test case is designated by assigning a global variable, and the operation is started; compiling an RTL code in the SOC chip system to be tested by using a simulation tool; running the compiling code to start simulation, and performing simulation control on a hardware platform by using a GPI interface;

step two: if the global variable is defined as a CPU participation value, the CPU loads an instruction of a corresponding test case through flash after being electrified and converts the instruction into a hardware behavior; otherwise, resetting the CPU to stop working, directly executing Python codes in the test case, and exciting the source to simulate the behavior of the CPU by the bus model;

step three: if the CPU participates, controlling the CPU to configure related functions of the design to be tested in the SOC chip system to be tested according to the verification scene, and responding feedback information of other equipment by the CPU; if the CPU control is not needed, the SOC chip system to be tested enters a working mode required by the verification scene through bus configuration in a Python test case;

step four: signal level excitation generation and transmission: generating random data according to the scene and function requirements, and sending the random data to a hardware interface through a layering path of signals in a hardware platform;

step five: signal beam excitation generation and transmission: generating random data for each signal in the signal beam according to the scene and function requirements, and driving the excitation data to a hardware interface corresponding to the signal beam according to the behavior time sequence requirement defined in the excitation model so as to enable the excitation data to meet the behavior specification of the interface;

step six: and response collection and judgment, collecting a response according to a time sequence requirement by the excitation model, judging whether the response is expected data in the score board, if so, giving a mark that the test case passes, waiting for finishing simulation after all codes are executed, and if not, printing error information and finishing simulation.

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