CN101008915A - Automatic verification method of network chip - Google Patents
Automatic verification method of network chip Download PDFInfo
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- CN101008915A CN101008915A CN 200610063602 CN200610063602A CN101008915A CN 101008915 A CN101008915 A CN 101008915A CN 200610063602 CN200610063602 CN 200610063602 CN 200610063602 A CN200610063602 A CN 200610063602A CN 101008915 A CN101008915 A CN 101008915A
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Abstract
This invention relates to network chip automatic test method, which establishes one set of automatic edit to fulfill whole process, which comprises the following steps: establishing or updating test environment through int order composed of file to be tested, reference module file and test platform file to new edit; then through runc order to fulfill test environment edit; then through runs order control test environment bar or vectors; finally fulfilling results through cktest order to print results.
Description
Technical field
The present invention relates to the checking of network chip function, mainly be meant a kind of automatic verification method of network chip.
Background technology
In recent years, internet develop rapidly.Along with rapid development of Internet, the use of the network switch is also more and more wider, and the scale of network exchanging chip is also increasing, up to ten million easily door, and tens modules are to the checking of chip functions become increasingly complex (the seeing Fig. 1, Fig. 2) that also become.
Vector to network chip verification usually reaches thousands of, with possibility various case in the simulation actual exchange.Because chip comprises a large amount of functions, and the cooperation between the function,, need a large amount of test vectors equally if verify completely.So numerous test vectors must cause numerous operation results to need to analyze.If design incumbent what change, all test vectors all are necessary to rerun once, with correctness and the completeness of guaranteeing to change.This shows that the time of one-time authentication may reach very long, such as several days even a week, checking slip-stick artist's workload also became very big.
Because being on a grand scale of chip, each project team's exploitation and maintenance module separately in case any renewal is arranged, all need to be reflected in the verification environment, to participate in checking.The checking slip-stick artist needs constantly to upgrade design to be measured, and the renewal of code has often taken place in the checking operational process, and the checking slip-stick artist then needs the change of identifying code to come analysis result.
With the 24+2 exchange chip that the present invention relates to is example, the one-time authentication process often needs up to a hundred vectors, if according to traditional verification mode, the checking personnel need copy up to a hundred vectors in the verification environment after the renewal, compile test platform then, then move test vector one by one, and analysis result.According to 10 minutes consuming time meters of an average vector, the checking slip-stick artist needed thousands of minutes just can finish one-time authentication, and owing to long-time repetitive operation, it also is inevitable going wrong simultaneously.
Summary of the invention
The automatic verification method that the purpose of this invention is to provide a kind of network chip, by setting up a cover robotization checking script, can finish all processes of checking, the verification operation personnel need not to grasp or understand complicated verification environment, only need this cover script of study can carry out chip checking, solved the defective that the existing network chip verification method exists preferably.
Realize that technical scheme of the present invention is: this method comprise by a cover operating instruction set up automatically verification environment, configuration surroundings, automatically move test vector, finish interpretation of result and print and generate report automatically, comprising setting up a cover robotization checking script, finish all processes of checking, be characterized in that described robotization checking script comprises
At first, create or the renewal verification environment by the int instruction, design document to be measured, reference model file and verification platform file that instruction execution back environment is comprised all are updated to latest edition or indicated release;
Then, finish compiling by runc instruction to verification environment;
Then, by runs instruction control verification environment operation wall scroll or many vectors;
At last, after operation finishes, finish analysis, and print analysis result and preserve the result by cktest instruction.
This technical scheme also comprises:
This instruction can cooperate the verification environment of setting up based on the suitable various emulation demands of various platforms with the CVS server, verification environment is free to be based upon on the kinds of platform and satisfies multiple demand, wherein the int instruction is used to set up the integrated emulation environment, and its parameter is as follows:
int [-t<int_name>-rm-rtl-tb-vt-mo-novt]
-t＜int_name〉appointment integrated verification environment name;
-rm upgrades the reference model code;
-rtl upgrades design code to be measured;
-tb refresh test platform code;
-vt refresh test vector;
-mo upgrades the monitoring document code;
-novt upgrades all source files except vector.
Described runc order is used to compile verification environment, and its parameter is as follows:
runc [-t<int_name>-rm-rtl-sw-m<module_name>-g-fsdb]
-t＜int_name〉appointment integrated verification environment name;
-rm only compiles reference model and test platform;
-rtl only compiles design to be measured and test platform;
The code of waveform is supported in-sw compiling;
-m＜module_name〉specify and need be embedded into the module name of verifying in the reference model.
Described runs is used to move emulation, and its parameter is as follows:
runs [-t?<int_name>-v<vector>-b<vect?list>-s-sw]
-t＜int_name〉appointment integrated verification environment name;
-v＜vector〉need the test vector name of operation;
-b＜vect list〉need the list name of the test vector of operation;
-sw operational process needs the wave file switch.
Described ckcode is used to check and verify the code of environment and the consistance of design code, and inconsistent code file is printed, and its parameter is as follows:
ckcode [-t<int_name>]
-t＜int_name〉appointment integrated verification environment name.
Described cktest is used to check the result of emulation, the response file .ref consistance of the response file .dump of design output more to be measured and reference model output, and its parameter is as follows:
cktest-t<int_name-m<module>-v<vect_name>-b<list_file>-f<num>-nocase
-t＜int_name〉appointment integrated verification environment name;
-m＜module〉analyze the consistance of designated module;
-v＜vect_name〉specify and to need the vector of analysis result name;
-b＜list_file〉specify the vector lists need analysis result;
-f＜num〉regional number specify to need analyzed;
-nocase analysis result case-insensitive switch;
-o analyzes the zone marker OK that passes through;
-short prints the filename of analysis in brief mode.
The beneficial effect that the present invention has: use verification method of the present invention, checking slip-stick artist's workload and error rate all reduce greatly.The checking slip-stick artist can finish whole verification process by keying in one or several instruction after the preparation of finishing test vector, after operation finishes, key in the analysis that the result is finished in one or several instruction with crossing, and obtains formal analytical documentation.Whole process is finished by machine, and its error rate is reduced to minimum.
Description of drawings
Fig. 1 is traditional chip checking environment block diagram.
Fig. 2 is traditional proof procedure block diagram.
Fig. 3 is a proof procedure block diagram of the present invention.
Fig. 4 is the present invention needs the interface operable instruction by checking personnel before and after simplifying a contrast block diagram.
Embodiment
The present invention will be further described below in conjunction with accompanying drawing:
Utilize the script can the above-mentioned checking thinking of very simple realization.
With the 24+2 exchange chip that the present invention relates to is example, describes the details that automatic verification method is implemented.
At first, or the checking personnel create the renewal verification environment by the int instruction, and design document to be measured, reference model file and verification platform file that instruction execution back environment is comprised all are updated to latest edition or indicated release.
Then, the checking personnel finish compiling to verification environment by runc instruction.
Then, the checking personnel are by runs instruction control verification environment operation wall scroll or many vectors.
At last, after operation finished, the checking personnel finished analysis to the result by cktest instruction, and printed analysis result and preserve.
As seen, whole loaded down with trivial details proof procedure taper to above four the step finish.
Following detailed directive script and the parameter that uses for the present invention.
1.int order is used to set up the integrated emulation environment, the meaning of int is integration.This order can make verification environment be free to be based upon on the kinds of platform cooperate the verification environment of setting up based on the suitable various emulation demands of various platforms with the CVS server.
Parameter is as follows:
int [-t<int_name>-rm-rtl-tb-vt-mo-novt]
-t＜int_name〉appointment integrated verification environment name.
-rm upgrades the reference model code.
-rtl upgrades design code to be measured.
-tb refresh test platform code.
-vt refresh test vector.
-mo upgrades the monitoring document code.
-novt upgrades all source files except vector.
The version information of-r appointment codes
-fpga sets up and renewal FPGA verification environment
2.runc order is used to compile verification environment.
Parameter is as follows:
runc [-t<int_name>-rm-rtl-sw-m<module_name>-g-fsdb]
-t＜int_name〉appointment integrated verification environment name.
-rm only compiles reference model and test platform.
-rtl only compiles design to be measured and test platform.
The code of waveform is supported in-sw compiling.
-m＜module_name〉specify and need be embedded into the module name of verifying in the reference model.
3.runs be used to move emulation.
Parameter is as follows:
runs [-t<int_name>-v<vector>-b<vect?list>-s-sw]
-t＜int_name〉appointment integrated verification environment name.
-v＜vector〉need the test vector name of operation.
-b＜vect list〉need the list name of the test vector of operation.
-sw operational process needs the wave file switch.
4.ckcode be used to check and verify the code of environment and the consistance of design code, and inconsistent code file printed.
Parameter is as follows:
ckcode [-t<int_name>]
-t＜int_name〉appointment integrated verification environment name
5.cktest be used to check the result of emulation, the response file .dump of design more to be measured output and
The response file .ref consistance of reference model output.
Parameter is as follows:
cktest-t<int_name>-m<module>-v<vect_name>-b<list_file>-f<num>-nocase
-t＜int_name〉appointment integrated verification environment name.
-m＜module〉analyze the consistance of designated module.
-v＜vect_name〉specify and to need the vector of analysis result name.
-b＜list_file〉specify the vector lists need analysis result.
-f＜num〉regional number specify to need analyzed.
-nocase analysis result case-insensitive switch
-o analyzes the zone marker OK that passes through.
-short prints the filename of analysis in brief mode.
Claims (6)
1. the automatic verification method of a network chip comprises and sets up a cover robotization checking script, finishes all processes of checking, it is characterized in that described robotization checking script comprises
A. at first, create or the renewal verification environment by the int instruction, design document to be measured, reference model file and verification platform file that instruction execution back environment is comprised all are updated to latest edition or indicated release;
B. then, finish compiling by runc instruction to verification environment;
C. follow, by runs instruction control verification environment operation wall scroll or many vectors;
D. last, after operation finishes, finish analysis, and print analysis result and preserve the result by cktest instruction.
2. the automatic verification method of network chip as claimed in claim 1 is characterized in that described int instruction is used to set up the integrated emulation environment, and its parameter is as follows:
int[-t<int_name>-rm-rtl-tb-vt-mo-novt]
-t＜int_name〉appointment integrated verification environment name;
-rm upgrades the reference model code;
-rtl upgrades design code to be measured;
-tb refresh test platform code;
-vt refresh test vector;
-mo upgrades the monitoring document code;
-novt upgrades all source files except vector.
3. the automatic verification method of network chip as claimed in claim 1 is characterized in that described runc order is used to compile verification environment, and its parameter is as follows:
runc[-t<int_name>-rm-rtl-sw-m<module_name>-g-fsdb]
-t＜int_name〉appointment integrated verification environment name;
-rm only compiles reference model and test platform;
-rtl only compiles design to be measured and test platform;
The code of waveform is supported in-sw compiling;
-m＜module_name〉specify and need be embedded into the module name of verifying in the reference model.
4. the automatic verification method of network chip as claimed in claim 1 is characterized in that described runs is used to move emulation, and its parameter is as follows:
runs[-t<int_name>-v<vector>-b<vect?list>-s-sw]
-t＜int_name〉appointment integrated verification environment name;
-v＜vector〉need the test vector name of operation;
-b＜vect list〉need the list name of the test vector of operation;
-sw operational process needs the wave file switch.
5. the automatic verification method of network chip as claimed in claim 1 is characterized in that described ckcode is used to check and verify the code of environment and the consistance of design code, and inconsistent code file is printed that its parameter is as follows:
ckcode[-t<int_name>]
-t＜int_name〉appointment integrated verification environment name.
6. the automatic verification method of network chip as claimed in claim 1 is characterized in that described cktest is used to check the result of emulation, the response file .ref consistance of the response file .dump of design output more to be measured and reference model output, and its parameter is as follows:
cktest-t<int_name>-m<module>-v<vect_name>-b<list_file>-f<num>-nocase
-t＜int_name〉appointment integrated verification environment name;
-m＜module〉analyze the consistance of designated module;
-v＜vect_name〉specify and to need the vector of analysis result name;
-b＜list_file〉specify the vector lists need analysis result;
-f＜num〉regional number specify to need analyzed;
-nocase analysis result case-insensitive switch;
-o analyzes the zone marker OK that passes through;
-short prints the filename of analysis in brief mode.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100636027A CN100451986C (en) | 2006-12-29 | 2006-12-29 | Automatic verification method of network chip |
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|---|---|---|---|
| CNB2006100636027A CN100451986C (en) | 2006-12-29 | 2006-12-29 | Automatic verification method of network chip |
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| CN101008915A true CN101008915A (en) | 2007-08-01 |
| CN100451986C CN100451986C (en) | 2009-01-14 |
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| CN100583057C (en) * | 2008-04-22 | 2010-01-20 | 中国科学院软件研究所 | Credible password module test case creation method and its test system |
| CN101183400B (en) * | 2007-12-21 | 2011-06-15 | 威盛电子股份有限公司 | Debugging and checking method and system in graph hardware design |
| CN101763451B (en) * | 2010-01-01 | 2012-07-18 | 江苏华丽网络工程有限公司 | Method for establishing large-scale network chip verification platform |
| CN103713993A (en) * | 2013-05-30 | 2014-04-09 | 深圳市汇春科技有限公司 | Chip verification platform and method for implementing chip testing |
| CN104714887A (en) * | 2015-03-09 | 2015-06-17 | 浪潮集团有限公司 | Method for achieving random verification through normal distribution |
| CN106529099A (en) * | 2016-12-20 | 2017-03-22 | 盛科网络（苏州）有限公司 | Method for automatically generating verification model on the basis of interface |
| CN108052373A (en) * | 2017-12-22 | 2018-05-18 | 福建星网智慧科技股份有限公司 | Method of the container generation with recovering with network is realized based on runC |
| CN113094274A (en) * | 2021-04-14 | 2021-07-09 | 深圳忆联信息系统有限公司 | Python-based FPGA (field programmable Gate array) verification method and device, computer equipment and storage medium |
| CN113485875A (en) * | 2021-05-20 | 2021-10-08 | 新华三半导体技术有限公司 | Chip verification system and verification method |
| CN116562204A (en) * | 2023-07-12 | 2023-08-08 | 英诺达(成都)电子科技有限公司 | Chip verification method and device, electronic equipment and computer readable storage medium |
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| JP2828590B2 (en) * | 1994-03-16 | 1998-11-25 | 株式会社日立製作所 | Microprogram verification method |
| JPH1139377A (en) * | 1997-07-24 | 1999-02-12 | Toshiba Corp | Method for verifying semiconductor integrated circuit, device for verifying semiconductor integrated circuit and computer readable recording medium recording verification program of semiconductor integrated circuit |
| US6539522B1 (en) * | 2000-01-31 | 2003-03-25 | International Business Machines Corporation | Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs |
| US6658633B2 (en) * | 2001-10-03 | 2003-12-02 | International Business Machines Corporation | Automated system-on-chip integrated circuit design verification system |
| CN100340987C (en) * | 2005-07-08 | 2007-10-03 | 北京中星微电子有限公司 | Chip examination system and method |
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| CN101183400B (en) * | 2007-12-21 | 2011-06-15 | 威盛电子股份有限公司 | Debugging and checking method and system in graph hardware design |
| CN100583057C (en) * | 2008-04-22 | 2010-01-20 | 中国科学院软件研究所 | Credible password module test case creation method and its test system |
| CN101763451B (en) * | 2010-01-01 | 2012-07-18 | 江苏华丽网络工程有限公司 | Method for establishing large-scale network chip verification platform |
| CN103713993A (en) * | 2013-05-30 | 2014-04-09 | 深圳市汇春科技有限公司 | Chip verification platform and method for implementing chip testing |
| CN104714887A (en) * | 2015-03-09 | 2015-06-17 | 浪潮集团有限公司 | Method for achieving random verification through normal distribution |
| CN106529099A (en) * | 2016-12-20 | 2017-03-22 | 盛科网络（苏州）有限公司 | Method for automatically generating verification model on the basis of interface |
| CN108052373A (en) * | 2017-12-22 | 2018-05-18 | 福建星网智慧科技股份有限公司 | Method of the container generation with recovering with network is realized based on runC |
| CN113094274A (en) * | 2021-04-14 | 2021-07-09 | 深圳忆联信息系统有限公司 | Python-based FPGA (field programmable Gate array) verification method and device, computer equipment and storage medium |
| CN113094274B (en) * | 2021-04-14 | 2023-10-13 | 深圳忆联信息系统有限公司 | Python-based FPGA verification method and device, computer equipment and storage medium |
| CN113485875A (en) * | 2021-05-20 | 2021-10-08 | 新华三半导体技术有限公司 | Chip verification system and verification method |
| CN113485875B (en) * | 2021-05-20 | 2024-07-19 | 新华三半导体技术有限公司 | Chip verification system and verification method |
| CN116562204A (en) * | 2023-07-12 | 2023-08-08 | 英诺达(成都)电子科技有限公司 | Chip verification method and device, electronic equipment and computer readable storage medium |
| CN116562204B (en) * | 2023-07-12 | 2023-09-22 | 英诺达(成都)电子科技有限公司 | Chip verification method and device, electronic equipment and computer readable storage medium |
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