CN103713993A - Chip verification platform and method for implementing chip testing - Google Patents
Chip verification platform and method for implementing chip testing Download PDFInfo
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Abstract
The invention provides a chip verification platform and a method for implementing chip testing. The chip verification platform comprises a to-be-tested design, a behavior-level functional model and an LCD (liquid crystal display) model or a Y2 interface model, wherein the behavior-level functional model comprises an infrared transmitter model, an input and output port model and a crystal oscillator model; and chip testing functions are expanded by using the LCD model or the Y2 interface model. A single-input-parameter test case script is established and cited; input and output files of various test cases are uniformly defined so that a combined testing case for performing combined testing on a plurality of testing cases is established; manual intervention is not required when the combined testing case runs; results of the testing cases are judged automatically; and the reliability and the repeatability are high.
Description
Technical field the present invention relates to chip verification platform, is for the checking of integrated circuit (IC) design and the easily-testing platform of making.
Background technology is along with the development of SIC (semiconductor integrated circuit), and the scale of integrated circuit (IC) chip is increasing, and the module comprising is also more and more.For the ease of fast and accurately chip being verified, use test platform (testbench) is also debugged to reach from software aspect based on this test platform the checking of the various functions of chip has been become to a kind of prevalent means.Application number is that 200510007449.1 Chinese patent application discloses a kind of more representational verification platform and software and hardware architecture thereof.
At existing use test platform, chip is carried out under the occasion of proof procedure, checking slip-stick artist need to use a lot of test cases of VERILOG language compilation.General checking slip-stick artist writes various excitation files according to the MID(module interface description) of design to be measured (comprising chip to be verified), this excitation file converts on the design circuit that corresponding pumping signal is communicated to design to be measured by verification platform, and checking slip-stick artist responds to judge that by observing the output of this design circuit whether test is correct again.Described observation is such as but not limited to the output waveform of artificial visual inspection emulator, and some checking slip-stick artist can write one in order to the behavioral scaling model of automatic decision, and the configuration of even going deep into chip internal for some is forced mark with FORCE statement.
Above-mentioned the deficiencies in the prior art part is, for emerging, comprise that LCD touches the various chips of chip, increase along with chip design scale, the way that the hand test of this manual intervention of employing observation output waveform obtains test result is not only original but also simple, reliability and reusability are not high, waste time and energy and cannot meet the requirement in PROJECT TIME; In addition,, because the function of design circuit is tending towards diversity, it is also a problem that the linking that how to solve a plurality of content measurements completes chip testing as early as possible.
Summary of the invention the technical problem to be solved in the present invention is to avoid above-mentioned the deficiencies in the prior art part and proposes a kind of chip verification platform and it realizes the method for chip testing, to reach automatically, to complete fast and efficiently chip testing.
As the technical scheme solving the problems of the technologies described above, be, provide a kind of chip verification platform to realize the method for chip testing, comprise the step that builds chip verification platform, this verification platform comprises design to be measured and some behavioral scaling functional modes, and described behavioral scaling functional mode comprises infrared transmitter model, input/output port model or crystal oscillator model; Especially, also comprise: by setting up the test cases script of a single input parameter, for each test cases, quote, and adopt unified definition to set up the translocation case step of several test cases translocations to the input-output file of each test cases; Wherein each test cases includes the sub-step that coding provides the sub-step of test and excitation, current test cases emulation to finish to output test result to described design to be measured; Move the step of described translocation case.
In such scheme, the operation of described translocation case comprises process: operation translocation case case script; Call and move the test cases script with first single input parameter; Call and move the test cases script with second single input parameter; By that analogy, until each test cases script is called and end of run.
Particularly, the calling and move and comprise process of test cases script described in each: create a current test cases file of the same name with this list input parameter according to be with single input parameter; Enter this document folder and call VCS emulator and enter emulation, call and move the assembly code text of the same name with this list input parameter or the excitation file of the same name with this list input parameter; According to current automatic test emulation result, generate the destination file of the same name with this list input parameter, finish and exit current test cases file.
In such scheme, described automatic test emulation result is to judge according to the specific executive address of assembly code program.Can be, after the correct entry address of described assembly code text Program comes error portal address.
In such scheme, described design to be measured comprises that LCD touches chip, and correspondingly, described behavioral scaling functional mode also comprises LCD model, and the LCD interface that connects design to be measured is to receive and to show the displaying contents from design to be measured.Described behavioral scaling functional mode also comprises Y2 interface model, connects the Y2 interface of reception survey design to communicate.
As the technical scheme solving the problems of the technologies described above still, a kind of chip verification platform is provided, comprise design to be measured and behavioral scaling functional mode, described behavioral scaling functional mode comprises infrared transmitter model, input/output port model and crystal oscillator model, the infrared remote control interface that wherein infrared transmitter model connects reception survey design is to receive and to check the remote control square wave from design to be measured, input/output port model connects the digital port of design to be measured to communicate, and crystal oscillator model connects the crystal oscillator interface of design to be measured to provide clock to this design to be measured; Especially: described behavioral scaling functional mode also comprises LCD model, the LCD interface that connects design to be measured is to receive and to show the displaying contents from design to be measured.
In such scheme, described behavioral scaling functional mode also comprises Y2 interface model, connects the Y2 interface of reception survey design to communicate.
With existing other technology comparison, the inventive method is applicable to different test cases can carry out unified result judgement, is convenient to realize the translocation of a plurality of test cases, and test result automatic comparison, without manual intervention, has suitable reliability and reusability.In addition, verification platform of the present invention to the expansion of behavioral scaling functional mode make can test chip type increase, and test function is more.
Accompanying drawing explanation
Fig. 1 is the framework of verification platform of the present invention;
Fig. 2 a is single LCD displaying principle schematic diagram, and Fig. 2 b is that a numeral shows exemplary plot;
Fig. 3 is assembly routine example architecture figure of the present invention;
Fig. 4 is translocation case case script topology example figure of the present invention.
Embodiment
Below, the most preferred embodiment shown in by reference to the accompanying drawings is further set forth the present invention.
Fig. 1 has illustrated the system architecture of verification platform of the present invention.Verification platform comprises design to be measured and behavioral scaling functional mode.Described design to be measured (DUT, Design Under Testbench) comprises design circuit, as chip, is the target being verified.This target being verified often comprise a CPU core and take as central control unit, comprise the unit such as ROM, RAM, counter, and the interface of for example, controlling by various modules (crystal oscillator module interface, infrared emittance control module, input and output port module).The chip of our company's exploitation has also comprised COM driver module and the SEG driver module that is used for connecting LCD display interface, is used for connecting the Y2 interface module of Y2 interface.Behavioral scaling functional mode (BFM, Behavior Function Model) is the application working environment of analog chip, and has configurable advantage, is convenient to user's method with software on emulator and fully debugs chip functions.User changes pumping signal by changing the parameter of behavioral scaling functional mode, and then the response being obtained by design to be measured judges whether design to be measured reaches requirement target.Conventional behavioral scaling functional mode has infrared transmitter model, input/output port model and crystal oscillator model at present.The infrared remote control interface (comprising pulse delivery outlet REM) that wherein infrared transmitter model connects reception survey design is to receive and to check the remote control square wave from design to be measured, input/output port model connect design to be measured digital port (such as but not limited in 54 bit parallel mouth PORTA～E any or a plurality of) to communicate, crystal oscillator model connects the crystal oscillator interface (comprising two clock line OSC and OSCX) of design to be measured to provide clock to this design to be measured.
Verification platform of the present invention touches chip for LCD, a kind of new behavioral scaling functional mode is proposed, be the behavioral scaling model (for simplicity, be called for short LCD model) of LCD display, the LCD interface that is used for connecting design to be measured is to receive and to show the displaying contents from design to be measured.As shown in Figure 1, the LCD interface of design to be measured provides some road SEG and some roads COM signal, to show corresponding numeral or radix point in LCD display, complete display effect is such as but not limited to as shown in Figure 2 a, " * " represents to light field, each adjacent letter is lighted symbol (the non-display effect part of field with numeral for this, only signal is used), by controlling, different light field and can show 15 numerals and 15 radix point, and make it by 1/3, 1/4, 1/5 or 1/6 dutycycle shows, and automatically carry out frequency sweeping, automatically carry out frame comparison.Visible according to Fig. 1, in design to be measured, CPU controls LCD power module by unit control circuit; Connect and that affect LCD interface displaying contents is LCD RAM, so user can programme to specify the content of demonstration to LCD RAM, comprise numeral.Even further comprise and show a plurality of numerals or character.For example, by LCD RAM, programme, it to show numeral " 2.3 "; In emulation, the numeral 2.3 and (constantly the refreshing) that in lcd screen, demonstrate as shown in Figure 2 b continue to show this numeral 2.3, judge that Presentation Function is verified so, otherwise the checking of judgement Presentation Function is not passed through.
Verification platform of the present invention touches chip for LCD, proposes a kind of new behavioral scaling functional mode, and Y2 interface model, connects the Y2 interface of reception survey design to communicate.Y2 interface is the pioneering a kind of two-wire serial communication interface standard proposing of our company, and utilizing two signal wires is that clock line Y2CK and data line Y2D carry out the bidirectional data transfers between two machines.This agreement concrete regulation the signal intensity on clock line Y2CK and data line Y2D in data transmission procedure, and 4 basic commands that concrete rendezvous protocol is supported " are write data ", the signal wire operating process under " read data ", " write address " and " reading address ".The foundation of Y2 interface model, 4 basic command operating process of described Y2 interface are packaged into a set of instruction set that comprises some instructions, user makes for realizing the operation to Y2 interface by these instructions, work can be freed from the processing of bottom physical signalling, thereby most of energy is focused on and in functional verification, removes to improve verification efficiency.Described instruction set is such as but not limited to comprising 9 instructions as shown in the table:
According to these instructions, can realize OTP(One-time programmble in DUT sheet, One Time Programmable chip) programming, or with debug host identity, visit register and the storage unit of DUT, thus checking DUT various functions.
According to above-mentioned, the existing method that realizes chip testing often comprises the step that builds chip verification platform, this verification platform comprises design to be measured and some behavioral scaling functional modes, and described behavioral scaling functional mode comprises infrared transmitter model, input/output port model or crystal oscillator model; The inventive method also increases LCD model and is convenient to the checking achievement that shows directly perceived in described behavioral scaling functional mode, increases Y2 interface model, is used for the chip with Y2 interface to communicate checking.But from angle easy to verify, the contribution of the inventive method maximum is, also comprise by setting up the test cases script of a single input parameter and quoting for each test cases, and adopt unified definition to set up the translocation case step of several test cases translocations to the input-output file of each test cases; And the step of moving described translocation case.Wherein, each test cases includes coding and provides the sub-step of test and excitation, the sub-step that present case emulation finishes to output test result to described design to be measured.
Fig. 4 be take script run_all as a described translocation case of illustration meaning.This script comprises several test cases scripts run_vcs, and this run_vcs script has a parameter, such as but not limited to testcase1, testcase2 or testcase3.Therefore run_vcs testcase1 and the run_vcs testcase2 corresponding different test cases of difference or test assignment.The process of moving this translocation case comprises: first move translocation case case script run_all, thereby call and move the test cases script with first single input parameter; Then call and move the test cases script with second single input parameter; By that analogy, until each test cases script is called and end of run.
Wherein, the calling and move and comprise process of test cases script described in each: take testcase1 as example, first create a current test cases file testcase1 of the same name with this list input parameter according to be with single input parameter; Enter again this document folder and call VCS emulator and enter emulation, call and move the assembly code text testcase1.txt of the same name with this list input parameter or the excitation file testcase1.v of the same name with this list input parameter; According to current automatic test emulation result, generate the destination file testcase1.log of the same name with this list input parameter, finish and exit current test cases file.Like this, unify to name all with the relevant input-output files of current test cases by an input parameter, only different suffix in addition, are convenient to the realization of automatized script, and file directory is unified and attractive in appearance simultaneously.
For individual test case, common scene is the verilog excitation input that only gives DUT expection, and verification platform automatically detects and the output response of DUT is judged, and when all responses all meet expection, thinks to test and passes through; Otherwise test is not passed through.Existing method is when doing translocation for different cases, a little inconsistent because of makeing mistakes of different test cases, must write different wrong processing modes for different test cases.The method that the present invention adopts is for this reason that described automatic test emulation result adopts and judges according to the specific executive address of assembly code program.Such as but not limited to as shown in Figure 3, when writing assembly routine, because the entry program of general MCU is from 0000H, we reserved 0044H is that misaddress entrance, 0088H are that correct entry address, 0002H～0004H are various interruption entrances.Like this, when assembly routine judgement makes mistakes, program jumps to 0044H address, does endless loop; When the whole tests of assembly routine are passed through, program jumps to 0084H address, does endless loop.Coding style based on unified like this, the inventive method is surveyed the address of program execution always or after waiting for a schedule time, when 0044H being detected, just thinks that test makes mistakes; When 0088H being detected, just think to test and pass through, automatic decision mechanism is provided thus.In this assembly code text embodiment, after the correct entry address of program comes error portal address, even if from the beginning the program that can guarantee is run and flown, also can first detect misaddress, thereby finish in advance emulation.
In sum, the best implementing procedure of translocation case run_all is expressed as in detail: l
1, operation run_all script;
2, run_all script calls run_vcs testcase1 script;
3, run_vcs script, according to input parameter testcase1, creates current test cases file, and name is testcase1;
4, enter testcase1 file, call VCS emulator, carry out emulation, in simulation process, call testcase1.txt assembly code, call testcase1.v excitation file;
5, according to the judgement way of aforesaid test result, automatic detection simulation result, and generate result and have no testcase1.log, then finish current testcase1 test;
6, run_all script calls run_vcs testcase2 script;
7, use testcase2 parameter, circulation step 3 ~ 5;
By that analogy, execute all test cases.
Through emulation experiment, this method can be successfully applied to chip checking.
In sum, architectural feature of the present invention and each embodiment disclose all in detail, and can fully demonstrate the present invention, all have the progressive of enforcement in object and effect.
More than explanation be only the preferred embodiments of the present invention, can not be used for express limiting the scope that the present invention implements, i.e. all equivalences of doing according to the claims in the present invention change and modification, all should belong in the scope that patent of the present invention contains.
Claims (9)
1. a chip verification platform, comprise design to be measured and behavioral scaling functional mode, described behavioral scaling functional mode comprises infrared transmitter model, input/output port model and crystal oscillator model, the infrared remote control interface that wherein infrared transmitter model connects reception survey design is to receive and to check the remote control square wave from design to be measured, input/output port model connects the digital port of design to be measured to communicate, and crystal oscillator model connects the crystal oscillator interface of design to be measured to provide clock to this design to be measured; It is characterized in that: described behavioral scaling functional mode also comprises LCD model, the LCD interface that connects design to be measured is to receive and to show the displaying contents from design to be measured.
2. chip verification platform as claimed in claim 1, is characterized in that: described behavioral scaling functional mode also comprises Y2 interface model, connects the Y2 interface of reception survey design to communicate.
3. chip verification platform is realized a method for chip testing, comprises
The step that builds chip verification platform, this verification platform comprises design to be measured and some behavioral scaling functional modes, described behavioral scaling functional mode comprises infrared transmitter model, input/output port model or crystal oscillator model;
It is characterized in that, also comprise:
By setting up the test cases script of a single input parameter, for each test cases, quote, and adopt unified definition to set up the translocation case step of several test cases translocations to the input-output file of each test cases; Wherein each test cases includes the sub-step that coding provides the sub-step of test and excitation, current test cases emulation to finish to output test result to described design to be measured;
Move the step of described translocation case.
4. chip verification platform is realized the method for chip testing as claimed in claim 3, it is characterized in that, the operation of described translocation case comprises process:
Operation translocation case case script;
Call and move the test cases script with first single input parameter;
Call and move the test cases script with second single input parameter;
By that analogy, until each test cases script is called and end of run.
5. chip verification platform is realized the method for chip testing as claimed in claim 4, it is characterized in that the calling and move and comprise process of test cases script described in each:
According to be with single input parameter, create a current test cases file of the same name with this list input parameter;
Enter this document folder and call VCS emulator and enter emulation, call and move the assembly code text of the same name with this list input parameter or the excitation file of the same name with this list input parameter;
According to current automatic test emulation result, generate the destination file of the same name with this list input parameter, finish and exit current test cases file.
6. chip verification platform is realized the method for chip testing as claimed in claim 5, it is characterized in that, described automatic test emulation result is to judge according to the specific executive address of assembly code program.
7. chip verification platform is realized the method for chip testing as claimed in claim 6, it is characterized in that, after the correct entry address of described assembly code text Program comes error portal address.
8. chip verification platform is realized the method for chip testing as claimed in claim 3, it is characterized in that: described design to be measured comprises that LCD touches chip, correspondingly, described behavioral scaling functional mode also comprises LCD model, and the LCD interface that connects design to be measured is to receive and to show the displaying contents from design to be measured.
9. chip verification platform is realized the method for chip testing as claimed in claim 8, it is characterized in that: described behavioral scaling functional mode also comprises Y2 interface model, connects Y2 interface that reception surveys design to communicate.
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| CN112733490A (en) * | 2021-01-07 | 2021-04-30 | 苏州浪潮智能科技有限公司 | System-level verification method and system of chip and related device |
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Address after: 518000 Guangdong, Longgang District, Buji street, white pigeon cage Industrial Zone, West Wing, comprehensive building, west side of the building (Office) (two) () Patentee after: SHENZHEN YSPRING TECHNOLOGY CO., LTD. Address before: 518054 Guangdong Province, Shenzhen city Nanshan District District Science Park Song Ping Road No. 5 Building 6 floor B block jarta Patentee before: Shenzhen Huichun Technology Co.,Ltd. |