CN113866586A - System-level chip verification platform and verification method - Google Patents
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Abstract
The application discloses a verification platform and a verification method of a system-level chip, wherein the method comprises the following steps: building a simulation verification environment of the system level chip; creating a bus function model unit, and binding the bus function model unit to the same interface connected with a bus by a central processing unit; creating a universal verification methodology test case, and executing the universal verification methodology test case through the bus function model unit to realize the test of the system-on-chip; creating a plurality of software test cases; compiling the plurality of software test cases, and executing the compiled plurality of software test cases by the central processing unit to realize the test of the system-on-chip.
Description
Technical Field
The present invention relates to the field of simulation verification technologies, and in particular, to a verification platform and a verification method for a system-level chip.
Background
SoC (System on Chip) technology refers to the integration of a Central Processing Unit (CPU), input/output (I/O) peripherals, memory, and other functional peripherals on one Chip. The SoC technology can effectively reduce the area of the product, improve the performance of the product, reduce the power consumption of the product and improve the reliability of the product, thereby being widely applied. However, since the manufacturing cost of the chip is high, in order to ensure the function and performance of the SoC chip, a large amount of sufficient verification needs to be performed before the chip is taped.
The SoC chip in the prior art has two modes for verification. One is to execute a test pattern by a CPU, and in the verification mode, a professional must first implement a flow of compiling, loading (boot), and the like of a software code in a verification platform, and then can start simulation. This verification requires each verification engineer to have a deep knowledge of the CPU, especially in assembly language. Moreover, development of the flow of compiling, loading, and the like of the software code takes a certain time, which delays the time of starting the verification. The CPU is time-consuming to execute the software codes, and each software code can enter the test program after the same loading program is run, so that the verification progress is influenced. The other is to execute a test mode by using a Universal Verification Methodology (UVM) case, which cannot reuse a software test program.
Disclosure of Invention
The invention aims to provide a verification platform and a verification method of a system-level chip, which provide a flexible simulation verification mode and shorten the verification period.
One embodiment of the present application discloses a verification platform for a system-level chip, comprising:
at least one test module, each test module comprising a central processor unit, a bus function model unit and a universal verification methodology test case, the central processor unit being connected to a bus, the bus function model unit being bound to the same interface where the central processor unit is connected to the bus;
the universal verification methodology test case realizes the test through the bus function model unit, and the software test case realizes the test through the central processing unit or realizes the test through the bus function model unit through a direct programming interface.
In a preferred embodiment, the system further comprises a first selection switch, and the central processing unit and the bus function model unit are respectively connected or bound to the same bus interface of the bus through the first selection switch.
In a preferred embodiment, the system further comprises a second selection switch, and the direct programming interface and the universal verification methodology test case are respectively connected to the bus function model unit through the second selection switch.
In a preferred embodiment, the system-on-chip includes one or more central processor units, a plurality of IP core modules, and a bus, where each IP core module is connected to the bus, and the central processor unit is connected to the bus.
Another embodiment of the present application further discloses a system-on-chip verification method, including:
building a simulation verification environment of the system level chip;
creating a bus function model unit, and binding the bus function model unit to the same interface connected with a bus by a central processing unit;
creating a universal verification methodology test case, and executing the universal verification methodology test case through the bus function model unit to realize the test of the system-on-chip;
creating a plurality of software test cases;
compiling the plurality of software test cases, and executing the compiled plurality of software test cases by the central processing unit to realize the test of the system-on-chip.
In a preferred embodiment, before the step of binding the bus function model unit to the same interface of the central processing unit connected to the bus, the method further includes: the connection of the central processor unit to the bus is disabled.
In a preferred embodiment, before the step of compiling the plurality of software test cases and executing the compiled plurality of software test cases by the central processing unit to implement the test of the system on chip, the method further includes: selecting, by the bus functional model unit, a direct programming interface to execute a portion of the plurality of software test cases; compiling the rest of the plurality of software test cases, and executing the compiled plurality of software test cases by the central processing unit.
In a preferred embodiment, the direct programming interface is connected to the bus function model while the universal verification methodology test case is executed by the bus function model unit to realize the test of the system-on-chip, so that the direct programming interface is selected by the bus function model unit to execute a part of the plurality of software test cases.
In a preferred embodiment, the direct programming interface is selected by the bus function model unit to execute the software test case to realize the test of the system-on-chip, and the compiled software test case is compiled and loaded to execute the compiled software test case by the central processing unit.
In a preferred embodiment, the number of the universal verification methodology test cases for implementing the system on chip test is greater than the number of the central processing unit for implementing the system on chip test.
The embodiment provides a flexible verification mode, different verification modes can be adopted according to requirements, the coverage rate of verification can be ensured, the complexity of verification is reduced, and the verification period is shortened.
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Non-limiting and non-exhaustive embodiments of the present application are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
Fig. 1 is a schematic diagram illustrating a verification platform of a system on chip in an embodiment of the present application.
Fig. 2 is a more detailed schematic diagram of a system-on-chip verification platform according to an embodiment of the present application.
Fig. 3 shows a flowchart of a verification method of a system-on-chip in an embodiment of the present application.
Detailed Description
Various aspects and examples of the present application will now be described. The following description provides specific details for a thorough understanding and enabling description of these examples. However, it will be understood by those skilled in the art that the present application may be practiced without many of these details.
Additionally, some well-known structures or functions may not be shown or described in detail to facilitate brevity and avoid unnecessarily obscuring the relevant description.
Description of partial concepts:
and an IP kernel module: the IP (interactive performance) kernel module is a pre-designed or even verified component with certain function, which is used for chip designers to integrate and select, and a plurality of IP kernel modules are generally integrated in the SoC.
BFM: bus function model, Bus function model.
DPI: direct program interface, Direct programming interface.
VIP: verification IP, verifying the IP module.
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
A first embodiment of the present application relates to a verification platform for a system-on-chip, and fig. 1 shows a schematic structural diagram of the verification platform in an embodiment of the present application. The verification platform includes: at least one test module, for example, test modules 0 to k, each of which is connected to a BUS (BUS), and by which functional testing of each IP core module and combinations thereof in the system level chip is achieved.
FIG. 2 shows a more detailed schematic of verification platform 100 in an embodiment of the present application. The verification platform 100 includes: a design under test 110 and a simulation environment 120. The design under test 110 includes a system-on-chip that needs to be verified, and the functions of the system-on-chip 110 are tested by the simulation environment 120. The system-on-chip to be verified includes a Central Processing Unit (CPU), a plurality of IP core modules (e.g., IP)1，IP2，……，IPn) And a bus, each of the IP core modules IP1，IP2，……，IPnConnected to the bus, respectively, each IP core module IP1，IP2，……，IPnIs a component having a particular function, e.g. IP1Is USB (Universal Serial bus)Using a serial bus) controller, IP2For video decoders, IP3An audio decoder, etc. It should be understood that each of the IP core modules is not limited to the above-mentioned exemplary components, but may also be components with other specific functions, which are well known to those skilled in the art and will not be described herein. The system-on-chip to be verified may comprise one or more central processing units, e.g. CPUs0，CPU1，……，CPUkEach of said central processing units CPU0，CPU1，……，CPUkIs connected to the bus. The simulation environment 120 includes a software test case, a universal verification methodology test case (UVM case), and a bus function model unit (BFM)0，BFM1，……，BFMk) The software test case is a software code (C program) written by using C language, and the universal verification methodology test case is a test code written by using the universal verification methodology. The bus function model unit BFM0，BFM1，……，BFMkBinding respectively to corresponding central processing unit CPU0，CPU1，……，CPUkThe same interface connected to the bus. The software test case is connected with the bus function model unit through a Direct Programming Interface (DPI). The universal verification methodology test case is connected with the bus function model unit.
In one embodiment, the verification platform 100 further comprises a first selection switch 130, the central processor unit CPU0，CPU1，……，CPUkEach with a respective one of said bus function model units BFM0，BFM1，……，BFMkSelectively connected or bound to the same bus interface of the bus by the first selection switch 130.
In an embodiment, the verification platform 100 further comprises a second selection switch 140, and the Direct Programming Interface (DPI) and the universal verification methodology test case are respectively connected to the corresponding bus function model units through the second selection switch 140.
In one embodiment, the bus functionality model unit connects the bus through a validation ip (vip) module (not shown). Typically, the interfaces of the central processor units conform to a standard Protocol, such as Advanced Microcontroller Bus Architecture (AMBA) Protocol or Open Core Protocol (OCP). The VIP module follows these standard protocols strictly and has been verified. Therefore, the VIP is adopted as the interface in the bus function model, the development time of a simulation verification environment can be shortened, and meanwhile, the correctness and completeness of a bus interface protocol can be verified.
With continued reference to FIG. 2, the central processing unit CPU0，CPU1，……，CPUkBus function model unit BFM0，BFM1，……，BFMkAnd general validation methodology test examples were used as test blocks 0 through k. Wherein the universal verification methodology test case passes through the bus function model unit BFM0，BFM1，……，BFMkThe test is realized, and the software test example passes through the central processing unit CPU0，CPU1，……，CPUkImplementing a test or passing through the bus function model unit BFM via a direct programming interface DPI0，BFM1，……，BFMkThe test is realized, that is, the present embodiment includes three test paths, a UVM use case path, a DPI path, and a CPU path. In the embodiment, the method is very useful in complex SoC verification, and any complex scene can be constructed according to the test requirements, for example, extreme and boundary verification scenes are constructed for verification.
Another embodiment of the present application further discloses a verification method for a system-on-chip, and fig. 3 shows a flowchart of the verification method for the system-on-chip in an embodiment of the present application. The method comprises the following steps:
step S301, building a simulation verification environment of the system level chip;
step S303, a bus function model unit is established, and the bus function model unit is respectively bound to the same interface connected with the bus by the central processing unit;
step S305, creating a universal verification methodology test case, and executing the universal verification methodology test case through the bus function model unit to realize the test of the system-on-chip;
step S307, a plurality of software test cases are created;
step S309, compiling the plurality of software test cases, and executing the compiled plurality of software test cases by the central processing unit to implement the test of the system on chip.
In this implementation, as shown in FIG. 2, the system-on-chip includes one or more CPU units (CPU)0，CPU1，……，CPUkA plurality of IP core modules IP1，IP2，……，IPnAnd each IP core module is respectively connected to the bus, and the central processing unit is connected to the bus. Creating one or more bus function model units BFM0，BFM1，……，BFMkOne or more bus function model units BFM0，BFM1，……，BFMkAre respectively bound to a central processing unit CPU0，CPU1，……，CPUkThe universal verification methodology test case is connected to the bus through the bus function model unit and tests, the test mode can realize random test, and the test coverage rate is improved.
In an embodiment, before the step S303 of binding the bus function model unit to the same interface of the central processing unit connected to the bus, the method further includes: the connection between the central processing unit and the bus is disabled (disable), so that the connection between the central processing unit and the bus does not work when the universal verification methodology test case is tested by the bus function model unit. It should be noted that, in the present embodiment, a plurality of central processing units CPU0，CPU1，……，CPUkIndependent of each other, i.e. part of the CPU units can be enabled to be connected with the bus for executing software test cases, and part of the CPU units can be disabled to be connected with the busFor binding the bus functionality model.
In an embodiment, the number of the universal verification methodology test cases implementing the system on chip tests is greater than the number of the central processor unit implementing the system on chip tests, i.e. a majority (e.g. greater than 80%) of the tests are implemented by the UVM case path and a minority (e.g. less than 20%) of the tests are implemented by the CPU path.
In an embodiment, before step S309 of compiling the plurality of software test cases and executing the compiled plurality of software test cases by the central processing unit to implement the test of the system on chip, the method further includes: selecting, by the bus functional model unit, a Direct Programming Interface (DPI) to execute a portion of the plurality of software test cases; compiling the rest of the plurality of software test cases, and executing the compiled plurality of software test cases by the central processing unit. Wherein a majority (e.g., more than 80%) of the plurality of software test cases are executed by the bus functional model unit selecting a direct programming interface, and a minority (e.g., less than 20%) of the plurality of software test cases are executed by the central processing unit. That is, before the CPU path is implemented, the test may be implemented by the DPI path, and most of the test may be implemented by the DPI path while a small part of the test is implemented by the CPU path.
In an embodiment, the direct programming interface is connected with the bus function model while the bus function model unit executes the universal verification methodology test case to realize the test of the system-on-chip, so that the bus function model unit selects the direct programming interface to execute a part of the plurality of software test cases, that is, a part of a DPI can be continuously realized in a simulation environment while the test is carried out through a UVM case access.
In an embodiment, the bus function model unit selects a direct programming interface to execute the software test case to realize the test of the system-on-chip, and the software test case is compiled and loaded to execute the compiled software test case through the central processing unit, that is, while the UVM case path is used for testing or the BFM selected DPI path is used for testing, the CPU path can be continuously realized in a simulation environment.
In this embodiment, most (for example, more than 90%) of the functions may be tested by the universal verification methodology example unit through the bus function model unit, a few (for example, less than 10%) of the functions that cannot be realized by the universal verification methodology are selected to create a software test case, the software test case is compiled, and the compiled software test case is loaded into the central processing unit and tested by the central processing unit. The embodiment can ensure the coverage rate of verification, reduce the complexity of verification and shorten the verification period. In addition, before the CPU channel is realized, a software test case of C language can be created according to the requirement, and the test is carried out through a bus function model through a direct programming interface.
It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.
All documents mentioned in this specification are to be considered as being incorporated in their entirety into the disclosure of the present application so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.
In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Claims (10)
1. A verification platform for a system-on-a-chip, comprising:
at least one test module, each test module comprising a central processor unit, a bus function model unit and a universal verification methodology test case, the central processor unit being connected to a bus, the bus function model unit being bound to the same interface where the central processor unit is connected to the bus;
the universal verification methodology test case realizes the test through the bus function model unit, and the software test case realizes the test through the central processing unit or realizes the test through the bus function model unit through a direct programming interface.
2. The system-on-chip verification platform of claim 1, further comprising a first selection switch, wherein the central processor unit and the bus function model unit are respectively connected or bound to a same bus interface of the bus through the first selection switch.
3. The system-on-chip verification platform of claim 1, further comprising a second selection switch through which the direct programming interface and the universal verification methodology test case are respectively connected to the bus function model unit.
4. The system-on-chip verification platform according to claim 1, wherein the system-on-chip comprises one or more central processor units, a plurality of IP core modules and a bus, each of the IP core modules is connected to the bus respectively, and the central processor units are connected to the bus.
5. A method for verifying a system-on-a-chip, comprising:
building a simulation verification environment of the system level chip;
creating a bus function model unit, and binding the bus function model unit to the same interface connected with a bus by a central processing unit;
creating a universal verification methodology test case, and executing the universal verification methodology test case through the bus function model unit to realize the test of the system-on-chip;
creating a plurality of software test cases;
compiling the plurality of software test cases, and executing the compiled plurality of software test cases by the central processing unit to realize the test of the system-on-chip.
6. The method for verifying system-on-chip as claimed in claim 5, wherein the step of binding the bus function model unit to the same interface of the CPU and the bus is preceded by the step of: the connection of the central processor unit to the bus is disabled.
7. The method for verifying the system-on-chip as recited in claim 5, wherein before the step of compiling the plurality of software test cases and executing the compiled plurality of software test cases by the central processing unit to realize the test of the system-on-chip, the method further comprises: selecting, by the bus functional model unit, a direct programming interface to execute a portion of the plurality of software test cases; compiling the rest of the plurality of software test cases, and executing the compiled plurality of software test cases by the central processing unit.
8. The method of claim 7, wherein the universal verification methodology test case is executed by the bus function model unit to implement the test of the system-on-chip, and the direct programming interface is connected to the bus function model to select the direct programming interface to execute a part of the plurality of software test cases by the bus function model unit.
9. The method of claim 7, wherein the compiled software test case is compiled and loaded to be executed by the CPU while the direct programming interface is selected to execute the software test case to realize the test of the SOC through the bus function model unit.
10. The method of claim 5, wherein the number of the universal verification methodology test cases implementing the system-on-chip tests is greater than the number of the central processing units implementing the system-on-chip tests.
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| CN115841089A (en) * | 2023-02-27 | 2023-03-24 | 合肥六角形半导体有限公司 | System-on-chip verification platform and verification method based on UVM |
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| CN113868987A (en) * | 2020-06-30 | 2021-12-31 | 澜至电子科技（成都）有限公司 | System-level chip verification platform and verification method thereof |
| US11630757B1 (en) * | 2022-02-02 | 2023-04-18 | Snabb IP LLC | System and method for developing, testing and debugging software for microcontrollers |
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| US20210406442A1 (en) | 2021-12-30 |
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