CN109684672A - A kind of SOC chip whole-system verification system and method - Google Patents
A kind of SOC chip whole-system verification system and method Download PDFInfo
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- CN109684672A CN109684672A CN201811458436.XA CN201811458436A CN109684672A CN 109684672 A CN109684672 A CN 109684672A CN 201811458436 A CN201811458436 A CN 201811458436A CN 109684672 A CN109684672 A CN 109684672A
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- G06F30/36—Circuit design at the analogue level
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Abstract
The present invention discloses a kind of SOC chip whole-system verification system and method, which includes emulation platform and SOC chip；Chip includes CPU, debugging interface, design under test, excitation transmission interface；Emulation platform includes: control CPU model, is connected by debugging interface with design under test according to interface protocol；It receives the indication signal that verifying starts and controls CPU and enter debugging mode, receive the indication signal that verifying terminates and control CPU and exit debugging mode, CPU is under debugging mode according to the instruction action of control CPU model；Transmission pattern is motivated, is connected by excitation transmission interface with design under test according to interface protocol, is sent for generating excited data to design under test, and acquire or receive the response data of design under test；Interpretation of result model is analyzed and is judged for the response data to authentication module, and exports verification result, exports the indication signal that verifying terminates according to verification result.The program solves the problems, such as that code maintenance very complicated causes verification efficiency low, and simplified code is safeguarded and improves verification efficiency.
Description
Technical field
The present invention relates to IC design technical field, especially a kind of SOC (System On Chip, system on chip)
Chip system level verification system and method.
Background technique
With the development of IC industry, the SOC chip showed also becomes increasingly complex, on the whole for verifying
It is required that also higher and higher, in the development cycle of chip design, the working time of verifying accounts for about the 80% of whole cycle, so
The research that verifying working efficiency how is improved under such overall background is meaningful.
The driver based on C language is finished writing for the verifying needs of SOC at present, compiles out by suitable compiler
Driving instruction program is finally write in memory in emulation platform and goes to take out instruction for CPU and execute, while verifying emulation platform
It needs to start control excitation to send, program compiled in advance can not do interaction, the thought of randomness verifying with emulation platform
It can not be applied to emulation well.
Referring to Fig. 1, existing conventional SOC verifying means are in C language environment by preparatory compiled C code (C language
Speech driver) come drive CPU carry out behavior control, cooperate simulated environment excitation generate and send component it is imitative to realize
Very；According to the behavior of CPU in C language driver control SOC chip compiled in advance, and then realize to chip correlation function
Configuration, emulation platform excitation, which sends component and applies relevant pumping signal, realizes that SOC chip is system-level to SOC chip design
Verifying, the exploitation compiling of driving and simulated environment are two sets of systems completely disengaged.Personnel are verified when being emulated can not spirit
Scheduling CPU living, the behavior of CPU are controlled by the driver compiled in advance completely, can not be formed with simulated environment very friendly
Interaction, modification verifying scene verifying personnel need to modify the driver of C code and the Systemverilog language of simulated environment
The component of speech, two sets of Validation Codes of maintenance undoubtedly increase work for the verifying personnel that validation task becomes increasingly complex
Amount, and then cause working efficiency not high.
Summary of the invention
The present invention provides a kind of SOC chip whole-system verification method and system, surveys in the prior art in emulation for overcoming
To the flexibility deficiency of the CPU control defects such as cause verification efficiency low during examination, improves and CPU is controlled during emulation testing
Flexibility, the maintenance of simplified code, improve verification efficiency.
To achieve the above object, the present invention proposes a kind of SOC chip whole-system verification system, including emulation platform and SOC
Chip；
The SOC chip includes CPU, the debugging interface being connected with the CPU, design under test and the mould to be verified
The connected excitation transmission interface of block；
The emulation platform includes:
CPU model is controlled, is connected by the debugging interface with the design under test according to interface protocol；It is opened in verifying
The indication signal that verifying starts is received when the beginning and controls CPU and enters debugging mode, and the finger that verifying terminates is received at the end of verifying
Show signal and control CPU and exit debugging mode, the CPU is under debugging mode according to the instruction action of the control CPU model；
Transmission pattern is motivated, is connected by the excitation transmission interface with the design under test according to interface protocol, is used
It is sent in generating excited data to design under test, and acquires or receive the response data of the design under test；
Interpretation of result model is analyzed and is judged for the response data to the authentication module, and exports verifying knot
Fruit, and the indication signal that verifying terminates is exported according to verification result.
To achieve the above object, the present invention also provides a kind of SOC chip whole-system verification emulation platforms, including above-mentioned SOC
Emulation platform in chip system level verification system.
To achieve the above object, the present invention also provides a kind of SOC chip whole-system verification methods, which is characterized in that described
SOC chip includes CPU, the debugging interface being connected with the CPU, design under test, the excitation being connected with the design under test
Transmission interface；The following steps are included:
Simultaneously composing software program is write in emulation platform；
Emulation platform generates the indication signal that verifying starts, and is exported by debugging interface and the CPU for controlling SOC chip enters
Debugging mode；
According to the correlation function of operating mode control CPU configuration design under test required for verifying scene；
It is generated according to the configuration of function and sends random excited data to excitation transmission interface；
It receives or acquires the response data of design under test and judge whether time-out；
Terminate to verify and report an error in response data time-out, whether just to check response data when response data has not timed out
Really；
Terminate to verify and report an error in response data mistake, judges whether that there are also other excitation numbers when response data is correct
According to；
Terminate to verify in other no excited datas, be returned in also other excited datas according to needed for verifying scene
The step of correlation function for the operating mode control CPU configuration design under test wanted.
SOC chip whole-system verification system and method provided by the invention, by SOC chip CPU driver fusion of platforms
It in emulation platform, is unified in same compiler language environment, using unified verification platform, is controlled completely using verification environment
CPU behavior processed and driving excitation, the method for simplifying the work of maintenance code, while randomness being made full use of to verify participate in
To the drive control of cpu, can be very good to interact with emulation platform, make to verify it is more flexible and more efficiently, convenient for dimension
Shield and extension accelerate the fast of verifying work so as to allow verifying personnel to focus more on the exploitation of scene and the covering of function
Speed convergence, can promote the whole work efficiency of verifying personnel.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
The structure shown according to these attached drawings obtains other attached drawings.
Fig. 1 is to realize that SOC chip emulates schematic diagram in the prior art；
Fig. 2 is the block schematic illustration for the SOC chip whole-system verification system that the embodiment of the present invention one provides；
Fig. 3 is the block schematic illustration of SOC chip whole-system verification system provided by Embodiment 2 of the present invention
Fig. 4 is the flow diagram of SOC chip whole-system verification method provided in an embodiment of the present invention.
The embodiments will be further described with reference to the accompanying drawings for the realization, the function and the advantages of the object of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiment is only a part of the embodiments of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts it is all its
His embodiment, shall fall within the protection scope of the present invention.
It is to be appreciated that the directional instruction (such as up, down, left, right, before and after ...) of institute is only used in the embodiment of the present invention
In explaining in relative positional relationship, the motion conditions etc. under a certain particular pose (as shown in the picture) between each component, if should
When particular pose changes, then directionality instruction also correspondingly changes correspondingly.
In addition, the description for being such as related to " first ", " second " in the present invention is used for description purposes only, and should not be understood as
Its relative importance of indication or suggestion or the quantity for implicitly indicating indicated technical characteristic.Define as a result, " first ",
The feature of " second " can explicitly or implicitly include at least one of the features.In the description of the present invention, " multiple " contain
Justice is at least two, such as two, three etc., unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " connection ", " fixation " etc. shall be understood in a broad sense,
For example, " fixation " may be a fixed connection, it may be a detachable connection, or integral；It can be mechanical connection, be also possible to
Electrical connection can also be physical connection or wireless communication connection；It can be directly connected, the indirect phase of intermediary can also be passed through
Even, the connection inside two elements or the interaction relationship of two elements be can be, unless otherwise restricted clearly.For this
For the those of ordinary skill in field, the specific meanings of the above terms in the present invention can be understood according to specific conditions.
It in addition, the technical solution between each embodiment of the present invention can be combined with each other, but must be general with this field
Based on logical technical staff can be realized, it will be understood that when the combination of technical solution appearance is conflicting or cannot achieve this
The combination of technical solution is not present, also not the present invention claims protection scope within.
The present invention proposes a kind of SOC chip whole-system verification system.
Embodiment one
Referring to figure 2., the present invention provides a kind of SOC chip whole-system verification system, including SOC chip 1 and emulation platform
2；
The SOC chip 1 includes CPU11, the debugging interface 14 being connected with the CPU11, design under test 12, other set
The excitation transmission interface 15 that meter logic 13 is connected with the design under test 12；
The emulation platform 2 includes control CPU model 21, excitation transmission pattern 22 and interpretation of result model 23；Wherein:
Control CPU model 21 is connected by the debugging interface 14 with the design under test 12 according to interface protocol；?
The indication signal that verifying starts is received when verifying starts and controls CPU11 and enters debugging mode, and verifying is received at the end of verifying
The indication signal of end simultaneously controls CPU11 and exits debugging mode, and the CPU11 is under debugging mode according to the control CPU mould
The instruction action of type 21；
Preferably, the control CPU model is built based on UVM verification methodology；The Working mould needed according to verifying scene
Formula control CPU configures the correlation function of design under test, is scheduled to peripheral equipment (other design logics 13).
Transmission pattern 22 is motivated to pass through the excitation transmission interface 15 and 12 phase of design under test according to interface protocol
Even, it is sent for generating excited data to design under test 12, and acquires or receive the response data of the design under test 12；
Preferably, the excitation transmission pattern is built based on UVM verification methodology, generates excited data according to operating mode
And it is sent to the excitation transmission interface 15.
Interpretation of result model 23 is analyzed and is judged for the response data to the authentication module 12, and exports and test
Card is as a result, and export the indication signal that verifying terminates according to verification result.
It is built based on UVM verification methodology, (automatic comparison ends automatically the main function of realizing verification environment automation
Emulation).The interpretation of result model is in the response data feedback time time-out for design under test occur or does not respond to, number of responses
When at least one of being sent situation according to mistake and excited data, the equal indication signals that terminates of output verifying.
Design under test 12 of the present invention is controlled the movement of each internal part by CPU, whole to treat in simulated environment
Authentication module is flexibly controlled and cooperates excitation to achieve the purpose that the certain functions of verifying, within the period of chip development, is visited
The effective method of rope improves verification efficiency, can be carried out more to cpu in simulated environment using the debug interface of cpu
It flexibly and effectively controls, in conjunction with the excitation of simulated environment, makes full use of the distinctive randomness of systemverilog language former
Reason can promote the whole work efficiency of verifying and the maintenance of simplified code, and then improve verification efficiency.
Preferably, emulation platform 1 passes through multiple interface (interface defined in systemverilog language, connection
Emulation platform and design to be measured) it is connected to excitation transmission interface 15 and debugging interface 14 in SOC chip 1, utilize UVM method
The eXecute UML code write control CPU model 21 and motivate transmission pattern 22 is learned, excitation transmission interface 15 includes but unlimited
In I2C, the interfaces such as SPI, UART；Debugging interface 14 includes but is not limited to jtag, the interfaces such as Serial wire.Debugging interface 14,
Excitation transmission interface 15 is the bridge for connecting emulation platform 2 and SOC chip to be measured 1, is achieved in that and uses
The method of interface in systemverilog.
Preferably, the control CPU model 21 and excitation transmission pattern 22 are internally provided with circulative metabolism, in verification process
In to any function in design under test 12 according to control CPU model 21 in configuration excitation transmission pattern 22 in generate it is more
Secondary arbitrary excitation Data duplication verifies the function.
The present invention becomes increasingly complex for the exploitation of current SOC chip, and verifying complexity is also further increasing, and explores effective
Method and scheme promote the efficiency of verifying, more flexible simulated environment exploitation can be provided for verifying personnel and more increase
The covering of the verifying scene of effect, be it is a kind of combine CPU control, emulation platform control, verification method modern integrated circuits survey
Examination technology.
The present invention is mainly by design (DUT, i.e. design under test 12) to be measured, and debugging interface 14, what conventional excitation generated tests
A kind of novel verification method that environment is constituted is demonstrate,proved, can freely control CPU11's in each node of emulation in conjunction with emulation eda tool
Various actions manage the behavior of design to be measured using very easily control cpu under specific function scene, in conjunction with verifying ring
The activation sequence in border is input to design to be measured, to require to fill to whether design to be measured under special scenes meets design specification
Divide verifying.Simultaneously because control CPU be to be realized under verification environment, can in conjunction with randomness verifying characteristic allow chip checking more
Add stalwartness, and the interactivity that CPU control and excitation are sent may be implemented.
Embodiment two
Referring to figure 3., for implement the invention be applied to I2C interface application:
Verification environment specifically includes that
1, it is mainly to pass through I2c_ according to the interface protocol of I2C that excitation, which generates and send component (excitation transmission pattern 22),
Interface is connected on the corresponding pin of SOC design to be measured (SOC chip 1), while can be sampled by the component to be measured
The response or returned data of design.
2, it controls cpu package (control CPU model 21) and mainly passes through jtag_ according to the interface protocol of jtag
Interface is connected on the corresponding supervisor of SOC design to be measured, allows CPU to enter debugging mould by accessing the register of cpu
Formula, CPU enters halt (pause) state under this mode, and the behavior of CPU is taken over by jtag completely.
3, other assemblies (interpretation of result model 23) are mainly to make automatic comparison and judgement to emulation in verification environment, can
Terminated with the emulation for controlling whole.
SOC design to be measured specifically includes that CPU, I2C controller, other logics；CPU mainly does various complexity works in chip
The scheduling of work parses when I2C controller is configured to from the operating mode of equipment and responds corresponding order, is configured to main equipment
The visit order from equipment external to chip is initiated when operating mode.Other logics refer to bus and the memory deposited in the chips
Equal components.
CPU component is controlled, mainly the CPU of design to be measured is flexibly controlled in emulation platform, can emulated
CPU is flexibly controlled in environment executes movement, is the sharpest edges of the relatively current emulation technology of the present invention.Excitation generates and hair
Component is sent, mainly design to be measured is applied in emulation platform and is motivated, design work to be measured is observed and whether response is normal, apply
It can be at any time by the behavior of control CPU component controls CPU during adding excitation.It controls CPU component and excitation generates and hair
Send the interaction mechanism between component: in emulation platform, control CPU component and excitation generation transmission component are can to interact with each other
, the random data that excitation is randomly generated can be controlled by controlling certain configurations of CPU component, it can also be by motivating random produce
Raw certain values come to control CPU component carry out certain behaviour control；Motivate send during simulated environment can be with
CPU is controlled at any time, carries out more flexible verifying so as to the processing to some chip abnormal conditions.
Embodiment three
The embodiment of the present invention also provides a kind of SOC chip whole-system verification emulation platform, the SOC core including any embodiment
Emulation platform in piece whole-system verification system.
Example IV
Referring to figure 4., the embodiment of the present invention provides SOC chip whole-system verification method corresponding with embodiment one, including
Following steps:
S1, simulation run start, and simultaneously composing software program is write in emulation platform；Use the common emulation tool of chip
If (VCS, IRUN) carrys out compiled code, emulation platform and SOC design to be measured are compiled；Compiled code is run, simulation work is utilized
To start emulation；
S2, control CPU enter debugging mode, and emulation platform generates the indication signal that verifying starts, defeated by debugging interface
Out and controls the CPU of SOC chip and enter debugging mode；
CPU can load instruction in the power-up state of default to run, and come due to us and without using the instruction that compiling comes out
CPU is controlled, so we, which need to control CPU by debugging interface using the control cpu package in simulated environment, enters debugging
Mode, so that our CPU can generate corresponding actions according to the behavior that our simulated environment provide.Using being controlled in simulated environment
Cpu package is realized；
S3 configures design correlation function to be measured according to verifying scenery control CPU: according to Working mould required for verifying scene
Formula controls the correlation function of CPU configuration design under test；
The operating mode scheduling of design to be measured needs CPU to go to control and dispatch, we need to allow design to be measured in emulation
The operating mode of scene needs is verified into us, cooperation excitation is to verify whether the function meets design objective.Utilize emulation
Cpu package is controlled in environment to realize；
S4, excitation generate simultaneously send: according to the configuration of function generate and send random excited data to motivate transmission connect
Mouthful；For a certain function of repeated authentication, it is multiple to can control a certain functional configuration that CPU is design under test, more for generating
A excited data that same function is verified；
According to the random data to generate excitation of belt restraining in simulated environment, according to correspondence inside driving (driver)
The timing requirements of interface are by motivating transmission interface to send data on the interface of design to be measured.It is produced using being motivated in verification environment
Hair tonic sending component controls.
Other excitations are sent: generally requiring multiple arbitrary excitation to some function more sufficiently to verify the function in simulations
Can, so needing circulative metabolism.Component is generated and sent using excitation in simulated environment to realize.
Design time-out to be measured: S5 receives or acquires the response data of design under test and judge whether time-out；
Timeout mechanism is set inside verification environment, different design, which closes expected or other reasons, causes design to be measured not have
Response, simulation run time-out simultaneously report an error.The design to be measured of SOC chip is monitored using other assemblies in verification environment.
S6 terminates to verify and report an error in response data time-out, whether checks response data when response data has not timed out
Correctly；
S7, emulation terminate and report an error: terminating to verify and report an error in response data mistake, judge when response data is correct
Whether there are also other excited datas；
When occurring manifest error in simulations, can quote corresponding error this when is which type of, is terminated after allowing
Emulation carries out subsequent debugging work.It is realized using other assemblies in simulated environment.
S8, emulation terminate: terminating to verify in other no excited datas, return to S3 in also other excited datas.
It emulates all excitations to be sent, normal termination emulation.It is realized using other assemblies in simulated environment.
Novel SOC verification method provided by the invention, can carry out SOC's completely without software translating C code
Simulation work for improving the code maintenance of verifying personnel and developing by significance, while also improving whole verifying effect
Rate.
The above description is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all at this
Under the inventive concept of invention, using equivalent structure transformation made by description of the invention and accompanying drawing content, or directly/use indirectly
It is included in other related technical areas in scope of patent protection of the invention.
Claims (10)
1. a kind of SOC chip whole-system verification system, which is characterized in that including emulation platform and SOC chip；
The SOC chip includes CPU, the debugging interface being connected with the CPU, design under test and the design under test phase
Excitation transmission interface even；
The emulation platform includes:
CPU model is controlled, is connected by the debugging interface with the design under test according to interface protocol；When verifying beginning
It receives the indication signal that verifying starts and controls CPU and enter debugging mode, the instruction letter that verifying terminates is received at the end of verifying
Number and control CPU and exit debugging mode, the CPU is under debugging mode according to the instruction action of the control CPU model；
Transmission pattern is motivated, is connected by the excitation transmission interface with the design under test according to interface protocol, for producing
Raw excited data is sent to design under test, and acquires or receive the response data of the design under test；
Interpretation of result model is analyzed and is judged for the response data to the authentication module, and exports verification result, and
The indication signal that verifying terminates is exported according to verification result.
2. SOC chip whole-system verification system as described in claim 1, which is characterized in that the control CPU model is based on
UVM verification methodology is built；The operating mode control CPU needed according to verifying scene carries out the correlation function of design under test
Configuration, is scheduled peripheral equipment.
3. SOC chip whole-system verification system as claimed in claim 2, which is characterized in that the excitation transmission pattern is based on
UVM verification methodology is built, and is generated excited data according to operating mode and is sent to the excitation transmission interface.
4. SOC chip whole-system verification system as claimed in claim 3, which is characterized in that the control CPU model and excitation
Transmission pattern is internally provided with circulative metabolism, to any function in design under test according to control CPU mould in verification process
Configuration in type generates multiple arbitrary excitation Data duplication in excitation transmission pattern and verifies the function.
5. SOC chip whole-system verification system as described in claim 1, which is characterized in that the interpretation of result model is going out
The response data feedback time time-out of existing design under test does not respond to, during response data mistake and excited data are sent
When at least one situation, the indication signal terminated is verified in output.
6. SOC chip whole-system verification system as claimed in claim 5, which is characterized in that the interpretation of result model by
In design under test response data mistake and send verifying terminate indication signal terminate verifying after, start error routine to sound
It answers the type of error in data to be inquired and exports debugging result.
7. SOC chip whole-system verification system as described in any one of claims 1 to 6, which is characterized in that the debugging interface
The method for being all made of interface in systemverilog with excitation interface realizes the connection of emulation platform and design under test.
8. a kind of SOC chip whole-system verification emulation platform, which is characterized in that including any one of claim 1~7 SOC
Emulation platform in chip system level verification system.
9. a kind of SOC chip whole-system verification method, which is characterized in that the SOC chip includes CPU, is connected with the CPU
Debugging interface, design under test, the excitation transmission interface being connected with the design under test；The following steps are included:
Step 1, emulation platform and SOC design to be measured are compiled using chip emulation tool；
Step 2, entire simulated program is started according to the setting of emulation platform, is exported by debugging interface and controls SOC chip
CPU enters debugging mode；
Step 3, the correlation function of the operating mode control CPU configuration design under test according to required for verifying scene；
Step 4, it is generated according to the configuration of function and sends random excited data to excitation transmission interface；
Step 5, it receives or acquires the response data of design under test and judge whether time-out；
Step 6, terminate to verify and report an error in response data time-out, whether just to check response data when response data has not timed out
Really；
Step 7, terminate to verify and report an error in response data mistake, judge whether that there are also other excitations when response data is correct
Data；
Step 8, terminate to verify in other no excited datas, return to step 3 in also other excited datas.
10. SOC chip whole-system verification method as claimed in claim 9, which is characterized in that in the configuration according to function
It generates and sends random excited data into excitation transmission interface step, excited data includes multiple testing same function
The excited data of card.
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