CN111858207B - SoC chip verification test system and method - Google Patents
SoC chip verification test system and method Download PDFInfo
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Abstract
The application discloses a system and a method for verifying and testing a SoC chip. The system disclosed in the present application comprises: the control end is used for sending the same control instruction to the at least two verification test platforms so that the at least two verification test platforms verify or test the same function point of the SoC chip to obtain at least two operation results; the control end is also used for receiving and comparing at least two operation results to obtain a comparison result, recording the comparison result and the at least two operation results to the recursive table of the function point, and storing the recursive table to the database. The method and the device can facilitate technicians to call the verification test data for analysis, provide reliable data support for the design and modification perfection of the SoC chip, avoid the operation result recording error caused by the instability of a certain verification test platform, improve the stability of the system and ensure the correctness of the verification result and the test result.
Description
Technical Field
The present disclosure relates to the field of integrated circuit testing technologies, and in particular, to a system and a method for SoC chip verification testing.
Background
SoC (System on Chip) is an integrated circuit with a dedicated target. After the design of each function point in the SoC is completed, the correctness of the function points needs to be verified, and if the correctness of the function point passes the verification, the stability of the function point under various scenes is tested.
Usually, a verification test platform can be implemented by using a hardware circuit design, and the verification test platform operates each function point of the SoC chip one by one under the control of the host computer and feeds back an operation result to the host computer. However, the hardware circuit may have sampling errors and other abnormal situations in some special environments, such as: high temperature environment, low temperature environment, extreme operating frequency, etc. Therefore, the stability of the existing verification test platform is insufficient, and problems may occur in the verification result and the test result.
Therefore, how to guarantee the correctness of the verification result and the test result is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of this, an object of the present application is to provide a system and a method for SoC chip verification test to ensure correctness of the verification result and the test result. The specific scheme is as follows:
in a first aspect, the present application provides a SoC chip verification test system, including: control end to and with a plurality of verification test platform that the control end is connected, wherein:
the control end is used for sending the same control instruction to at least two verification test platforms so that the at least two verification test platforms perform corresponding operation according to the control instruction to obtain at least two operation results; the control instruction is an instruction for controlling the verification test platform to verify or test any functional point of the SoC chip;
the control end is further configured to receive the at least two operation results returned by the at least two verification test platforms, compare the at least two operation results to obtain a comparison result, record the comparison result and the at least two operation results to the recursive table of the function point, and store the recursive table to the database.
Preferably, the database records a to-be-verified test function point of the SoC chip, and a test case and an inspection item corresponding to the to-be-verified test function point, and the control instruction is generated based on the to-be-verified test function point and the inspection item.
Preferably, the control terminal is further configured to calculate a verification test coverage and a verification test defect rate of the SoC chip by using the data in the database, and visually display the data in the database, the verification test coverage and the verification test defect rate.
Preferably, the control end and the plurality of verification test platforms are connected in a star topology.
Preferably, the control end and any verification test platform communicate by using Ethernet, Can bus or Uart.
Preferably, the control terminal is connected to at least one of the plurality of verification test platforms, and the at least one verification test platform is connected to other verification test platforms of the plurality of verification test platforms.
Preferably, the control end and the at least one verification test platform communicate by using an ethernet, a Can bus or a Uart, and the at least one verification test platform and other verification test platforms in the multiple verification test platforms communicate by using an ethernet, a Can bus or a Uart.
Preferably, the control end is further configured to configure routing information to each verification test platform.
Preferably, the control terminal is remotely located from the plurality of verification test platforms.
Preferably, the verification test platform is an FPGA.
In a second aspect, the present application provides a SoC chip verification test method, which is applied to a control end connected with a plurality of verification test platforms, and includes:
sending the same control instruction to at least two verification test platforms to enable the at least two verification test platforms to perform corresponding operation according to the control instruction to obtain at least two operation results; the control instruction is an instruction for controlling the verification test platform to verify or test any functional point of the SoC chip;
receiving the at least two operation results returned by the at least two verification test platforms, comparing the at least two operation results to obtain a comparison result, recording the comparison result and the at least two operation results to the recursive table of the function point, and storing the recursive table to a database.
According to the above scheme, the present application provides an SoC chip verification test system, including: control end to and with a plurality of verification test platform that the control end is connected, wherein: the control end is used for sending the same control instruction to at least two verification test platforms so that the at least two verification test platforms perform corresponding operation according to the control instruction to obtain at least two operation results; the control instruction is an instruction for controlling the verification test platform to verify or test any functional point of the SoC chip; the control end is further configured to receive the at least two operation results returned by the at least two verification test platforms, compare the at least two operation results to obtain a comparison result, record the comparison result and the at least two operation results to the recursive table of the function point, and store the recursive table to the database.
Therefore, the verification test system provided by the application comprises a control end and a plurality of verification test platforms connected with the control end, wherein the control end can send the same control instruction to at least two verification test platforms, so that for the same function point, at least two verification test platforms test or verify the same function point, and at least two operation results can be obtained; therefore, the control end can compare the operation results of different verification test platforms on the same function point, so that a comparison result is obtained, the comparison result and all the operation results are stored in the recursion table of the function point, the recursion table is stored in the database, technical personnel can conveniently call corresponding data from the database for analysis, and reliable data support is provided for the design and modification perfection of the SoC chip. Moreover, the verification test data related to different functional points are recorded in different recursive tables, so that subsequent query and summarization can be facilitated. The control end compares different operation results, so that the error recording of the operation result caused by the instability of a certain verification test platform can be avoided, the stability of the system is improved, the correctness of the verification result and the test result can be ensured, technicians can conveniently find the verification test platform with problems in time, and an effective basis is provided for system maintenance.
Correspondingly, the SoC chip verification test method provided by the application also has the technical effects.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a first SoC chip verification test system disclosed in the present application;
fig. 2 is a schematic diagram of a second SoC chip verification test system disclosed in the present application;
FIG. 3 is a schematic diagram of a third SoC chip verification test system disclosed in the present application;
fig. 4 is a flowchart of a SoC chip verification test method disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, the stability of the existing verification test platform is insufficient, and problems may occur in the verification result and the test result. Therefore, the application provides a verification test scheme for the SoC chip, which can ensure the correctness of the verification result and the test result.
Referring to fig. 1, an embodiment of the present application discloses a first SoC chip verification test system, including: control end to and a plurality of verification test platform of being connected with the control end, wherein: the control end is used for sending the same control instruction to the at least two verification test platforms so that the at least two verification test platforms perform corresponding operation according to the control instruction to obtain at least two operation results; the control instruction is an instruction for controlling the verification test platform to verify or test any functional point of the SoC chip; the control terminal is further used for receiving at least two operation results returned by the at least two verification test platforms, comparing the at least two operation results to obtain a comparison result, recording the comparison result and the at least two operation results to the recursive table of the function point, and storing the recursive table to the database.
The control command may be a command for verifying a certain functional point, or may be a command for testing a certain functional point. For any functional point in the SoC chip, correctness verification is generally performed first, and then stability tests are performed under various special environments. The verification part has a large workload, and because the design function point is an innovative process from scratch, the principle of the verification part is extremely important. The stability test of the functional points is relatively heavy in the actual application scenes of the chip, the workload is relatively less, and each application scene is also relatively easy to design. A verification test platform is a platform that can be used to verify a functional point and that can be used to test a functional point.
In a specific implementation manner, a to-be-verified test function point of the SoC chip, and a test case and an inspection item corresponding to the to-be-verified test function point are recorded in a database in the control terminal, and the control instruction is generated based on the to-be-verified test function point and the inspection item. Technical personnel can record all functional points needing to be verified and tested in the SoC chip in a database in advance, test cases and check items corresponding to the functional points are added at the same time, and verification and testing can be carried out on each functional point one by one in the follow-up verification testing process based on the pre-stored contents. The test function points to be verified are as follows: a functional point of verification and testing is required. For example: the flash memory in the SoC chip needs to be verified and tested, so that the read-write capability of the SoC chip needs to be verified and tested, and whether the SoC chip can normally complete read-write operation in special environments such as high temperature and low temperature is tested. Wherein, reading and writing are check items of the flash memory.
In a specific embodiment, the control terminal is further configured to calculate a verification test coverage and a verification test defect rate of the SoC chip by using data in the database, and visually display the data in the database, the verification test coverage and the verification test defect rate. Verifying test coverage includes: for all functional points needing to be verified and tested in a certain SoC chip, the ratio (namely verification coverage) of the functional points which are already verified to the functional points needing to be verified; the ratio of the functional points that have completed testing to the functional points that need to be tested (i.e., test coverage). Verifying the test defect rate includes: for all functional points needing verification and test in a certain SoC chip, the ratio (verification defect rate) of the error verification result to all verification results; ratio of erroneous test results to all test results (test defect rate). The verification test coverage rate and the verification test defect rate can better help SoC chip designers to plan and arrange work.
Typically, an SoC chip includes one or more processor systems (processors and their peripherals), memory, interconnect bus, high speed interface modules (e.g., gigabit ethernet, RapidIO, PCI-Express, etc.). The current one-time chip-feeding success rate of the SoC chip is only about 35 percent, and the main reason for the repeated chip-feeding of the SoC chip is that the verification test scheme is not accurate enough, and the resources required to be fed by the current verification test SoC chip account for 60 to 80 percent of the whole design resources of the SoC chip. In this regard, the solution provided by the present embodiment may be used to solve this problem.
Therefore, the verification test system disclosed in the embodiment of the application comprises a control end and a plurality of verification test platforms connected with the control end, wherein the control end can send the same control instruction to at least two verification test platforms, so that for the same function point, at least two verification test platforms test or verify the same function point, and at least two operation results can be obtained; therefore, the control end can compare the operation results of different verification test platforms on the same function point, so that a comparison result is obtained, the comparison result and all the operation results are stored in the recursion table of the function point, the recursion table is stored in the database, technical personnel can conveniently call corresponding data from the database for analysis, and reliable data support is provided for the design and modification perfection of the SoC chip. Moreover, the verification test data related to different functional points are recorded in different recursive tables, so that subsequent query and summarization can be facilitated. The control end compares different operation results, so that the error recording of the operation result caused by the instability of a certain verification test platform can be avoided, the stability of the system is improved, the correctness of the verification result and the test result can be ensured, technicians can conveniently find the verification test platform with problems in time, and an effective basis is provided for system maintenance.
Referring to fig. 2, an embodiment of the present application discloses a second SoC chip verification test system, including: control end to and a plurality of verification test platform of being connected with the control end, wherein: the control end is used for sending the same control instruction to the at least two verification test platforms so that the at least two verification test platforms perform corresponding operation according to the control instruction to obtain at least two operation results; the control terminal is further used for receiving at least two operation results returned by the at least two verification test platforms, comparing the at least two operation results to obtain a comparison result, recording the comparison result and the at least two operation results to the recursive table of the function point, and storing the recursive table to the database.
The function IP (Intelligent Property) in FIG. 2 refers to: the module which is defined in advance and verified to be reusable can complete certain functions.
When the control instruction is an instruction for verifying a certain functional point, verifying that an operation result output by the test platform is a verification result; and when the control instruction is an instruction for testing a certain functional point, verifying that the operation result output by the test platform is a test result. If some verification test platforms can perform verification tests on the same function point, it indicates that the verification test platforms are provided with function modules capable of verifying the same function point, and the function modules included in the verification test platforms may be completely the same or partially the same. For example: the verification test platform A comprises: functional module 1, functional module 2, functional module 3, include in the verification test platform B: functional module 2, functional module 3, and functional module 4, then, the verification test platform a and the verification test platform B can perform verification test on the functional points 2 and 3 (assuming that one functional module corresponds to one functional point). Of course, the verification test platform B may be identical to the functional module included in the verification test platform a.
In this embodiment, the control end is connected to the multiple verification test platforms by using a star topology, the control end communicates with any one of the verification test platforms by using an ethernet, a Can bus, or a Uart, and different verification test platforms may be connected or not connected (generally not connected). The communication connection mode between the control terminal and different verification test platforms can be the same or different.
In one embodiment, the control end is located off-site from the plurality of verification test platforms, i.e. the plurality of verification test platforms are located at the same geographical location, and the control end is located at another geographical location, so that the control end and the verification test platforms need to communicate remotely.
Of course, the control end is also used for configuring the routing information to each verification test platform so that the control end can communicate with each verification test platform. Specifically, the control end configures addresses required for communication for each verification test platform, and the addresses can be customized at the control end as long as the control end can be used for distinguishing each verification test platform.
The verification test platform may be an FPGA (Field-Programmable Gate Array). All the verification test platforms in this embodiment may be FPGAs, or some of the verification test platforms may be FPGAs.
It should be noted that, the control end is provided with corresponding management software, and the communication protocol to be used can be customized at the control end. The data sent by the control end comprises the routing information of the source node and the routing information of the destination node, so that after the node receiving the data analyzes the data, if the routing address of the destination node is consistent with the routing information of the node, the node carries out subsequent operation according to the received data. A node refers to a verification test platform in a system.
The star topology structure in the embodiment is relatively simple, the verification test platforms are not required to forward data, and the verification test platforms are mutually independent, so that the test process or the verification process cannot be performed due to the fault of one verification test platform. The embodiment can facilitate technicians to call corresponding data from the database for analysis, thereby providing reliable data support for the design and modification perfection of the SoC chip. Moreover, the verification test data related to different functional points are recorded in different recursive tables, so that subsequent query and summarization can be facilitated. The control end compares different operation results, so that the error recording of the operation result caused by the instability of a certain verification test platform can be avoided, the stability of the system is improved, the correctness of the verification result and the test result can be ensured, technicians can conveniently find the verification test platform with problems in time, and an effective basis is provided for system maintenance.
Referring to fig. 3, an embodiment of the present application discloses a third SoC chip verification test system, including: control end to and a plurality of verification test platform of being connected with the control end, wherein: the control end is used for sending the same control instruction to the at least two verification test platforms so that the at least two verification test platforms perform corresponding operation according to the control instruction to obtain at least two operation results; the control terminal is further used for receiving at least two operation results returned by the at least two verification test platforms, comparing the at least two operation results to obtain a comparison result, recording the comparison result and the at least two operation results to the recursive table of the function point, and storing the recursive table to the database.
In this embodiment, the control terminal is connected to at least one of the plurality of verification test platforms, and the at least one verification test platform is connected to other verification test platforms of the plurality of verification test platforms. Namely: only individual verification test platforms are directly connected with the control end, and other verification test platforms are indirectly connected with the control end. The control end and at least one verification test platform adopt Ethernet, Can bus or Uart to communicate, and the at least one verification test platform and other verification test platforms in the plurality of verification test platforms adopt Ethernet, Can bus or Uart to communicate. Some of different verification test platforms have communication connection, and some of the different verification test platforms have no communication connection. The communication connection mode between the control terminal and each verification test platform and between different verification test platforms can be the same or different.
Referring to fig. 3, the system of fig. 3 is built with a 2D-Mesh topology. When only one or more verification test platforms are directly connected with the controller, the verification test platforms are required to have a data forwarding function. In this way, the network topology structure of the system needs to be determined first, and the routing information of all the verification test platforms in the system is determined according to the network topology structure, so that the control end can communicate with any verification test platform.
In fig. 3, if it is desired to send data from the control terminal to the verification test platform 9 using the XY routing algorithm, there are various available paths. For example: if the path "Y" is taken first (horizontal direction) and the path "X" is taken again (vertical direction), the path is as follows: 1- >2- >3- >6- > 9; or the 'Y' path can be taken first, and then the 'X' path is taken, so that the path is as follows: 1- >4- >7- >8- > 9; the path can also be taken firstly, then the path is taken secondly, then the path is taken thirdly, and then the path is: 1- >2- >5- >8- > 9. The specific path used can be set according to the type and the number of interfaces of the platform, and whether the data on the path is congested.
It should be noted that, the control end is provided with corresponding management software, and the communication protocol to be used can be customized at the control end. The data sent by the control end comprises the routing information of the source node and the routing information of the destination node, so that after each intermediate node on the path analyzes the data, if the routing address of the destination node is found not to be matched with the routing information of the intermediate node, the data can be forwarded to the next node according to the routing address of the destination node until the data reaches the destination node. A node refers to a verification test platform in a system.
In a specific implementation mode, by using a database of a control end, information such as verification test regression, verification test problems, design bugs and the like can be recorded and analyzed. Specifically, the database may include: basic function recursion table, complex function recursion table, and recursion table of coverage and defect rate. The basic function recursion table records some basic function points of the SoC chip to be verified, and specifically records test cases, check items, test scenes, verification results and the like corresponding to the basic function points. The stability of the basic function points to be tested is recorded in the complex function recursion table, and the stability test cases, the check items to be checked for stability, the complex test scenes to be responded, the test results and the like corresponding to the basic function points are recorded specifically. The coverage rate and the defect rate are calculated based on the basic function recursion table and the complex function recursion table in the recursion tables of the coverage rate and the defect rate; specifically, several test cases can be randomly found from the basic function recursion table and the complex function recursion table, then the corresponding function points are tested or verified, and then the coverage rate and the defect rate are calculated.
At the control end, technicians submit corresponding test cases respectively aiming at the verification process and the test process, and a corresponding recursive table is established in a database. Then, when verifying or testing, recording the corresponding result to the recursive table. Therefore, the personnel participating in the test or the verification can clearly see the related progress of the verification or the test process based on the corresponding recursive table in the database, can not be interfered by too many human factors, and can objectively reflect the verification and test conditions of each function point.
Therefore, the system provided by the embodiment can remotely control a plurality of verification test platforms, design more complex application scenes, and better test and verify the stability of the system and the working state under the limit condition. The database in the control end can help technicians to complete related work better and discover SoC chip design defects and system design defects earlier, so that the success rate of chip flow can be improved.
Referring to fig. 4, an embodiment of the present application discloses a SoC chip verification test method, which is applied to a control end connected with a plurality of verification test platforms, and includes:
s401, the same control instruction is sent to at least two verification test platforms, so that the at least two verification test platforms perform corresponding operation according to the control instruction, and at least two operation results are obtained.
The control instruction is an instruction for controlling the verification test platform to verify or test any functional point of the SoC chip.
S402, receiving at least two operation results returned by the at least two verification test platforms, comparing the at least two operation results to obtain a comparison result, recording the comparison result and the at least two operation results to a recursive table of the function point, and storing the recursive table to a database.
It should be noted that the control terminal can simultaneously verify or test different function points of the SoC chip. For example: the control end simultaneously sends a control instruction A and a control instruction B, wherein the control instruction A is sent to the verification test platforms 1, 2 and 3; the control instruction B is sent to the verification test platforms 4, 5, 6, and 7, and then the verification test platforms 1, 2, and 3 and the verification test platforms 4, 5, 6, and 7 execute related operations at the same time, thereby achieving the purpose of verifying or testing two function points at the same time. The control instruction A is used for verifying or testing the functional point A, and the control instruction B is used for verifying or testing the functional point B.
In this embodiment, the control end can send the same control instruction to the at least two verification test platforms, so that for the same function point, the at least two verification test platforms test or verify the same function point, and thus at least two operation results can be obtained; therefore, the control end can compare the operation results of different verification test platforms for the same function point, so as to obtain a comparison result, thereby avoiding the error of the verification test result caused by the fault of a certain verification test platform and ensuring the correctness of the verification test result. The control end stores the comparison result and all operation results to the recursion table of the function point, and stores the recursion table to the database, so that technical personnel can conveniently call corresponding data from the database for analysis, and reliable data support is provided for the design and modification perfection of the SoC chip.
The verification test data related to different functional points are recorded in different recursive tables, so that follow-up query and summarization can be facilitated, the control end compares different operation results, and technicians can find problematic verification test platforms in time conveniently, so that an effective basis is provided for system maintenance.
References in this application to "first," "second," "third," "fourth," etc., if any, are intended to distinguish between similar elements and not necessarily to describe a particular order or sequence. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, or apparatus.
It should be noted that the descriptions in this application referring to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of readable storage medium known in the art.
The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (7)
1. An SoC chip verification test system, comprising: control end to and with a plurality of verification test platform that the control end is connected, wherein:
the control end is used for sending the same control instruction to at least two verification test platforms so that the at least two verification test platforms perform corresponding operation according to the control instruction to obtain at least two operation results; the control instruction is an instruction for controlling the verification test platform to verify or test any functional point of the SoC chip;
the control end is further configured to receive the at least two operation results returned by the at least two verification test platforms, compare the at least two operation results to obtain a comparison result, record the comparison result and the at least two operation results to the recursive table of the function point, and store the recursive table to the database;
the system comprises a database, a test system and a control instruction, wherein the database records a to-be-verified test function point of the SoC chip, and a test case and an inspection item corresponding to the to-be-verified test function point, and the control instruction is generated based on the to-be-verified test function point and the inspection item;
the control terminal is further used for calculating the verification test coverage rate and the verification test defect rate of the SoC chip by using the data in the database, and visually displaying the data in the database, the verification test coverage rate and the verification test defect rate;
and the control end is connected with the plurality of verification test platforms by adopting a star topology structure.
2. The SoC chip verification test system of claim 1, wherein the control end and any one of the verification test platforms use ethernet, Can bus or Uart for communication.
3. The SoC chip validation test system of claim 1, wherein the control terminal is connected to at least one of the plurality of validation test platforms, the at least one validation test platform being connected to other of the plurality of validation test platforms.
4. The SoC chip verification test system of claim 3, wherein the control terminal and the at least one verification test platform communicate using Ethernet, Can bus or Uart, and the at least one verification test platform and other verification test platforms of the plurality of verification test platforms communicate using Ethernet, Can bus or Uart.
5. The SoC chip verification test system of any one of claims 1 to 4, wherein the control side is further configured to configure routing information to each verification test platform.
6. The SoC chip verification test system of any one of claims 1 to 4, wherein the control terminal is remotely located from the plurality of verification test platforms.
7. A SoC chip verification test method is applied to a control end connected with a plurality of verification test platforms, and comprises the following steps:
sending the same control instruction to at least two verification test platforms to enable the at least two verification test platforms to perform corresponding operation according to the control instruction to obtain at least two operation results; the control instruction is an instruction for controlling the verification test platform to verify or test any functional point of the SoC chip;
receiving the at least two operation results returned by the at least two verification test platforms, comparing the at least two operation results to obtain a comparison result, recording the comparison result and the at least two operation results to a recursive table of the function point, and storing the recursive table to a database;
the system comprises a database, a test system and a control instruction, wherein the database records a to-be-verified test function point of the SoC chip, and a test case and an inspection item corresponding to the to-be-verified test function point, and the control instruction is generated based on the to-be-verified test function point and the inspection item;
the control terminal is further used for calculating the verification test coverage rate and the verification test defect rate of the SoC chip by using the data in the database, and visually displaying the data in the database, the verification test coverage rate and the verification test defect rate;
and the control end is connected with the plurality of verification test platforms by adopting a star topology structure.
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Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1916920A (en) * | 2006-09-14 | 2007-02-21 | 华为技术有限公司 | System and method for testing and measuring percentage of coverage of function |
| CN101515301A (en) * | 2008-02-23 | 2009-08-26 | 炬力集成电路设计有限公司 | Method and device for verifying SoC (system on a chip) chips |
| CN106332163A (en) * | 2015-06-30 | 2017-01-11 | 展讯通信（上海）有限公司 | Functional module testing method and system |
| CN107193738A (en) * | 2017-05-19 | 2017-09-22 | 郑州云海信息技术有限公司 | A kind of verification method that dynamic adjustment random constraints are covered based on function point |
| CN107423505A (en) * | 2017-07-21 | 2017-12-01 | 山东华芯半导体有限公司 | A kind of reusable checking system of module level and SoC level and verification method |
| CN108052427A (en) * | 2017-12-21 | 2018-05-18 | 北京遥感设备研究所 | One kind accelerates processing SoC chip automation simulation test method based on image |
| CN108959673A (en) * | 2017-05-27 | 2018-12-07 | 深圳市中兴微电子技术有限公司 | A kind of verification platform and verification method |
| CN109508284A (en) * | 2018-07-02 | 2019-03-22 | 四川斐讯信息技术有限公司 | A kind of system interface test platform and system |
| CN109684672A (en) * | 2018-11-30 | 2019-04-26 | 上海芯钛信息科技有限公司 | A kind of SOC chip whole-system verification system and method |
| CN109726061A (en) * | 2019-01-07 | 2019-05-07 | 上海琪埔维半导体有限公司 | A kind of verification method of SoC chip |
| CN109726507A (en) * | 2019-01-17 | 2019-05-07 | 湖南进芯电子科技有限公司 | A kind of efficiently multi-functional verification platform and method |
| CN109800170A (en) * | 2019-01-25 | 2019-05-24 | 郑州云海信息技术有限公司 | A kind of test method based on API test platform, equipment and readable storage medium storing program for executing |
| CN109920467A (en) * | 2019-02-28 | 2019-06-21 | 无锡中微腾芯电子有限公司 | A method of it is tested for more storage chips |
| CN110634530A (en) * | 2019-09-10 | 2019-12-31 | 珠海博雅科技有限公司 | Chip testing system and method |
| CN111339731A (en) * | 2020-01-21 | 2020-06-26 | 中国人民解放军军事科学院国防科技创新研究院 | FPGA (field programmable Gate array) verification platform and method for SoC (System on chip) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7788057B2 (en) * | 2008-01-23 | 2010-08-31 | International Business Machines Corporation | Test apparatus and methods thereof |
-
2020
- 2020-06-30 CN CN202010616612.9A patent/CN111858207B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1916920A (en) * | 2006-09-14 | 2007-02-21 | 华为技术有限公司 | System and method for testing and measuring percentage of coverage of function |
| CN101515301A (en) * | 2008-02-23 | 2009-08-26 | 炬力集成电路设计有限公司 | Method and device for verifying SoC (system on a chip) chips |
| CN106332163A (en) * | 2015-06-30 | 2017-01-11 | 展讯通信（上海）有限公司 | Functional module testing method and system |
| CN107193738A (en) * | 2017-05-19 | 2017-09-22 | 郑州云海信息技术有限公司 | A kind of verification method that dynamic adjustment random constraints are covered based on function point |
| CN108959673A (en) * | 2017-05-27 | 2018-12-07 | 深圳市中兴微电子技术有限公司 | A kind of verification platform and verification method |
| CN107423505A (en) * | 2017-07-21 | 2017-12-01 | 山东华芯半导体有限公司 | A kind of reusable checking system of module level and SoC level and verification method |
| CN108052427A (en) * | 2017-12-21 | 2018-05-18 | 北京遥感设备研究所 | One kind accelerates processing SoC chip automation simulation test method based on image |
| CN109508284A (en) * | 2018-07-02 | 2019-03-22 | 四川斐讯信息技术有限公司 | A kind of system interface test platform and system |
| CN109684672A (en) * | 2018-11-30 | 2019-04-26 | 上海芯钛信息科技有限公司 | A kind of SOC chip whole-system verification system and method |
| CN109726061A (en) * | 2019-01-07 | 2019-05-07 | 上海琪埔维半导体有限公司 | A kind of verification method of SoC chip |
| CN109726507A (en) * | 2019-01-17 | 2019-05-07 | 湖南进芯电子科技有限公司 | A kind of efficiently multi-functional verification platform and method |
| CN109800170A (en) * | 2019-01-25 | 2019-05-24 | 郑州云海信息技术有限公司 | A kind of test method based on API test platform, equipment and readable storage medium storing program for executing |
| CN109920467A (en) * | 2019-02-28 | 2019-06-21 | 无锡中微腾芯电子有限公司 | A method of it is tested for more storage chips |
| CN110634530A (en) * | 2019-09-10 | 2019-12-31 | 珠海博雅科技有限公司 | Chip testing system and method |
| CN111339731A (en) * | 2020-01-21 | 2020-06-26 | 中国人民解放军军事科学院国防科技创新研究院 | FPGA (field programmable Gate array) verification platform and method for SoC (System on chip) |
Non-Patent Citations (5)
| Title |
|---|
| "FAL-based High Reusability and Automated Verification Platform";Tingrong Zhang等;《Proceedings of the 2nd International Conference on Computer Science and Application Engineering》;20181022;第1-5页 * |
| "SoC验证方法学研究与应用";吴军等;《空间控制技术与应用》;20121031;第27-33页 * |
| "基于51核SoC的功能验证";杜辉;《中国优秀硕士学位论文全文数据库 信息科技辑》;20090115;I135-95 * |
| "基于多平台的计算机软件测试方法分析";易敏捷;《科技传播》;20131031;第202-203页 * |
| "覆盖率驱动的交换芯片验证方法研究";闫爱;《中国优秀硕士学位论文全文数据库 信息科技辑》;20170315;I135-736 * |
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