CN113032195A - Chip simulation verification method, system, equipment and storage medium - Google Patents
Chip simulation verification method, system, equipment and storage medium Download PDFInfo
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- CN113032195A CN113032195A CN202110315045.8A CN202110315045A CN113032195A CN 113032195 A CN113032195 A CN 113032195A CN 202110315045 A CN202110315045 A CN 202110315045A CN 113032195 A CN113032195 A CN 113032195A
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2263—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using neural networks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
Abstract
The invention provides a method, a system, equipment and a storage medium for chip simulation verification, wherein the method comprises the following steps: acquiring a chip verification configuration file, wherein the chip verification configuration file comprises operator parameters and test parameters, the operator parameters comprise configuration parameters of each operator, the test parameters comprise an operation mode, and the operation mode comprises single operator test and/or chip model integral test; generating random excitation data according to the chip verification configuration file; inputting the random excitation data into a corresponding simulation operator or simulation algorithm model, and acquiring a simulation result; generating an input file of an input chip according to the random excitation data and the input data format requirement of the chip; inputting the input file into a chip and acquiring an output result of the chip; and comparing the simulation result with the output result of the chip to obtain a chip verification result. The method is applied to simulation and verification of the neural network model inference chip, and realizes quick functional verification of different neural network models and operators.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a method, a system, a device, and a storage medium for chip simulation verification.
Background
Chip verification is always an industry with the continuous development of chip design, and function verification takes much time in the whole design cycle of a chip. In recent years, along with the improvement of computer computing power, various algorithm models oriented to different scenes are diversified, on one hand, different network models are designed and iterated according to actual industrial demand scenes, on the other hand, the models are converted into computing power supported by hardware, and in the inference stage of the models, trained neural network model algorithms are written on a chip, so that the purposes of real-time inference and low power consumption are achieved, and the method is the core competitiveness of many companies. As a hardware basis of an Artificial Intelligence (AI) technology and a necessary carrier for industry landing, it is becoming more and more important to establish a chip verification architecture for an AI algorithm to shorten a development cycle of a chip.
At present, the mainstream framework of chip Verification is Universal Verification Methodology (UVM), and UVM is a Universal Verification Methodology, provides standardization of a design mode, and provides a base library for a construction platform. The user can directly expand the function according to the requirement to obtain the own verification component, and a complete verification platform is built. But when the specification is carried out, a threshold for entering a door is brought, and a user needs to be familiar with a UVM framework and then build a UVM testing platform according to the requirement. A chip software and hardware simulation environment based on UVM and FPGA (Field Programmable Gate Array) is provided by CN107463473A aiming at the problems that the scene of UVM verification is limited and the speed is low, the chip software and hardware simulation environment based on UVM and FPGA is connected with an FPGA verification platform through an IP standard model, the FPGA is driven to carry out simulation verification, a verification result is sent to the UVM as Field environment configuration, the UVM verification platform is connected with the IP standard model, an algorithm in the IP standard model is called to carry out simulation verification on the FPGA result, and more verification scenes can be obtained. The construction process of the verification environment of the method is complex.
The chip verification language based on C/C + +/system Verilog is a relatively common chip verification language at present, the languages are characterized in that the verification code needs to be recompiled every time the verification code is modified, and when the chip verification language is used for large-scale test data sets, the verification efficiency is undoubtedly reduced by frequent compiling operation. To solve this problem, CN101515301A, a method for generating a configuration file by using configuration and module constraint conditions required for chip verification, and sending the configuration file to a chip for chip verification according to the information of a well-defined instruction interpretation module decoding. Although this approach reduces the operations of repeated compilation by generating configuration and stimulus files separately, it introduces an instruction interpretation module and does not improve the problem of fast localization of proof debugging.
CN106708687A discloses a method and apparatus for verifying chip based on executable file, which can reduce the memory occupation of simulation and improve the security of algorithm source code by generating an executable file containing configuration information and data packet, which is independent of verification environment. However, the executable file is realized based on C, a large amount of test case tests can carry out frequent compiling operation, in addition, the confidentiality of source codes is improved, meanwhile, the verification process is also split into two steps of operation, and the flexibility of verification is reduced.
Disclosure of Invention
Aiming at the problems in the prior art, the invention aims to provide a chip simulation verification method, a system, equipment and a storage medium, which are applied to simulation and verification of a neural network model inference chip and realize rapid function verification of different neural network models and operators.
The embodiment of the invention provides a chip simulation verification method, which comprises the following steps:
obtaining a chip verification configuration file, wherein the chip verification configuration file comprises operator parameters and test parameters, the operator parameters comprise configuration parameters of each operator, the test parameters comprise an operation mode, and the operation mode comprises single operator test and/or chip model integral test;
generating random excitation data according to the chip verification configuration file;
inputting the random excitation data into a corresponding simulation operator or simulation algorithm model according to the operation mode, and acquiring a simulation result;
generating an input file of an input chip according to the random excitation data and the input data format requirement of the chip;
inputting the input file into a chip and acquiring an output result of the chip;
and comparing the simulation result with the output result of the chip to obtain a chip verification result.
In some embodiments, the chip verification configuration file is an excel file, an operator parameter and a test parameter of at least one test case are defined in the excel file, and the test parameter further includes a test case number.
In some embodiments, the generating random excitation data according to the chip verification configuration file includes:
determining test task information according to the operator parameters and the test parameters of each test case in the chip verification configuration file;
and generating random excitation data corresponding to each test task according to the test task information.
In some embodiments, an implementation environment of the chip simulation verification method is constructed based on Python language.
In some embodiments, inputting the random excitation data into a corresponding simulation operator or simulation algorithm model according to the operation mode, and obtaining a simulation result, including the following steps:
constructing a simulation operator for testing based on the operator parameters;
judging whether the operation mode is a single operator test or a chip model integral test;
and if the operation mode is a single operator test, inputting the random excitation data into the corresponding simulation operator, and acquiring output data from the corresponding simulation operator as a simulation result.
In some embodiments, when the operation mode includes a chip model overall test, the test parameters further include connection relationships of operators during the chip model overall test.
In some embodiments, inputting the random excitation data into a corresponding simulation operator or simulation algorithm model according to the operation mode, and obtaining a simulation result, including the following steps:
constructing a simulation operator for testing based on the operator parameters;
judging whether the operation mode is a single operator test or a chip model integral test;
if the operation mode is a chip model integral test, constructing a simulation algorithm model connecting corresponding simulation operators according to the connection relation of each operator in the test parameters;
and inputting the random excitation data into the constructed simulation algorithm model, and acquiring output data from the simulation algorithm model as a simulation result.
In some embodiments, the chip verification configuration file further includes address parameters, the address parameters include an input data address and an output data address in the chip, and the chip is configured to receive the input file, store the input data address and store the output result in the output data address;
and acquiring the output result of the chip, including reading the output result of the chip from the output data address of the chip.
In some embodiments, the address parameters further include a model parameter address in a chip, the chip further configured to read chip model parameters from the model parameter address.
In some embodiments, after obtaining the simulation result, the method further includes: saving the simulation result as a text file;
after obtaining the output result of the chip, the method further comprises the following steps: and saving the output result of the chip as a text file.
In some embodiments, if the current mode is the joint debugging verification mode, after the chip verification result is obtained, the method further includes the following steps:
judging whether the output result of the simulation algorithm model is consistent with the output result of the chip or not;
if not, performing problem positioning on the codes of the simulation operator and/or the simulation algorithm model in a verification environment based on Python language;
and after the problem is positioned, adjusting the corresponding codes in the simulation operator and/or simulation algorithm model and the corresponding codes in the chip model.
In some embodiments, if the current batch verification mode is the batch verification mode, after the chip verification result is obtained, the method further includes the following steps:
recording a chip verification result, and judging whether an output result of the simulation algorithm model is consistent with an output result of the chip;
if the chip is consistent with the chip verification result, the chip verification is determined to be successful;
and if the chip verification is inconsistent, determining that the chip verification fails.
The embodiment of the invention also provides a chip simulation verification system, which is used for realizing the chip simulation verification method and comprises the following steps:
the verification configuration module is used for acquiring a chip verification configuration file, wherein the chip verification configuration file comprises operator parameters and test parameters, the operator parameters comprise configuration parameters of each operator, the test parameters comprise an operation mode, and the operation mode comprises single operator test and/or chip model integral test;
the data generation module is used for generating random excitation data according to the chip verification configuration file;
the model simulation module is used for inputting the random excitation data into a corresponding simulation operator or simulation algorithm model according to the operation mode;
the data preparation module is used for generating an input file of an input chip according to the random excitation data and the input data format requirement of the chip and inputting the input file into the chip;
and the comparison verification module is used for acquiring a simulation result and an output result of the chip, and comparing the simulation result with the output result of the chip to obtain a chip verification result.
An embodiment of the present invention further provides a chip simulation verification apparatus, including:
a processor;
a memory having stored therein executable instructions of the processor;
wherein the processor is configured to perform the steps of the chip emulation verification method via execution of the executable instructions.
The embodiment of the invention also provides a computer readable storage medium for storing a program, and the program realizes the steps of the chip simulation verification method when being executed by a processor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
The chip simulation verification method, the system, the equipment and the storage medium have the following beneficial effects:
the invention is applied to simulation and verification of a neural network model reasoning chip, realizes rapid function verification of different neural network models and operators, comprises the whole flow design from the entrance of a test case to the simulation and result verification of hardware functions, combines the characteristics of the neural network model, realizes the chip simulation and verification of an AI algorithm model by taking the operators as units, can improve the operator reuse rate, can follow up the continuously developed algorithm model in time, and accelerates the chip research and development landing speed of a business model.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings.
FIG. 1 is a flow chart of a chip emulation verification method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of obtaining simulation results according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for verifying chip simulation in joint debugging mode according to an embodiment of the present invention;
FIG. 4 is a flowchart of a method for verifying chip simulation in batch verification mode according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a chip emulation verification system according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the interaction of the modules in the joint tone verification mode according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of the interaction of the modules in batch verification mode according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a chip emulation verification apparatus according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the steps. For example, some steps may be decomposed, and some steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
As shown in fig. 1, an embodiment of the present invention provides a chip simulation verification method, which is applied to simulation and verification of a neural network model inference chip, and the method includes the following steps:
s100: obtaining a chip verification configuration file, wherein the chip verification configuration file comprises operator parameters and test parameters, the operator parameters comprise configuration parameters of each operator, the test parameters comprise an operation mode, and the operation mode comprises single operator test and/or chip model integral test;
s200: generating random excitation data according to the chip verification configuration file;
s300: inputting the random excitation data into a corresponding simulation operator or simulation algorithm Model according to the operation mode, and acquiring a simulation result, wherein the simulation algorithm Model is a Reference Model (RM) for simulating the chip and verifying the result;
s400: generating an input file of an input chip according to the random excitation data and the input data format requirement of the chip;
s500: inputting the input file into a chip and acquiring an output result of the chip;
s600: and comparing the simulation result with the output result of the chip to obtain a chip verification result.
The Artificial Intelligence (AI) algorithm is different from the traditional algorithm, has various forms and fast version iteration speed, and is represented by more layers and more various operator types. Different algorithms are combined to form different algorithm models. The operator is composed of a plurality of hyper-parameters, a large number of test cases can be generated by randomly combining the hyper-parameters, and the characteristics require that a chip verification framework of the AI algorithm is lighter and has high flexibility. If the UVM verification platform in the prior art is adopted, a large amount of time is needed to build a frame in the early stage, and the UVM verification platform cannot be applied to the variability of an AI algorithm in the later stage.
In the invention, the operator is an individual functional unit in the neural network model, and the convolutional neural network model is taken as an example and comprises a convolution operator, a pooling operator, a full-link operator and the like. The chip simulation verification method realizes the rapid functional verification of different neural network models and operators, and comprises the whole process design from the entrance of a test case to the simulation of hardware functions and result verification. Specifically, the chip simulation verification method can be deployed on a PC or a server to construct a chip simulation verification environment, the chip simulation verification environment combines the characteristics of a neural network model, the chip simulation and verification of an AI algorithm model are realized by taking operators as units, the operators can carry out function verification independently, different simulation operators can be constructed quickly based on operator parameters, different operators can be combined into various different models, test cases can be generated automatically in batches, the operator reuse rate is improved, the continuously developed algorithm model can be followed in time, and the chip research and development landing speed of a business model is accelerated.
In this embodiment, the chip verification configuration file defines operator parameters and test parameters of at least one test case, and the test parameters further include a test case number. The test case may be a functional test directed to an operator, or a test directed to a model, where one model includes a plurality of operators, and the operators in the model are connected according to a certain order. Different operator parameters may form different operator test cases. Taking a common convolution operator as an example, the operator parameters include the length, width, channel number, convolution kernel size, convolution step length, zero padding mode and the like of the output. When one test case is used for testing the operator, the operation mode of the test case is the single operator test, so that the function of the single operator can be tested, and the problem tracking and positioning are convenient when the problem is verified.
When one test case is a test aiming at a chip model, the operation mode is the whole test of the chip model, different operator parameters can be adopted to form different simulation operators according to different chip models, and different chip models are formed by adopting different model architectures, so that the multiplexing of operators can be realized, and different model architectures can be simulated rapidly.
In this embodiment, the chip verification configuration file is an excel file, in which related parameters of a plurality of Test cases can be defined simultaneously, and only the related parameters in the chip verification configuration file need to be changed for different chips to be tested (DUTs) or different Test cases of the same chip to be tested, which is convenient for the configuration of the chip verification personnel. The same excel file is adopted for chip verification configuration, common parameters among different test cases can be combined conveniently, an independent file is used as an entrance of chip verification, misoperation and missing operation of directly operating verification codes are avoided, a large number of test case configurations can be automatically generated according to rule definition, and verification requirements of large-scale test cases in batches are met.
In this embodiment, the chip verification configuration file further includes address parameters, where the address parameters include an input data address and an output data address in a chip, and the chip is configured to receive the input file of step S400, store the input data address in the chip, and store the output result in the output data address after performing model operation according to the input file to obtain the output result. In step S500, obtaining the output result of the chip includes reading the output result of the chip from the output data address of the chip.
In this embodiment, the address parameter further includes a model parameter address in the chip, and specifically, the model parameter address is a storage address of the model parameter in a register of the chip. The chip is also configured to read chip model parameters from the model parameter addresses, where the chip model parameters are model parameters determined by the model during the training process.
In this embodiment, the step S200: generating random excitation data according to the chip verification configuration file, comprising:
determining test task information according to the operator parameters and the test parameters of each test case in the chip verification configuration file, wherein the test task information specifically comprises whether a single operator or a whole model is to be tested, the operator parameters and test input data, and when a plurality of test cases exist, a test task is respectively determined corresponding to each test case;
and generating random excitation data corresponding to each test task according to the test task information, wherein the random excitation data can be a random test vector which contains input data required to be provided for the chip.
After the random excitation data is obtained, because the format requirements of different chips on the input data are different, for example, the arrangement order of different parameters is different, an input file of the input chip is further generated according to the random excitation data and the format requirements of the input data of the chips through step S400. The format of this input file may be text, or other types of file formats.
As shown in fig. 2, in this embodiment, the step S300: inputting the random excitation data into a corresponding simulation operator or simulation algorithm model according to the operation mode, and acquiring a simulation result, wherein the method comprises the following steps:
s310: constructing a simulation operator for testing based on the operator parameters, specifically, codes of operators of different types are preset in the chip simulation verification environment, and the simulation operator for testing can be obtained through combination of the operator parameters and the codes of the corresponding operators;
s320: judging whether the operation mode is a single operator test or a chip model integral test;
s330: and if the operation mode is a single operator test, inputting the random excitation data into the corresponding simulation operator, and acquiring output data from the corresponding simulation operator as a simulation result.
When the operation mode is a single operator test, for a chip, the input of the chip is the input of a corresponding operator in the chip, and the output of the corresponding operator in the chip is the output result of the chip.
In this embodiment, the operation mode includes that when the chip model is integrally tested, the test parameters further include connection relationships of operators when the chip model is integrally tested. For example, taking a five-layer model as an example, from the inside, the output of the first layer operator is the input of the second layer operator, the output of the second layer operator is the input of the third layer operator, the output of the third layer operator is the input of the fourth layer operator, the output of the fourth layer operator is the end-to-end form of the input of the fifth layer operator, and from the outside, the output of the fifth layer is given to the input of the first layer. The internal end-to-end connection relation is defined in the test parameters of the chip verification configuration file.
For example, if a convolutional neural network model includes a convolutional operator, a pooling operator and a full link operator, operator parameters of the convolutional operator, the pooling operator and the full link operator of the test case need to be defined in a chip verification configuration file, an operation mode is defined as a chip model integral test, and a sequence in which the convolutional operator, the pooling operator and the full link operator are sequentially connected is defined. Here, the connection relationship between different operators is defined, and the connection order can be defined by using the IDs of the operators. In different test cases, if the same operator parameters are adopted, the same operator parameters can be merged. For example, the test case A includes convolution operator 101, convolution operator 102, pooling operator 201, pooling operator 202, and all-connected operator 301, and the connection sequence thereof is 101-. The test case A and the test case B have the same convolution operator 101 and the same pooling operator 201, and the operator parameters of the convolution operator 101 and the pooling operator 201 can be configured in the chip verification configuration file only once and can be quoted in different test cases. That is, in the chip verification configuration file, operator parameters of a plurality of different operators can be configured in advance, and when each test case is defined, the operator ID referred by the test case is defined to refer to the operator parameters of the operator without repeated definition, so that algorithm multiplexing can be realized more conveniently, and the efficiency of editing the chip verification configuration file is improved.
As shown in fig. 2, in this embodiment, the step S320: after the operation mode is judged to be a single operator test or a chip model integral test, the method further comprises the following steps:
s340: if the operation mode is a chip model integral test, constructing a simulation algorithm model connecting corresponding simulation operators according to the connection relation of each operator in the test parameters;
s350: and inputting the random excitation data into the constructed simulation algorithm model, and acquiring output data from the simulation algorithm model as a simulation result.
Specifically, for step S310, if multiple test cases all involve the same operator, the simulation operator only needs to be constructed once, and repeated construction is not needed. That is, step S310 may further include: and judging whether a simulation operator corresponding to the operator parameter exists or not, if so, repeatedly constructing the simulation operator, and if not, constructing the simulation operator for testing based on the operator parameter. In step S340, the codes of the simulation operators may be combined according to the connection relationship of the operators, so as to obtain an overall code of the simulation algorithm model.
The existing chip verification is mostly finished by adopting a C/C + +/system Verilog/system C language, and small modification at each time needs to be recompiled, which is not beneficial to the generation and maintenance of a large number of test cases. In this embodiment, an implementation environment of the chip simulation verification method is constructed based on Python language. Python is a new script language in recent years, has simple grammar, does not need to consider the problem of memory leakage, can instantly modify codes, gradually debug the codes, and is easier to generate a large number of test cases and position problems in verification. The verification efficiency of the chip can be accelerated.
The chip simulation verification method simulates the operation logic inside the chip hardware through software, forms a simulation operator and a simulation algorithm model, gradually restores all the processes of the hardware, and saves intermediate process data needing comparison verification in a file form. In this embodiment, after obtaining the simulation result, the step S300 further includes: and saving the simulation result as a text file. The intermediate process files can be used as references of the operation results of the chip on one hand, and on the other hand, whether the hardware design is consistent with the expectation or not can be observed in one step, and if the hardware design is not consistent with the expectation, the simulation algorithm model and the algorithm model of the chip to be tested are synchronously adjusted.
In step S500, after obtaining the output result of the chip, the method further includes: and saving the output result of the chip as a text file. Therefore, when comparing the simulation result with the output result of the chip in step S600, the content of the text file and the content of the text file can be directly compared by the chip verification personnel, thereby avoiding direct interaction between the chip verification personnel and the logic at the bottom layer of the chip, separating the chip verification personnel from the chip developer, and reducing the threshold of the chip verification personnel to a certain extent. the comparison between the contents of the text file and the text file is more intuitive, and the content comparison efficiency of the chip verification personnel is improved. In another embodiment, software can also be used to automatically compare the output result of the chip with the data of the simulation result and output the comparison result, and the verification personnel of the chip only needs to check the comparison result.
The chip simulation verification method can be applied to batch chip verification, can also be used for joint debugging verification during chip development, and is suitable for joint debugging stages after various functions of the chip are integrated. If the result of a certain function is found to be inconsistent with the expectation, the codes of the simulation operator and/or the simulation algorithm model can be directly tracked step by step in the Python simulation environment, the position of the problem is quickly positioned, and then the corresponding codes in the corresponding simulation operator and/or simulation algorithm model and the corresponding codes in the chip model are adjusted.
Fig. 3 is a flowchart of a chip simulation verification method in the joint debugging verification mode in this embodiment. Specifically, in this embodiment, if the current mode is the joint debugging verification mode, the step S600: after obtaining the chip verification result, the method also comprises the following steps:
S610-A: judging whether the output result of the simulation algorithm model is consistent with the output result of the chip or not;
S620-A: if not, performing problem positioning on the codes of the simulation operator and/or the simulation algorithm model in a verification environment based on Python language;
S630-A: after the problem is located, adjusting corresponding codes in the simulation operator and/or simulation algorithm model and corresponding codes in the chip model;
S640-A: and if the two are consistent, the joint debugging verification is finished.
The chip simulation verification method can also be used in a batch verification mode, namely in a batch large-scale case regression testing stage after the joint debugging verification is finished. Fig. 4 is a flowchart of a chip simulation verification method in the batch verification mode in this embodiment. Specifically, in this embodiment, if the current batch verification mode is the batch verification mode, after the chip verification result is obtained, the following steps are further included:
S610-B: recording a chip verification result as a verification record file, and judging whether the output result of the simulation algorithm model is consistent with the output result of the chip;
S620-B: if the chip is consistent with the chip to be tested, the chip is determined to be successfully verified, namely the chip to be tested can realize the required function;
S630-B: and if the chip verification is inconsistent, determining that the chip verification fails.
In the batch verification mode, all test cases are configured in a chip verification configuration file, after parameters required by all test cases are given through an excel file, batch regression testing is completed without extra manual intervention, and finally, a verification record file can be inquired to independently analyze the reasons of failure cases. Based on the overall verification method, the chip verification configuration file is the only place needing to be modified, and the verification configuration parameter can be confirmed and modified more intuitively and conveniently by the mode of independently outputting the configuration information of the verification case, so that relatively clean verification environment management is realized. In addition, the design of parameters in the excel file can verify the model operator independently and can also realize the verification of the whole AI algorithm model.
As shown in fig. 5, an embodiment of the present invention further provides a chip simulation verification system, configured to implement the chip simulation verification method, where the system includes:
the verification configuration module M100 is configured to obtain a chip verification configuration file, where the chip verification configuration file includes operator parameters and test parameters, the operator parameters include configuration parameters of each operator, the test parameters include an operation mode, and the operation mode includes a single operator test and/or a chip model integral test;
the data generation module M200 is used for generating random excitation data according to the chip verification configuration file;
the model simulation module M300 is used for inputting the random excitation data into a corresponding simulation operator or simulation algorithm model according to the operation mode;
the data preparation module M400 is used for generating an input file of an input chip according to the random excitation data and the input data format requirement of the chip, and inputting the input file into the chip;
and the comparison verification module M500 is used for acquiring a simulation result and an output result of the chip, and comparing the simulation result and the output result of the chip to obtain a chip verification result.
The chip simulation verification system can be deployed on a PC or a server to construct a chip simulation verification environment, the chip simulation verification environment combines the characteristics of a neural network model, the chip simulation and verification of an AI algorithm model are realized by taking operators as units, the operators can carry out function verification independently, different simulation operators can be constructed quickly based on operator parameters, the different operators can be combined into various different models, test cases can be generated automatically in batches, the operator reuse rate is improved, the continuously developed algorithm model can be followed in time, and the chip research and development landing speed of a business model is accelerated.
The functions of the modules in the chip simulation verification system of the present invention may be implemented by using the specific implementation manners of the above steps, for example, the verification configuration module M100 may obtain a chip verification configuration file through the specific implementation manner of step S100, the data generation module M200 may generate random excitation data through the specific implementation manner of step S200, the model simulation module M300 may perform simulation input through the specific implementation manner of step S300, the data preparation module M400 may perform chip input through the specific implementation manners of step S400 and step S500, the comparison verification module M500 may obtain a simulation result and an output result of the chip through the specific implementation manner obtained in the steps S300 and S500, and perform result comparison through the specific implementation manner of step S600, which is not described herein again.
The chip simulation verification system can be applied to batch chip verification, joint debugging verification during chip development and joint debugging stages after integration of various functions of the chip.
As shown in fig. 6, it is an interaction schematic diagram of each module in the joint verification mode of this embodiment, in this mode, after the verification module M500 is compared to obtain the chip verification result, if the chip verification result is inconsistent with the chip verification result, the model simulation module M300 returns to modify the code of the simulation operator and/or the simulation algorithm model, and returns to the chip to be tested to modify the model in the chip. As shown in fig. 7, which is an interaction diagram of each module in the batch verification mode of this embodiment, after the verification module M500 is compared to obtain the chip verification result, if the chip verification result is inconsistent, the chip verification fails, the reason for the chip verification failure may be found by querying the verification record file, and if the chip verification result is consistent, the chip verification succeeds, that is, the chip may implement the required function.
The embodiment of the invention also provides a chip simulation verification device, which comprises a processor; a memory having stored therein executable instructions of the processor; wherein the processor is configured to perform the steps of the chip emulation verification method via execution of the executable instructions.
As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or program product. Thus, various aspects of the invention may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" platform.
An electronic device 600 according to this embodiment of the invention is described below with reference to fig. 8. The electronic device 600 shown in fig. 8 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present invention.
As shown in fig. 8, the electronic device 600 is embodied in the form of a general purpose computing device. The components of the electronic device 600 may include, but are not limited to: at least one processing unit 610, at least one storage unit 620, a bus 630 that connects the various system components (including the storage unit 620 and the processing unit 610), a display unit 640, and the like.
Wherein the storage unit stores program code executable by the processing unit 610, such that the processing unit 610 performs the steps according to various exemplary embodiments of the present invention described in the chip simulation verification method section above in this specification. For example, the processing unit 610 may perform the steps as shown in fig. 1.
The storage unit 620 may include readable media in the form of volatile memory units, such as a random access memory unit (RAM)6201 and/or a cache memory unit 6202, and may further include a read-only memory unit (ROM) 6203.
The memory unit 620 may also include a program/utility 6204 having a set (at least one) of program modules 6205, such program modules 6205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.
The electronic device 600 may also communicate with one or more external devices 700 (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the electronic device 600, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 600 to communicate with one or more other computing devices. Such communication may occur via an input/output (I/O) interface 650. Also, the electronic device 600 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the Internet) via the network adapter 660. The network adapter 660 may communicate with other modules of the electronic device 600 via the bus 630. It should be appreciated that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.
In the chip simulation verification device, the program in the memory is executed by the processor to realize the steps of the chip simulation verification method, so the device can also obtain the technical effect of the chip simulation verification method.
The embodiment of the invention also provides a computer readable storage medium for storing a program, and the program realizes the steps of the chip simulation verification method when being executed by a processor. In some possible embodiments, aspects of the present invention may also be implemented in the form of a program product comprising program code for causing a terminal device to perform the steps according to various exemplary embodiments of the present invention described in the chip emulation verification method section above of this specification, when the program product is executed on the terminal device.
Referring to fig. 9, a program product 800 for implementing the above method according to an embodiment of the present invention is described, which may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be executed on a terminal device, such as a personal computer. However, the program product of the present invention is not limited in this regard and, in the present document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable storage medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable storage medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).
The program in the computer storage medium implements the steps of the chip simulation verification method when being executed by the processor, and therefore, the computer storage medium can also obtain the technical effects of the chip simulation verification method.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (15)
1. A chip simulation verification method is characterized by comprising the following steps:
obtaining a chip verification configuration file, wherein the chip verification configuration file comprises operator parameters and test parameters, the operator parameters comprise configuration parameters of each operator, the test parameters comprise an operation mode, and the operation mode comprises single operator test and/or chip model integral test;
generating random excitation data according to the chip verification configuration file;
inputting the random excitation data into a corresponding simulation operator or simulation algorithm model according to the operation mode, and acquiring a simulation result;
generating an input file of an input chip according to the random excitation data and the input data format requirement of the chip;
inputting the input file into a chip and acquiring an output result of the chip;
and comparing the simulation result with the output result of the chip to obtain a chip verification result.
2. The chip simulation verification method according to claim 1, wherein the chip verification configuration file is an excel file, operator parameters and test parameters of at least one test case are defined in the excel file, and the test parameters further include a test case number.
3. The method of claim 2, wherein the generating random stimulus data according to the chip verification configuration file comprises:
determining test task information according to the operator parameters and the test parameters of each test case in the chip verification configuration file;
and generating random excitation data corresponding to each test task according to the test task information.
4. The chip simulation verification method according to claim 1, wherein an implementation environment of the chip simulation verification method is constructed based on Python language.
5. The chip simulation verification method according to claim 1, wherein the random excitation data is input into a corresponding simulation operator or simulation algorithm model according to the operation mode, and a simulation result is obtained, comprising the steps of:
constructing a simulation operator for testing based on the operator parameters;
judging whether the operation mode is a single operator test or a chip model integral test;
and if the operation mode is a single operator test, inputting the random excitation data into the corresponding simulation operator, and acquiring output data from the corresponding simulation operator as a simulation result.
6. The method for chip simulation verification according to claim 1, wherein the operation mode includes a connection relationship between operators in the whole chip model test, and the test parameters further include a connection relationship between operators in the whole chip model test.
7. The chip simulation verification method according to claim 6, wherein the random excitation data is input into a corresponding simulation operator or simulation algorithm model according to the operation mode, and a simulation result is obtained, comprising the steps of:
constructing a simulation operator for testing based on the operator parameters;
judging whether the operation mode is a single operator test or a chip model integral test;
if the operation mode is a chip model integral test, constructing a simulation algorithm model connecting corresponding simulation operators according to the connection relation of each operator in the test parameters;
and inputting the random excitation data into the constructed simulation algorithm model, and acquiring output data from the simulation algorithm model as a simulation result.
8. The method of claim 1, wherein the chip verification configuration file further comprises address parameters, the address parameters comprise an input data address and an output data address in the chip, and the chip is configured to receive the input file, store the input data address and store the output result in the output data address;
and acquiring the output result of the chip, including reading the output result of the chip from the output data address of the chip.
9. The method of claim 8, wherein the address parameters further comprise a model parameter address in the chip, and the chip is further configured to read chip model parameters from the model parameter address.
10. The method for verifying chip simulation according to claim 1, wherein after obtaining the simulation result, the method further comprises: saving the simulation result as a text file;
after obtaining the output result of the chip, the method further comprises the following steps: and saving the output result of the chip as a text file.
11. The method for verifying chip simulation according to claim 4, wherein if the current mode is the joint debugging verification mode, after the chip verification result is obtained, the method further comprises the following steps:
judging whether the output result of the simulation algorithm model is consistent with the output result of the chip or not;
if not, performing problem positioning on the codes of the simulation operator and/or the simulation algorithm model in a verification environment based on Python language;
and after the problem is positioned, adjusting the corresponding codes in the simulation operator and/or simulation algorithm model and the corresponding codes in the chip model.
12. The method for verifying chip simulation according to claim 11, wherein if the current mode is batch verification mode, after obtaining the chip verification result, the method further comprises the following steps:
recording a chip verification result, and judging whether an output result of the simulation algorithm model is consistent with an output result of the chip;
if the chip is consistent with the chip verification result, the chip verification is determined to be successful;
and if the chip verification is inconsistent, determining that the chip verification fails.
13. A chip simulation verification system for implementing the chip simulation verification method according to any one of claims 1 to 12, the system comprising:
the verification configuration module is used for acquiring a chip verification configuration file, wherein the chip verification configuration file comprises operator parameters and test parameters, the operator parameters comprise configuration parameters of each operator, the test parameters comprise an operation mode, and the operation mode comprises single operator test and/or chip model integral test;
the data generation module is used for generating random excitation data according to the chip verification configuration file;
the model simulation module is used for inputting the random excitation data into a corresponding simulation operator or simulation algorithm model according to the operation mode;
the data preparation module is used for generating an input file of an input chip according to the random excitation data and the input data format requirement of the chip and inputting the input file into the chip;
and the comparison verification module is used for acquiring a simulation result and an output result of the chip, and comparing the simulation result with the output result of the chip to obtain a chip verification result.
14. A chip emulation verification apparatus, comprising:
a processor;
a memory having stored therein executable instructions of the processor;
wherein the processor is configured to perform the steps of the chip simulation verification method of any one of claims 1 to 12 via execution of the executable instructions.
15. A computer-readable storage medium storing a program, wherein the program, when executed by a processor, implements the steps of the chip simulation verification method of any one of claims 1 to 12.
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