CN111752839A - Test case, rule generation method, chip test method, device, equipment and medium - Google Patents
Test case, rule generation method, chip test method, device, equipment and medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a test case, a test case rule generation method, a chip test method, a device, equipment and a medium. The method for generating the test case comprises the following steps: generating a plurality of alternative test cases according to an original case rule base matched with a chip to be tested; calling at least one standard operator provided by the gold system to execute each alternative test case and acquiring an execution result of each alternative test case; and according to the execution result, dividing each alternative test case into a normal test case set and an abnormal test case set. The technical scheme of the embodiment of the invention can quickly, accurately and automatically generate the test case meeting the test requirement.
Description
Technical Field
Embodiments of the present invention relate to test technologies, and in particular, to a test case, a test case rule generation method, a test case rule generation device, a chip test method, a chip test apparatus, a chip test device, and a medium.
Background
A test case is a set of test inputs, execution conditions, and expected results that are tailored for a particular purpose to verify that a particular system under test (e.g., an application or data processing chip, etc.) meets a particular data processing requirement. The test cases generally include normal test cases or abnormal test cases. The normal test case is a test case with an expected result being normally executed, and the abnormal test case is a test case with an expected result being an abnormal error.
Whether the test case is a normal test case or an abnormal test case, the test case is generally obtained by manual design of experienced testers, and the testers need to thoroughly understand each functional module or an implementation mechanism of a system to be tested so as to compile the test case meeting the conditions.
In the process of implementing the invention, the inventor finds that the prior art has the following defects: the test case can be generated manually only after the experienced testers deeply know the system to be tested, the requirement on the testers is high, the implementation cost is high, and a large amount of time is consumed.
Disclosure of Invention
The embodiment of the invention provides a test case, a test case rule generation method, a chip test method, a device, equipment and a medium, which are used for quickly, accurately and automatically generating the test case meeting the test requirement.
In a first aspect, an embodiment of the present invention provides a method for generating a test case, where the method for generating a test case includes:
generating a plurality of alternative test cases according to an original case rule base matched with a chip to be tested;
calling at least one standard operation operator provided by the gold system to execute each alternative test case and acquiring an execution result of each alternative test case;
and according to the execution result, dividing each alternative test case into a normal test case set and an abnormal test case set.
In a second aspect, an embodiment of the present invention further provides a method for generating a test case rule, where the method for generating a test case rule includes:
generating a plurality of alternative test cases according to an original case rule base matched with a chip to be tested;
calling at least one standard operation operator provided by the gold system to execute each alternative test case and acquiring an execution result of each alternative test case;
dividing each alternative test case into a normal test case set and an abnormal test case set according to an execution result;
and generating a normal case rule base and an abnormal case rule base according to the normal test case set and/or the abnormal test case set.
In a third aspect, an embodiment of the present invention further provides a chip testing method, where the chip testing method includes:
acquiring a target test case;
calling at least one standard operation operator provided by the gold system to execute the target test case and acquiring a first execution result of the target test case;
calling at least one hardware execution unit included in the chip to be tested to execute the target test case, and acquiring a second execution result of the target test case;
and if the first execution result is inconsistent with the second execution result, determining that the chip to be tested does not pass the test.
In a fourth aspect, an embodiment of the present invention further provides a device for generating a test case, where the device for generating a test case includes:
the alternative test case generation module is used for generating a plurality of alternative test cases according to the original case rule base matched with the chip to be tested;
the execution result acquisition module is used for calling at least one standard operation operator provided by the gold system to execute each alternative test case and acquiring the execution result of each alternative test case;
and the test case dividing module is used for dividing each alternative test case into a normal test case set and an abnormal test case set according to the execution result.
In a fifth aspect, an embodiment of the present invention further provides a device for generating a test case rule, where the device for generating a test case rule includes:
the alternative test case generation module is used for generating a plurality of alternative test cases according to the original case rule base matched with the chip to be tested;
the execution result acquisition module is used for calling at least one standard operation operator provided by the gold system to execute each alternative test case and acquiring the execution result of each alternative test case;
the test case dividing module is used for dividing each alternative test case into a normal test case set and an abnormal test case set according to the execution result;
and the rule base generation module is used for generating a normal case rule base and an abnormal case rule base according to the normal test case set and/or the abnormal test case set.
In a sixth aspect, an embodiment of the present invention further provides a chip testing apparatus, where the chip testing apparatus includes:
the target test case acquisition module is used for acquiring a target test case;
the first execution result acquisition module is used for calling at least one standard operator provided by the gold system to execute the target test case and acquiring a first execution result of the target test case;
the second execution result acquisition module is used for calling at least one hardware execution unit included in the chip to be tested to execute the target test case and acquiring a second execution result of the target test case;
and the test verification module is used for determining that the chip to be tested does not pass the test if the first execution result is inconsistent with the second execution result.
In a seventh aspect, an embodiment of the present invention further provides a computer device, where the computer device includes:
one or more processors;
a storage device for storing one or more programs,
when the one or more programs are executed by the one or more processors, the one or more processors implement the test case generation method, as any one of the embodiments of the present invention, or implement the test case rule generation method, as any one of the embodiments of the present invention, or implement the chip test method, as any one of the embodiments of the present invention.
In an eighth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements a method for generating a test case according to any one of the embodiments of the present invention, or implements a method for generating a test case rule according to any one of the embodiments of the present invention, or implements a method for testing a chip according to any one of the embodiments of the present invention.
According to the technical scheme of the embodiment of the invention, the standard arithmetic operator in the gold system is used as the correctness verification standard of the chip to be tested, and the normal test case, the abnormal test case and the test case rule which meet the test requirement can be quickly, accurately and automatically generated only by using the roughly constructed original case rule library according to the execution result of the gold system on the test case, so that the chip to be tested can be effectively verified in availability. The labor and time cost required by constructing the test case are greatly reduced, and the test efficiency of the chip to be tested is improved.
Drawings
FIG. 1 is a flowchart illustrating an implementation of a method for generating a test case according to a first embodiment of the present invention;
FIG. 2 is a flowchart illustrating an implementation of a method for generating test case rules according to a second embodiment of the present invention;
FIG. 3 is a flowchart illustrating an implementation of a method for generating test case rules according to a third embodiment of the present invention;
FIG. 4 is a flowchart of an implementation of a chip testing method according to a fourth embodiment of the present invention;
fig. 5 is a structural diagram of a test case generation apparatus according to a fifth embodiment of the present invention;
fig. 6 is a structural diagram of a test case rule generation apparatus according to a sixth embodiment of the present invention;
fig. 7 is a structural diagram of a chip testing apparatus according to a seventh embodiment of the present invention;
fig. 8 is a block diagram of a computer device according to an eighth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example one
Fig. 1 is a flowchart illustrating an implementation of a method for generating a test case according to an embodiment of the present invention, where the method is applicable to a situation where an original case rule base obtained by rough setting is used to generate a test case meeting test requirements quickly, accurately, and automatically, and the method may be executed by a device for generating a test case, where the device may be implemented by software and/or hardware, and may be generally integrated in various computer devices (e.g., a desktop computer, a server, or a notebook computer) having a data processing function. The method of the embodiment of the invention specifically comprises the following steps:
and S110, generating a plurality of alternative test cases according to the original case rule base matched with the chip to be tested.
In this embodiment, the chip to be tested refers to a hardware chip that needs to use the test case for performing an availability test, and the chip to be tested can execute the test case and obtain a matching execution result.
Optionally, the chip to be tested may include one or more hardware execution units, where the hardware execution units are configured to execute the setting data processing and the calculation operation in a hardware manner. The types of data may include: a numerical value, a vector, an array, a matrix, an image, or the like, which is not limited in this embodiment.
Optionally, the data processing and computing operations that the hardware execution unit may perform may be: operations between at least two values, for example: addition, subtraction, multiplication, division, and the like, and may be: the setting operation between at least two matrices, for example, matrix addition, matrix multiplication, convolution between matrices, or the like, may be a setting operation for the same value or matrix, for example: squaring, matrix transposition or solving an inverse matrix of the matrix and the like; an image processing operation for the setting image, for example, image flipping, image clipping, or image format conversion, may be performed.
In order to test the chip to be tested, test cases (normal test cases and abnormal test cases) meeting the test requirements of the chip to be tested need to be constructed. In the embodiment, a tester does not need to deeply learn, master the implementation mechanism and principle of the chip to be tested to design a very accurate test case, and only a wider and rough original case rule base is set.
The raw case rule library stores one or more raw case rules, and the raw case rules may include an operator, a data value range corresponding to the operator, a data type (e.g., integer, long integer, or floating point) matched with the operator, and the like. And matching the operational characters included in the original case rule with the hardware execution units in the chip to be tested. Optionally, different data types (values, matrices, or arrays, etc.) correspond to different operators.
Optionally, the operator may include: the data type corresponding to the operator may be a floating point type or an integer type, and the range of the data value corresponding to the operator may be [ - ∞, + ∞ ].
It can be understood that the matched data value range and data type can be set widely only according to the physical meaning of the operator, and the set original use case rule is not required to be guaranteed, and the optimum use case rule which can be adapted by the hardware execution unit in the chip to be tested is determined. Particularly, considering that a plurality of normal test cases and a plurality of abnormal test cases need to be constructed respectively to test a chip to be tested, it is not necessary to ensure that the original case rule must meet the physical meaning of an operator, for example, a squared value must be a positive number, a denominator in two divided values cannot be 0, or row and column values in two multiplied matrixes must meet a set numerical relationship, and the like, so as to ensure the diversity and completeness of the types of the alternative test cases obtained through the original case rule base construction.
In this embodiment, one or more matched raw case rules may be acquired from a raw case rule library in a set raw case rule combination manner, and a plurality of matched candidate test cases are constructed based on the acquired raw case rules.
The alternative test case may be a normal test case or an abnormal test case for testing the chip to be tested. In a specific example, the alternative test case is a calculation formula composed of one or more specific data and one or more operators. For example: 9+7-6, or matrix a matrix B, etc.; the size or format of the input image may be set for one sheet.
Optionally, multiple candidate test cases matched with the original case rule base may be generated through a preset case generator.
And S120, calling at least one standard operator provided by the gold system to execute each alternative test case, and acquiring an execution result of each alternative test case.
In this embodiment, since the role of a person in the test case design process is weakened, the type of the test case (normal test case or abnormal test case), or the execution result of the test case (normal execution, or generation of abnormal error) needs to be predetermined in other ways. Based on this, the inventor creatively proposes to use the golden system as a correctness verification standard for the test case execution result.
Optionally, the alternative test case includes at least one operator, and the chip to be tested includes a hardware execution unit matched with the operator; the operational characters are matched with standard operational operators provided by the golden system, and the standard operational operators are in one-to-one correspondence with hardware execution units of the chip to be tested.
It is understood that various deep learning models (also referred to as neural networks) or frameworks that are widely used today provide various standard operators, such as numerical operations, vector operations, matrix operations, convolution operations, or various image processing operations. The standard operator may be run on a CPU (central Processing Unit) or a GPU (Graphics Processing Unit). Therefore, the neural network or the learning framework can be used as a golden system to execute each alternative test case.
According to a specific application or an operator to be realized by a chip, a related network or a learning framework adopted in the industry, such as TensorFlow, Caffe, Pythroch or Keras in a golden system, can be selected as a golden system, and the selected golden system contains reference implementations of various operators to be realized. Because the golden system for realizing the operators is relatively mature and stable in technology, the golden system can be used as a correctness verification standard for the execution result of the test case.
It will be understood, of course, that the above examples of specific forms of the golden system are merely exemplary, and in fact, those skilled in the art may also use other types of neural networks or learning frameworks, which are used in the art, and the present embodiment is not limited thereto.
As described above, since at least one item of standard operators preset and provided in the gold system is matched with the operators used in the alternative test cases, each alternative test case can be executed by calling the standard operators matched with the operators in the alternative test cases in the gold system, and the execution result of each alternative test case is obtained.
If the gold system can normally execute a certain alternative test case and correspondingly obtain matched case result data, the execution result of the alternative test case is determined to be normal, and if the gold system cannot normally execute the certain alternative test case and correspondingly output one or more abnormal errors, the execution result of the alternative test case is determined to be abnormal.
And S130, dividing each alternative test case into a normal test case set and an abnormal test case set according to the execution result.
In this embodiment, if the execution result of one candidate test case is normal, the candidate test case may be classified into a normal test case set, and if the execution result of one candidate test case is abnormal, the candidate test case may be classified into an abnormal test case set.
Correspondingly, the normal test case set and the abnormal test case set are used respectively, so that the chip to be tested can be effectively tested, and each hardware execution module in the chip to be tested can be effectively changed or optimized according to the test result.
According to the technical scheme of the embodiment of the invention, the standard arithmetic operator in the gold system is used as the correctness verification standard of the chip to be tested, and the normal test case and the abnormal test case which meet the test requirement can be quickly, accurately and automatically generated only by using the roughly constructed original case rule base according to the execution result of the gold system on the test case, so that the effective usability verification of the chip to be tested can be further carried out. The labor and time cost required by constructing the test case are greatly reduced, and the test efficiency of the chip to be tested is improved.
In an optional embodiment mode of this embodiment, generating the alternative test case according to the original case rule base may include:
acquiring at least one test case template to be filled, wherein the test case template comprises at least one operator to be filled and at least one data item to be filled;
acquiring at least one operator from an original use case rule base as a target operator;
constructing a target data item according to at least one data value range and at least one data type corresponding to the target operational character in the original case rule base;
and correspondingly filling the target operator and the target data item into each test case module to generate each alternative test case.
The rules stored in the raw case rule base may include: operators, data value ranges and data types. Correspondingly, a mapping relation between the type (numerical value, matrix or array, etc.) of the data and the operator can be established in the original use case rule base, and a mapping relation between the operator and the data value range and between the operator and the data type can be respectively established. Based on the above, each alternative test case can be constructed.
In a specific example, a certain test case template includes: two numeric operators to be filled, and three data items to be filled, one for filling in each data item to be filled. Accordingly, a plurality of sets of numerical operators may be obtained from the original use case rule base, where each set of numerical operators includes two data operators, for example: numeric operator set 1{ "+", "+" }, numeric operator set 2{ "-", "/" }, and so on.
Meanwhile, aiming at each target operator included in the numerical operator set, at least one data value range and at least one data type matched in the original case rule base can be used for constructing corresponding target data items. Specifically, the corresponding target data item may be determined according to the data value range by random selection or by sequential selection according to a set rule. For example, for the set of numeric operators 1, the generated target set of data items is {5.34, 6.23, 7.12} and { -7.33, 40.00, 5.03}, and for the set of numeric operators 2, the generated target set of data items is {7, -5, 0} and { -9, 1368, -2230 }.
Correspondingly, according to the target operator and the target data item, the candidate test case obtained by filling the test case module may be: alternative test case 1: 5.34+6.23 × 7.12, alternative test case 2: (-7.33) +40.00 × 5.03, alternative test case 3: 7- (-5)/0 and alternative test case 4: (-9) -1368/(-2230).
Of course, those skilled in the art will appreciate that alternative test cases may also be constructed in other ways, and this is merely an example of one possible implementation.
The advantages of such an arrangement are: comprehensive and complete alternative test cases can be automatically generated in a traversal mode according to various original case rules in the original case rule base, a large amount of labor cost is saved, and the diversity of the alternative test cases in the alternative test case set can be guaranteed.
Example two
Fig. 2 is a flowchart illustrating an implementation of a method for generating test case rules according to a second embodiment of the present invention, where the method is applicable to a situation where an original case rule base obtained by rough setting is used to generate test case rules meeting test requirements quickly, accurately, and automatically, and the method can be executed by a device for generating test case rules, where the device can be implemented in a software and/or hardware manner, and can be generally integrated into various types of computer devices (e.g., a desktop computer, a server, or a notebook computer, etc.) having a data processing function. Correspondingly, the method of the embodiment of the invention specifically comprises the following steps:
s210, generating a plurality of alternative test cases according to the original case rule base matched with the chip to be tested.
S220, calling at least one standard operator provided by the gold system to execute each alternative test case, and obtaining the execution result of each alternative test case.
Optionally, the alternative test case includes at least one operator, and the chip to be tested includes a hardware execution unit matched with the operator; the operators match the standard operators provided by the golden system.
And S230, dividing each alternative test case into a normal test case set and an abnormal test case set according to the execution result.
S240, generating a normal case rule base and an abnormal case rule base according to the normal test case set and/or the abnormal test case set.
In this embodiment, according to the execution result of each candidate test case output by the gold system, each candidate test case generated by the original case rule base may be divided into a normal test case set and an abnormal test case set, so that the test on the chip to be tested may be implemented. However, if the chip to be tested needs to use a new normal test case or an abnormal test case for testing, the chip to be tested needs to continue to execute the operations from S210 to S230 to obtain the test result, which is relatively complicated.
In this embodiment, the inventor creatively proposes to construct a normal case rule base for generating a normal test case and an abnormal case rule base for generating an abnormal test case based on a normal test case set, an abnormal test case set, or a combination of the normal test case set and the abnormal test case set, which are determined by using the golden system, so that generation steps of the normal test case and the abnormal test case can be simplified, and generation efficiency of the normal test case and the abnormal test case can be improved.
Similar to the original use case rule base, the normal use case rules in the normal use case rule base may include: the data type of the data is matched with the data value range; the abnormal use case rules in the abnormal use case rule base may include: the data type comprises an operator, a data value range matched with the operator and a data type.
Optionally, generating a normal case rule base and an abnormal case rule base according to the normal test case set and/or the abnormal test case set may include:
generating a normal case rule base according to the normal test case set, and generating an abnormal case rule base according to the abnormal test case set; or
And generating an abnormal case rule base according to the abnormal test case set, and generating a normal case rule base according to the original case rule base and the abnormal case rule base.
Specifically, the matched normal case rule base and abnormal case rule base can be respectively generated according to the normal test case set and the abnormal test case set. Or, after the abnormal case rule base is generated according to the abnormal test case set, the complement of the abnormal case rule base in the original case rule base is calculated to be used as the normal case rule base.
Of course, after the normal case rule base is generated according to the normal test case set, the complement of the normal case rule base in the original case rule base can be calculated and used as the abnormal case rule base.
However, considering that the proportion of the abnormal case rule in all the original case rule libraries should be small, that is, the normal case rule included in the normal case rule library is generally much more than the abnormal case rule included in the abnormal case rule library, therefore, the abnormal case rule library may be generated according to the abnormal test case set.
Optionally, a rule generator may be constructed in advance, and each abnormal test case included in the abnormal test case set is input to the rule generator, so as to obtain each abnormal case rule, and further an abnormal case rule base may be constructed according to each abnormal case rule; further, the abnormal case rule base may be constructed manually or semi-manually, but the present embodiment is not limited to this.
According to the technical scheme of the embodiment of the invention, the standard arithmetic operator in the gold system is used as the correctness verification standard of the chip to be tested, and the normal test case rule base and the abnormal test case rule base which meet the test requirements can be quickly, accurately and automatically generated only by using the roughly constructed original case rule base according to the execution result of the gold system on the test case, so that a large number of normal test cases and abnormal test cases can be generated through the normal test case rule base and the abnormal test case rule base to effectively verify the availability of the chip to be tested. The labor and time cost required by constructing the test case are greatly reduced, and the test efficiency of the chip to be tested is improved.
On the basis of the foregoing embodiments, after generating the normal use case rule base and the abnormal use case rule base according to the normal test use case set and/or the abnormal test use case set, the method may further include:
and generating at least one normal test case according to the normal case rule base, and/or generating at least one abnormal test case according to the abnormal case rule base.
The advantages of such an arrangement are: normal test cases and abnormal test cases are not required to be determined again in the newly generated alternative test cases by using the gold system, and the normal test cases and the abnormal test cases meeting requirements can be generated only through the generated normal case rule base and the abnormal case rule base, so that the labor and time cost for constructing the test cases is further reduced, and the test efficiency of the chip to be tested is improved.
EXAMPLE III
Fig. 3 is a flowchart of an implementation of a method for generating test case rules according to a third embodiment of the present invention, which is further detailed based on the above embodiment, in this embodiment, an operation of generating an abnormal case rule base according to an abnormal test case set is set as: clustering the abnormal test cases according to the case parameter information of the abnormal test cases to obtain a plurality of cluster clusters; according to the case parameter information of each abnormal test case in each cluster, a linear equation set corresponding to each cluster is constructed, and the linear relation equation comprises: at least one abnormal case rule to be solved; solving each linear equation set corresponding to each cluster to obtain matched abnormal case rules; and generating an abnormal case rule base according to the various abnormal case rules obtained by solving.
Correspondingly, the method of the embodiment of the invention specifically comprises the following steps:
s310, generating a plurality of alternative test cases according to the original case rule base matched with the chip to be tested.
And S320, calling at least one standard operator provided by the gold system to execute each alternative test case and acquiring an execution result of each alternative test case.
Optionally, the alternative test case includes at least one operator, and the chip to be tested includes a hardware execution unit matched with the operator; the operators match the standard operators provided by the golden system.
S330, according to the execution result, dividing each alternative test case into a normal test case set and an abnormal test case set.
S340, according to the case parameter information of each abnormal test case, clustering the abnormal test cases to obtain a plurality of cluster clusters.
Wherein, the user parameter information may include: operators and data specific values. Correspondingly, clustering processing can be performed on the abnormal test cases according to the types of the operators or the types of the data, so that the same type of the abnormal test cases in the same cluster is ensured.
Optionally, all the abnormal test cases including a specific operator (for example, a matrix transpose operator) may be grouped into the same cluster, or all the abnormal test cases corresponding to the same data type (a numerical value, a matrix, an array, or the like) may be grouped into the same cluster, and the like, which is not limited in this embodiment.
And S350, constructing linear equation sets respectively corresponding to each cluster according to the case parameter information of the abnormal test cases in each cluster.
Wherein, the linear relation equation comprises: at least one exception use case rule to be solved.
In this embodiment, a plurality of abnormal use case rules to be solved may be constructed, and each abnormal use case rule may include one or more unknowns.
And S360, solving each linear equation set corresponding to each cluster to obtain the matched abnormal case rule.
Generally, the number of abnormal test cases will be much greater than the variables contained in the abnormal case rules to be solved. Therefore, the linear equation set obtained for each cluster is generally an overdetermined equation set, and then a plurality of possible abnormal use case rules can be obtained for each linear equation set. After multiple groups of possible abnormal case rules are obtained, the optimal solution can be found through a certain fitting mode, and one or more abnormal case rules respectively matched with each cluster are obtained.
And S370, generating an abnormal use case rule base according to each abnormal use case rule obtained through solving.
And S380, generating a normal case rule base according to the normal test case set.
In this embodiment, the manner of generating the normal case rule base according to the normal test case set is similar to the manner of generating the abnormal case rule base according to the abnormal test case set, and may be, for example:
according to the case parameter information of each normal test case, clustering each normal test case to obtain a plurality of cluster clusters; according to the case parameter information of each normal test case in each cluster, constructing a linear equation set corresponding to each cluster, wherein the linear relation equation comprises: at least one normal case rule to be solved; solving each linear equation set corresponding to each cluster to obtain a matched normal case rule; generating a normal case rule base according to each normal case rule obtained by solving
The technical scheme of the embodiment of the invention is based on the normal test case set, the abnormal test case set or the combination of the normal test case set and the abnormal test case set which are determined by using the golden system, automatically constructs a linear equation set to solve the abnormal case rule and the normal case rule, and constructs a corresponding abnormal case rule library and a corresponding normal case rule library, thereby simplifying the generation steps of the normal test case and the abnormal test case, and improving the generation efficiency of the normal test case and the abnormal test case.
Of course, it is understood that, besides the abnormal use case rule and the normal use case rule may be solved by constructing a linear equation set, other ways may be adopted to generate the abnormal use case rule and the normal use case rule, for example, the abnormal use case rule and the normal use case rule may be obtained by learning by using a pre-constructed abnormal rule generation model or normal rule generation model, and the present embodiment does not limit this.
Example four
Fig. 4 is a flowchart of an implementation of a chip testing method according to a fourth embodiment of the present invention, where the method is applicable to a case where a gold system is used as a correctness verification standard to verify a chip to be tested, and the method may be executed by a chip testing apparatus, where the apparatus may be implemented by software and/or hardware, and may be generally integrated in various computer devices (e.g., a desktop computer, a server, or a notebook computer, etc.) having a data processing function. Correspondingly, the method of the embodiment of the invention specifically comprises the following steps:
and S410, acquiring a target test case.
The target test case may be a normal test case, an abnormal test case, or a test case with unknown execution result. The target test case may be manually constructed, may be obtained from a normal test case set or an abnormal test case set obtained by any embodiment of the present invention, may be automatically generated according to a normal case rule base or an abnormal case rule base obtained by any embodiment of the present invention, and the like, and is not limited herein.
Optionally, the target test case includes at least one operator, and the chip to be tested includes a hardware execution unit matched with the operator.
S420, calling at least one standard operator provided by the gold system to execute the target test case, and acquiring a first execution result of the target test case.
Optionally, the standard operator is matched with the operator.
As described above, in the embodiments of the present invention, the standard operator in the gold system is used as the correctness verification standard of the test case execution result. And then, each alternative test case can be executed by calling a standard operation operator matched with an operator in the alternative test case in the gold system, and an execution result of each alternative test case is obtained.
When the first execution result of the target test case is abnormal, the target test case is proved to have abnormal errors in the execution process, and corresponding case result data cannot be output.
S430, calling at least one hardware execution unit included in the chip to be tested to execute the target test case, and acquiring a second execution result of the target test case.
When the second execution result of the target test case is abnormal, the target test case is indicated to generate an abnormal error in the execution process, and the corresponding case result data cannot be output.
S440, if the first execution result is inconsistent with the second execution result, determining that the chip to be tested does not pass the test.
In this embodiment, if the first execution result and the second execution result are not consistent, that is: the first execution result is normal and the second execution result is abnormal, or the first execution result is abnormal and the second execution result is normal. At this time, it is indicated that the chip under test cannot achieve the expected effect (which is not in accordance with the correctness verification standard of the standard operator in the gold system), and it is determined that the chip under test fails.
Further, if the first execution result and the second execution result obtained by verifying a large number of target test cases are consistent, each hardware execution unit of the chip to be tested can be described, the same effect as that of a standard operation operator realized by each software in the gold system can be achieved, and the chip to be tested passes the test.
According to the technical scheme of the embodiment of the invention, the standard operation operator in the gold system is used as the correctness verification standard of the test case execution result, the type of the test case is not required to be determined to be normal or abnormal in advance, and whether the chip to be tested passes the verification can be quickly judged only by comparing whether the execution results of the chip to be tested and the gold system on the same target test case are consistent, so that a new mode for testing the chip to be tested is provided, and the test efficiency of the chip to be tested is improved.
EXAMPLE five
Fig. 5 is a block diagram of a test case generation apparatus according to a fifth embodiment of the present invention, and as shown in fig. 5, the apparatus includes: an alternative test case generation module 510, an execution result acquisition module 520, and a test case division module 530. Wherein:
an alternative test case generation module 510, configured to generate multiple alternative test cases according to an original case rule base matched with a chip to be tested;
an execution result obtaining module 520, configured to invoke at least one standard operator provided by the gold system to execute each alternative test case, and obtain an execution result of each alternative test case;
the test case dividing module 530 is configured to divide each candidate test case into a normal test case set and an abnormal test case set according to the execution result.
According to the technical scheme of the embodiment of the invention, the standard arithmetic operator in the gold system is used as the correctness verification standard of the chip to be tested, and the normal test case and the abnormal test case which meet the test requirement can be quickly, accurately and automatically generated only by using the roughly constructed original case rule base according to the execution result of the gold system on the test case, so that the effective usability verification of the chip to be tested can be further carried out. The labor and time cost required by constructing the test case are greatly reduced, and the test efficiency of the chip to be tested is improved.
On the basis of the above embodiments, the alternative test case includes at least one operator, and the chip to be tested includes a hardware execution unit matched with the operator; the operators match the standard operators provided by the golden system. On the basis of the foregoing embodiments, the alternative test case generation module 510 may specifically be configured to:
acquiring at least one test case template to be filled, wherein the test case template comprises at least one operator to be filled and at least one data item to be filled;
acquiring at least one operator from an original use case rule base as a target operator;
constructing a target data item according to at least one data value range and at least one data type corresponding to the target operational character in the original case rule base;
and correspondingly filling the target operator and the target data item into each test case module to generate each alternative test case.
On the basis of the above embodiments, the gold system may include: TensorFlow, Caffe, Pytrch, or Keras.
The test case generation device provided by the embodiment of the invention can execute the test case generation method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
EXAMPLE six
Fig. 6 is a structural diagram of an apparatus for generating test case rules according to a sixth embodiment of the present invention, and as shown in fig. 6, the apparatus includes: an alternative test case generating module 610, an execution result obtaining module 620, a test case dividing module 630 and a rule base generating module 640. Wherein:
the alternative test case generation module 610 is configured to generate a plurality of alternative test cases according to the original case rule base matched with the chip to be tested;
an execution result obtaining module 620, configured to invoke at least one standard operator provided by the gold system to execute each alternative test case, and obtain an execution result of each alternative test case;
the test case dividing module 630 is configured to divide each alternative test case into a normal test case set and an abnormal test case set according to the execution result;
the rule base generating module 640 is configured to generate a normal case rule base and an abnormal case rule base according to the normal test case set and/or the abnormal test case set.
According to the technical scheme of the embodiment of the invention, the standard arithmetic operator in the gold system is used as the correctness verification standard of the chip to be tested, and the normal test case rule base and the abnormal test case rule base which meet the test requirements can be quickly, accurately and automatically generated only by using the roughly constructed original case rule base according to the execution result of the gold system on the test case, so that a large number of normal test cases and abnormal test cases can be generated through the normal test case rule base and the abnormal test case rule base to effectively verify the availability of the chip to be tested. The labor and time cost required by constructing the test case are greatly reduced, and the test efficiency of the chip to be tested is improved.
On the basis of the foregoing embodiments, the rule base generating module 640 may specifically include:
the first rule base generation unit is used for generating a normal case rule base according to the normal test case set and generating an abnormal case rule base according to the abnormal test case set; or the second rule base generating unit is used for generating an abnormal case rule base according to the abnormal test case set and generating a normal case rule base according to the original case rule base and the abnormal case rule base.
On the basis of the foregoing embodiments, the first rule base generating unit or the second rule base generating unit may be specifically configured to:
clustering the abnormal test cases according to the case parameter information of the abnormal test cases to obtain a plurality of cluster clusters; according to the case parameter information of each abnormal test case in each cluster, a linear equation set corresponding to each cluster is constructed, and the linear relation equation comprises: at least one abnormal case rule to be solved; solving each linear equation set corresponding to each cluster to obtain matched abnormal case rules; and generating an abnormal case rule base according to the various abnormal case rules obtained by solving.
On the basis of the above embodiments, the method may further include: a test case generation module for:
after generating the normal case rule base and the abnormal case rule base according to the normal test case set and/or the abnormal test case set, the method further comprises the following steps: and generating at least one normal test case according to the normal case rule base, and/or generating at least one abnormal test case according to the abnormal case rule base.
The device for generating the test case rule provided by the embodiment of the invention can execute the method for generating the test case rule provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
EXAMPLE seven
Fig. 7 is a structural diagram of a chip testing apparatus according to a seventh embodiment of the present invention, and as shown in fig. 7, the apparatus includes: a target test case obtaining module 710, a first execution result obtaining module 720, a second execution result obtaining module 730, and a test verifying module 740. Wherein:
a target test case obtaining module 710, configured to obtain a target test case;
a first execution result obtaining module 720, configured to invoke at least one standard operator provided by the gold system to execute the target test case, and obtain a first execution result of the target test case;
a second execution result obtaining module 730, configured to invoke at least one hardware execution unit included in the chip to be tested to execute the target test case, and obtain a second execution result of the target test case;
the test verification module 740 is configured to determine that the chip to be tested fails the test if the first execution result is inconsistent with the second execution result.
According to the technical scheme of the embodiment of the invention, the standard operation operator in the gold system is used as the correctness verification standard of the test case execution result, the type of the test case is not required to be determined to be normal or abnormal in advance, and whether the chip to be tested passes the verification can be quickly judged only by comparing whether the execution results of the chip to be tested and the gold system on the same target test case are consistent, so that a new mode for testing the chip to be tested is provided, and the test efficiency of the chip to be tested is improved.
The chip testing device provided by the embodiment of the invention can execute the chip testing method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
Example eight
Fig. 8 is a schematic structural diagram of a computer apparatus according to an eighth embodiment of the present invention, as shown in fig. 8, the computer apparatus includes a processor 80, a memory 81, an input device 82, and an output device 83; the number of the processors 80 in the computer device may be one or more, and one processor 80 is taken as an example in fig. 8; the processor 80, the memory 81, the input device 82 and the output device 83 in the computer apparatus may be connected by a bus or other means, and the connection by the bus is exemplified in fig. 8.
The memory 81 is used as a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as a module corresponding to the test case generation method in the embodiment of the present invention, or a module corresponding to the test case rule generation method in the embodiment of the present invention, or a module corresponding to the chip test method in the embodiment of the present invention. The processor 80 executes various functional applications and data processing of the computer device by executing software programs, instructions and modules stored in the memory 81, that is, implements a test case generation method according to any embodiment of the present invention. The method comprises the following steps:
generating a plurality of alternative test cases according to an original case rule base matched with a chip to be tested; calling at least one standard operation operator provided by the gold system to execute each alternative test case and acquiring an execution result of each alternative test case; and according to the execution result, dividing each alternative test case into a normal test case set and an abnormal test case set.
Or, the method for generating the test case rule according to any embodiment of the present invention is implemented. The method comprises the following steps:
generating a plurality of alternative test cases according to an original case rule base matched with a chip to be tested; calling at least one standard operation operator provided by the gold system to execute each alternative test case and acquiring an execution result of each alternative test case; dividing each alternative test case into a normal test case set and an abnormal test case set according to an execution result; and generating a normal case rule base and an abnormal case rule base according to the normal test case set and/or the abnormal test case set.
Alternatively, a chip testing method as any embodiment of the invention is implemented. The method comprises the following steps:
acquiring a target test case; calling at least one standard operation operator provided by the gold system to execute the target test case and acquiring a first execution result of the target test case; calling at least one hardware execution unit included in the chip to be tested to execute the target test case, and acquiring a second execution result of the target test case; and if the first execution result is inconsistent with the second execution result, determining that the chip to be tested does not pass the test.
The memory 81 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 81 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, memory 81 may further include memory located remotely from processor 80, which may be connected to a computer device through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 82 may be used to receive input numeric or character information and generate key signal inputs relating to user settings and function controls of the computer apparatus. The output device 83 may include a display device such as a display screen.
Example nine
An embodiment ninth of the present invention further provides a storage medium containing computer-executable instructions, where the computer-executable instructions are executed by a computer processor to perform a method for generating a test case according to any embodiment of the present invention, where the method includes:
generating a plurality of alternative test cases according to an original case rule base matched with a chip to be tested; calling at least one standard operation operator provided by the gold system to execute each alternative test case and acquiring an execution result of each alternative test case; and according to the execution result, dividing each alternative test case into a normal test case set and an abnormal test case set.
Or, executing a test case rule generating method according to any embodiment of the present invention, where the method includes:
generating a plurality of alternative test cases according to an original case rule base matched with a chip to be tested; calling at least one standard operation operator provided by the gold system to execute each alternative test case and acquiring an execution result of each alternative test case; dividing each alternative test case into a normal test case set and an abnormal test case set according to an execution result; and generating a normal case rule base and an abnormal case rule base according to the normal test case set and/or the abnormal test case set.
Alternatively, a chip testing method according to any embodiment of the invention is performed, the method comprising:
acquiring a target test case; calling at least one standard operation operator provided by the gold system to execute the target test case and acquiring a first execution result of the target test case; calling at least one hardware execution unit included in the chip to be tested to execute the target test case, and acquiring a second execution result of the target test case; and if the first execution result is inconsistent with the second execution result, determining that the chip to be tested does not pass the test.
Of course, the storage medium provided by the embodiment of the present invention contains computer-executable instructions, and the computer-executable instructions are not limited to the above method operations, and may also perform related operations in the method provided by any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (14)
1. A method for generating a test case is characterized by comprising the following steps:
generating a plurality of alternative test cases according to an original case rule base matched with a chip to be tested;
calling at least one standard operator provided by the gold system to execute each alternative test case and obtain an execution result of each alternative test case;
and according to the execution result, dividing each alternative test case into a normal test case set and an abnormal test case set.
2. The method of claim 1, wherein:
the alternative test case comprises at least one operator, and the chip to be tested comprises a hardware execution unit matched with the operator; the operator matches the standard operator provided by the golden system.
3. The method of claim 1, wherein generating the alternative test cases according to the original case rule base matched with the chip to be tested comprises:
acquiring at least one test case template to be filled, wherein the test case template comprises at least one operator to be filled and at least one data item to be filled;
acquiring at least one operator from the original use case rule base as a target operator;
constructing a target data item according to at least one data value range and at least one data type corresponding to the target operational character in the original use case rule base;
and correspondingly filling the target operator and the target data item into each test case module to generate each alternative test case.
4. The method according to claim 1, characterized in that said golden system comprises: TensorFlow, Caffe, Pytrch, or Keras.
5. A method for generating test case rules is characterized by comprising the following steps:
generating a plurality of alternative test cases according to an original case rule base matched with a chip to be tested;
calling at least one standard operator provided by the gold system to execute each alternative test case and obtain an execution result of each alternative test case;
dividing each alternative test case into a normal test case set and an abnormal test case set according to the execution result;
and generating a normal case rule base and an abnormal case rule base according to the normal test case set and/or the abnormal test case set.
6. The method according to claim 5, wherein generating a normal use case rule base and an abnormal use case rule base according to the normal test use case set and/or the abnormal test use case set comprises:
generating a normal case rule base according to the normal test case set, and generating an abnormal case rule base according to the abnormal test case set; or
And generating an abnormal case rule base according to the abnormal test case set, and generating the normal case rule base according to the original case rule base and the abnormal case rule base.
7. The method of claim 6, wherein generating an exception case rule base from the exception test case set comprises:
according to the case parameter information of each abnormal test case, clustering each abnormal test case to obtain a plurality of cluster clusters;
according to the case parameter information of each abnormal test case in each cluster, a linear equation set corresponding to each cluster is constructed, and the linear relation equation comprises: at least one abnormal case rule to be solved;
solving each linear equation set corresponding to each cluster to obtain matched abnormal case rules;
and generating an abnormal case rule base according to each abnormal case rule obtained by solving.
8. The method according to any one of claims 5 to 7, further comprising, after generating a normal use case rule base and an abnormal use case rule base according to the normal test use case set and/or the abnormal test use case set:
and generating at least one normal test case according to the normal case rule base, and/or generating at least one abnormal test case according to the abnormal case rule base.
9. A method for testing a chip, comprising:
acquiring a target test case, wherein the target test case comprises at least one operator;
calling at least one standard operation operator provided by a gold system to execute the target test case and acquiring a first execution result of the target test case;
calling at least one hardware execution unit included in the chip to be tested to execute the target test case, and acquiring a second execution result of the target test case;
and if the first execution result is inconsistent with the second execution result, determining that the chip to be tested does not pass the test.
10. An apparatus for generating a test case, comprising:
the alternative test case generation module is used for generating a plurality of alternative test cases according to the original case rule base matched with the chip to be tested, and the alternative test cases comprise at least one operator;
the execution result acquisition module is used for calling at least one standard operator provided by the gold system to execute each alternative test case and acquiring the execution result of each alternative test case;
and the test case dividing module is used for dividing each alternative test case into a normal test case set and an abnormal test case set according to the execution result.
11. An apparatus for generating test case rules, comprising:
the alternative test case generation module is used for generating a plurality of alternative test cases according to the original case rule base matched with the chip to be tested;
the execution result acquisition module is used for calling at least one standard operator provided by the gold system to execute each alternative test case and acquiring the execution result of each alternative test case;
the test case dividing module is used for dividing each alternative test case into a normal test case set and an abnormal test case set according to the execution result;
and the rule base generation module is used for generating a normal case rule base and an abnormal case rule base according to the normal test case set and/or the abnormal test case set.
12. A chip testing apparatus, comprising:
the target test case acquisition module is used for acquiring a target test case;
the first execution result acquisition module is used for calling at least one standard operator provided by the gold system to execute the target test case and acquiring a first execution result of the target test case;
the second execution result acquisition module is used for calling at least one hardware execution unit included in the chip to be tested to execute the target test case and acquiring a second execution result of the target test case;
and the test verification module is used for determining that the chip to be tested does not pass the test if the first execution result is inconsistent with the second execution result.
13. A computer device, characterized in that the computer device comprises:
one or more processors;
a storage device for storing one or more programs,
when the one or more programs are executed by the one or more processors, the one or more processors implement the test case generation method according to any one of claims 1 to 4, or implement the test case rule generation method according to any one of claims 5 to 8, or implement the chip test method according to claim 9.
14. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the method for generating test cases according to any one of claims 1 to 4, or implements the method for generating test case rules according to any one of claims 5 to 8, or implements the method for testing chips according to claim 9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113032195A (en) * | 2021-03-24 | 2021-06-25 | 上海西井信息科技有限公司 | Chip simulation verification method, system, equipment and storage medium |
| CN115952758A (en) * | 2023-03-10 | 2023-04-11 | 成都登临科技有限公司 | Chip verification method and device, electronic equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113032195A (en) * | 2021-03-24 | 2021-06-25 | 上海西井信息科技有限公司 | Chip simulation verification method, system, equipment and storage medium |
| CN113032195B (en) * | 2021-03-24 | 2023-05-23 | 上海西井信息科技有限公司 | Chip simulation verification method, system, equipment and storage medium |
| CN115952758A (en) * | 2023-03-10 | 2023-04-11 | 成都登临科技有限公司 | Chip verification method and device, electronic equipment and storage medium |
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