CN114756474A - Method and device for generating random vector in CPU verification and electronic equipment - Google Patents
Method and device for generating random vector in CPU verification and electronic equipment Download PDFInfo
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Abstract
A method and a device for generating a random vector in CPU verification and electronic equipment are provided. The invention relates to a method and a device for generating a random vector in verification, wherein the method comprises the following steps: writing a random instruction sequence file, performing test case generator processing and assembling the file, wherein the written random instruction sequence file has a writing format and a semantic format, and the semantic format is also the most core constraint expression method; processing a test case generator to analyze according to the set semantics and generate a specific random instruction; in the assembly file, the output random instruction sequence file is the assembly file, and once the assembly file is generated, simulation verification can be performed according to the requirement. The invention provides a simple and visual high-efficiency verification method which is specially used for random test and has no specific requirements on architecture and the like, and is particularly suitable for the defects of the conventional random verification method.
Description
Technical Field
The present invention relates to the field of functional verification technologies, and in particular, to a method and an apparatus for generating a random vector in CPU verification, and an electronic device.
Background
As the process of integrated circuits becomes more advanced, the design scale and complexity are increased, making functional verification a huge bottleneck in digital chip design.
The current authentication means are mainly divided into directed authentication and random authentication.
The directional verification is that a verifier develops a test vector according to a specific test scenario, and then the test scenario is limited after all, and various complex scenarios are difficult to cover. Random authentication can largely solve this problem.
The random verification is characterized in that: on one hand, a large number of random test vectors can be generated rapidly, and time cost and labor cost are reduced; on the other hand, as the excitation is generated randomly, the combination mode is more diversified, many unexpected results can be generated, and an unexpected bug (problem point) is likely to be found.
The CPU, as a chip with the most complexity in design, is a great challenge to the verification work, and therefore, random verification has an indispensable important position and role in CPU verification. Based on this, there is a need to provide a simple, versatile and efficient random vector generation method.
The technical scheme in the prior art is as follows:
the verification case (test case) is divided into a directional case and a random case, the directional case is completed by handwriting of a verifier and is used for verifying a specific function point, and the random case is completed by using a constraint grammar in System Verilog (a language) in the current verification.
The prior art has the following disadvantages:
random case is completed by using constraint grammar in System Verilog in the current verification, and possible existing values of variables are difficult to distinguish along with the increase of constraints, so that the scale enlargement of the verification process is not facilitated, the logic is complicated, and the universality is poor.
Disclosure of Invention
Problems to be solved by the invention
The invention mainly aims to provide a method and a device for generating a random vector in CPU verification, which are used for solving the problems of the prior art that the scale of a verification process is not easy to expand, the logic is complicated, the universality is poor and the like.
Means for solving the problems
In order to achieve the above object, the present invention provides a method for generating a random vector in CPU verification, comprising the steps of:
step S1: writing a random instruction sequence file, wherein the random instruction sequence file has a writing format and a semantic format;
step S2: processing a test case generator, wherein the tool is made by computer assembly language and used for analyzing according to the set semantics to generate a specific random instruction;
step S3: and assembling the file, wherein the output random instruction sequence file is the assembly file, and once the assembly file is generated, simulation verification is performed as required.
Preferably, the step S1 specifically includes the following steps:
step S11: creating and opening a blank file;
step S12: completing the definition of the predefined type;
step S13: writing code using the defined variables and the direct application type;
step S14: and (5) storing the file.
Preferably, the step S2 specifically includes the following steps:
step S21: processing the file by a test case generator tool;
step S22: the number of output assembly files is specified.
Preferably, the step S3 specifically includes the following steps:
step S31: after the processing is finished, the required number of randomly finished assembly files are generated;
step S32: the specific file suffix starts at 0 and increases until the required number minus 1.
Preferably, the semantic formats in step S1 are divided into two types: predefined type and direct application type.
Preferably, the predefined type includes several sub-types.
Preferably, the direct application type includes several subtypes.
In order to achieve the above object, the present invention provides a device for generating a random vector in CPU authentication, comprising:
the writing random instruction sequence file module is used for writing a random instruction sequence and has a writing format and a semantic format;
the test case generator processing module is used for carrying out test case generator processing, the tool is made by computer assembly language and used for analyzing according to set semantics and generating specific random instructions;
and the assembly file module is used for assembling the file, wherein the output random instruction sequence file is the assembly file, and once the assembly file is generated, simulation verification can be carried out as required.
In order to achieve the above object, the present invention provides an electronic device, a memory of the electronic device and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.
In order to achieve the above object, the present invention provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of any of the above methods.
ADVANTAGEOUS EFFECTS OF INVENTION
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a simple and visual high-efficiency verification method which is specially used for random test and has no specific requirements on architecture and the like, and is particularly suitable for the defects of the conventional random verification method.
The invention can carry out randomness aiming at the instructions of any architecture, has universality and intuitive constraint conditions, and can generate random instructions of any scene only by providing random instruction files of specific formats and analyzing the random instruction files by a generator.
Drawings
FIG. 1 is a flow chart of a method for generating random vectors in CPU authentication according to the present invention;
FIG. 2 is a block diagram of an apparatus for generating random vectors in CPU authentication according to the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a program product for implementing a random vector generation method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention. It should be further emphasized here that the following embodiments provide preferred embodiments, and that the various aspects (embodiments) may be used in combination or cooperation with each other.
As shown in fig. 1, a flow chart of a method for generating a random vector in CPU verification is shown, and the method for generating a random vector in CPU verification of the present invention includes the following steps:
step S1: the method is characterized in that a File (File) with a writing format and a semantic format is written in a random instruction sequence RIS (RIS is short for random instruction sequence), wherein the writing format is described in the following description, and the semantic format is also a most core constraint expression method.
The step S1 specifically includes the following steps:
step S11: creating and opening a blank file;
step S12: completing the definition of the predefined type, wherein the specific predefined type is explained in the following;
step S13: writing code using the defined variables and the direct application type;
step S14: and (5) saving the file.
Step S2: generator (test case generator) processing is carried out, and the tool is made by computer assembly language (python) and used for analyzing according to the set semantics and generating specific random instructions;
the step S2 specifically includes the following steps:
step S21: the test case generator tool processes the file written in the step S1;
step S22: the number of output assembly files is specified, such as 10,100,1000,10000.
Step S3: assembly file (ASM file): the output random instruction sequence file is an assembly file, and once the assembly file is generated, simulation verification can be performed as required.
The step S3 specifically includes the following steps:
step S31: after the processing is finished, the required number of randomly finished assembly files are generated;
step S32: the specific file suffix starts at 0 and increases until the required number minus 1.
Hereinafter, the semantic format of the random instruction sequence File (RIS File) in the above steps and the specific processing thereof by the semantic parser generator will be described in detail.
The semantic format in step S1 is divided into two types: predefined types and direct application types, each of which is further sub-classified under several sub-types.
First, the predefined type is described in detail, and the characteristics of the predefined type are as follows: define then apply
1.1' predefined set
1.1.1define rdm _ set xxx (xxx stands for any name, user-defined): all possible alternatives are predefined in xxx, and any one result is selected randomly
The realization method comprises the following steps:
the generator written by python analyzes, and every time $ xxx is encountered, the result of random function from the alternative items is used as index to select the corresponding numerical value.
Example of definition:
`define rdm_set odd_reg
item:[x1，x3，x5，x7，x9，x11，x13，x15，x17，x19，x21，x23，x25，x27，x29，x31]
`enddef
application example:
li$odd_reg,0x10
then the $ odd _ reg random result may be any value in the set, such as li x9,0x 10 as the final result
Rdmc means random cycle by cycle, with emphasis on the order of occurrence. The repeated value can not occur before the same circle is not completed randomly;
the implementation method comprises the following steps:
analyzing through a generator written by python, randomly obtaining a numerical value from the alternative items by using a random function every time when $ xxx is encountered, confirming whether the numerical value does not appear in the current round, and returning if the numerical value meets the requirement; otherwise, continuing to be random until the requirement is met.
Example of definition:
`define rdmc_set odd_reg
item：[x1，x3，x5，x7，x9，x11，x13，x15，x17，x19，x21，x23，x25，x27，x29，x31]
`enddef
application example:
li$odd_reg,0x10
li$odd_reg,0x18
it indicates that the $ odd _ reg for the two instructions in the same round may not be the same until the values in the $ odd _ reg set have not been randomized, such as li x9,0x 10 and li x11,0x 18, but li x9,0x 10 and li x9,0x 18 in the same round.
1.2. Predefined unique set (exclusive, once only set): unique means that the number once randomly coming out in each entry macro does not change, and it is emphasized that the stability of the random number in the range controlled by the root macro needs to be used in the macro (display macro and implicit macro { }).
1.2.1.`define rdm_unique xxx:
The implementation method comprises the following steps:
through parsing by generator written by python, when $ xxx is encountered, the macro is directly marked as the root macro (meaning the macro entered for the first time in the program, which can continue to nest all levels of macro, like tree structures, so called root macro), the unique variable exists in the root macro, then any alternative is randomly selected, and when $ xxx is encountered again at the root macro level to which the macro belongs and all levels below the root macro level, the value which is randomly selected is directly replaced until the root macro is skipped.
Example of definition:
`define rdm_unique odd_reg_unique
item：[x1，x3，x5，x7，x9，x11，x13，x15，x17，x19，x21，x23，x25，x27，x29，x31]
`enddef
`define macro macro_ld_sd
ld$odd_reg_unique,0x0(0x10)
sd$odd_reg_unique,0x8(0x10)
`enddef
application example:
$macro_ld_sd
$macro_ld_sd
the values that $ macro _ ld _ sd first comes out randomly may be ld x9,0x0(0x10) and sd x9,0x8(0x10), but not ld x9,0x0(0x10) and sd x11,0x8(0x10),
similarly, the second random value for $ macro _ ld _ sd may be ld x11,0x0(0x10) and sd x11,0x8(0x10), but not ld x9,0x0(0x10) and sd x11,0x8(0x10),
1.2.2. "define rdmc _ unique xxx. rdmc has the meaning given above and unique has also been given above, as a combination of the two
The implementation method comprises the following steps:
similar to 1.2.1, but in the random value, whether the random value does not appear in the current round is confirmed, if the random value meets the requirement, the random value is returned, otherwise, the random value is continued until the random value meets the requirement.
Example of definition:
`define rdmc_unique odd_reg_unique
item:[x1，x3，x5，x7，x9，x11，x13，x15，x17，x19，x21，x23，x25，x27，x29，x31]
`enddef
`define macro macro_ld_sd
ld$odd_reg_unique,0x0(0x10)
sd$odd_reg_unique,0x8(0x10)
`enddef
application example:
$macro_ld_sd
$macro_ld_sd
then the values that $ macro _ ld _ sd was randomized for the first time could be ld x9,0x0(0x10) and sd x9,0x8(0x10)
Likewise, the second random values of $ macro _ ld _ sd are no longer possible ld x9,0x0(0x10) and sd x9,0x8(0x10)
1.3. Pre-defined macro: the instruction order is predefined and may include any of the semantics mentioned herein, although any random and nestable macro may be added to the macro.
1.3.1. "define macro (macro) xxx:
the realization method comprises the following steps:
analyzing through a generator written by python, analyzing the statements in the generator each time when $ xxx is met, if the statements are of a set type, replacing the statements according to the method just mentioned, if the statements are also of a macro type, entering the macro, then analyzing the statements in the generator, and entering the last stage and then returning, thus completing the analysis. Thus supporting arbitrary levels of macro nesting.
Example of definition:
`define macro macro_ld_sd
ld x10,0x0(0x10)
sd x10,0x8(0x10)
`enddef
application example:
$macro_ld_sd
generator treatment gave ld x10,0x0(0x10) and sd x10,0x8(0x10),
2. direct application type:
2.1. direct application of random repetition times
2.1.1.$ rdm _ repeat _ x _ y (repeat means): arbitrary values for random [ x, y ] intervals for an instruction or sequence of instructions, comprising x, y times
The realization method comprises the following steps:
the generator written by python is used for analyzing, and random operation is carried out in x and y every time $ xxx is met, so that x and y can easily acquire numerical values even if the numerical value range is large, and the analysis efficiency is not influenced. The following [ x, y ] is also the same method, and no specific description is given.
Example (c): $ rdm _ repeat _1_3, after being processed by the generator, the random result at each time can be any value of 1, 2and 3,
2.1.2.$ rdmc _ repeat _ x _ y: the difference from 2.1.1 is that the random numbers in the [ x, y ] interval are not likely to be repeated until all the numbers are not contained, i.e. the random first turn and then the random second turn are performed in sequence, and the occurrence sequence is also emphasized.
The implementation method comprises the following steps:
similar to 2.1.1, but in the case of random values, whether the random values do not appear in the current round is confirmed, if the random values meet the requirements, the random values are returned, and otherwise, the random values are continued until the random values meet the requirements.
Example (c): the result of random times after generator processing for rdmc _ repeat _1_3 may be 1, 3, 2, 3, but not 2, 1, 2, 3
2.2. Direct application of random decimal immediate
2.2.1.$ rdm _ imm _ dec _ x _ y (imm means immediate, dec means decimal) are related
2.2.1.1.$ rdm _ imm _ dec _ x _ y any number within random [ x, y ] closed interval, x, y being in decimal format
The implementation method comprises the following steps:
analyzing by a generator written by python, and performing random operation in decimal in [ x, y ] every time $ xxx is met.
Example (c): $ rdm _ imm _ dec _1_3, after generator processing, the random result at each time may be any value of 1, 2, 3
2.2.1.2.$ rdm _ imm _ dec _ x _ y _ not _ a [ _ b [ … ] ] (not meaning here) any number within the closed interval of [ x, y ] randomly except a, [ b [ … ] ]. x, y, a are in decimal format, and if there is _ b, then b is unlikely to occur
The implementation method comprises the following steps:
similar to 2.2.1.1, except that at random values, non-excluded items are confirmed, if the requirements are met, the return is made, otherwise, the random is continued until the requirements are met.
Example (c): $ rdm _ imm _ dec _1_3_ not _2, after generator processing, the random result at each time may be any value of 1, 3, but certainly may not be 2; $ rdm _ imm _ dec _1_3_ not _2_3, after generator processing, the random result at each time may only be 1
2.2.1.3.$ rdm _ imm _ dec _ x _ y _ tail _ z (tail: meaning tail) random number in the closed interval of [ x, y ], x, y being in decimal format, followed by z tail
The implementation method comprises the following steps:
similar to 2.2.1.1, except that in the case of random values, a tail is added.
Example (c): $ rdm _ imm _ dec _1_3_ tail _00, after generator processing, the random result may be any value of 100, 200, 300
2.2.1.4.$ rdm _ imm _ dec _ x _ y _ not _ a [ _ b [ … ] ] _ tail _ z random number in a closed interval of [ x, y ] except a, [ b [ … ] ], x, y, a being in decimal format, b being unlikely to occur if b is present, and then adding a tail z to the random number
The realization method comprises the following steps:
similar to 2.2.1.2 and 2.2.1.3, the characteristics of the two are combined, and the two items are not excluded, but are added with tailors.
Example (a): $ rdm _ imm _ dec _1_3_ not _2_ tail _00, after generator processing, the result of each random may be any value of 100, 300, but not 200
2.2.2.$ rdmc _ imm _ dec _ x _ y correlation
2.2.2.1.$ rdmc _ imm _ dec _ x _ y decimal number in closed interval of circled [ x, y ]
The implementation method comprises the following steps:
similar to 2.2.1.1, except that in the case of random values, whether the random values do not appear in the current round is determined, if the random values meet the requirements, the random values are returned, otherwise, the random values are continued until the requirements are met.
Example (a): the result of random times after generator processing for rdmc _ imm _ dec _1_3 may be 1, 3, 2, 3, but not 2, 1, 2, 3
2.2.2.2.$ rdmc _ imm _ dec _ x _ y _ not _ a [ _ b [ … ] ]. decimal numbers in a closed interval of [ x, y ] are circled except a [, b [ … ] ], etc. ]
The implementation method comprises the following steps:
similar to 2.2.1.2, but in the case of random values, whether the random values do not appear in the current round is confirmed, if the random values meet the requirements, the random values are returned, otherwise, the random values continue to be obtained until the random values meet the requirements.
The realization method comprises the following steps:
similar to the methods of 2.2.2.1.3.1.2, 2.2.2.1.3.1.3,
example (c): $ rdmc _ imm _ dec _1_3_ not _ 2. after generator processing, the random result may be 1, 3, 3, but not 1, 1, 3
2.2.2.3.$ rdmc _ imm _ dec _ x _ y _ tail _ z decimal numbers in a closed interval of [ x, y ] circled, followed by a z-tail
The implementation method comprises the following steps:
similar to 2.2.1.3, except that in the case of random values, whether the random values do not appear in the current round is determined, if the random values meet the requirements, the random values are returned, otherwise, the random values are continued until the requirements are met.
Example (c): $ rdmc _ imm _ dec _1_3_ tail _ 00. after being processed by a generator, the random result may be 100, 300, 200, but may not be 100,100, 200
2.2.2.4.$ rdmc _ imm _ dec _ x _ y _ not _ a [ _ b [ … ] ] _ tail _ z, which circles through the decimal numbers in the closed interval of [ x, y ] except a, b [ … ] ] etc., and then tailors the randomly derived numbers with a suffix z
The realization method comprises the following steps:
similar to 2.2.1.4, except that in the case of random values, whether the random values do not appear in the current round is determined, if the random values meet the requirements, the random values are returned, otherwise, the random values are continued until the requirements are met.
Example (a): $ rdmc _ imm _ dec _1_3_ not _2_ tail _ 00. after generator processing, the random result may be 100, 300, 300, but not 100,100, 300
2.3. Direct application of unique decimal immediate, the description of unique is the same as in 1.2.1
2.3.1.$ rdm _ unique _ imm _ dec _ x _ y correlation
2.3.1.1.$ rdm _ unique _ imm _ dec _ x _ y-consistent with 2.2.1.1 except for the 2.3 statement about unique
2.3.1.2.$ rdm _ unique _ imm _ dec _ x _ y _ not _ a [ _ b [ … ] ], except for the 2.3 statement about unique, it corresponds to 2.2.1.2
2.3.1.3.$ rdm _ unique _ imm _ dec _ x _ y _ tail _ z-consistent with 2.2.1.3 except for the description of unique 2.3
2.3.1.4.$ rdm _ unique _ imm _ dec _ x _ y _ not _ a [ _ b [ … ] ] _ tail _ z-consistent with 2.2.1.4 except for the description of unique 2.3
2.3.2.$ rdmc _ unique _ imm _ dec _ x _ y correlation
2.3.2.1 rdmc _ unique _ imm _ dec _ x _ y consistent with 2.2.2.1 except for the description of unique 2.3
2.3.2.2.$ rdmc _ unique _ imm _ dec _ x _ y _ not _ a [ _ b [ … ] ] -consistent with 2.2.2.2 except for the description of unique 2.3
2.3.2.3.$ rdmc _ unique _ imm _ dec _ x _ y _ tail _ z-consistent with 2.2.2.3 except for the description of unique 2.3
2.3.2.4.$ rdmc _ unique _ imm _ dec _ x _ y _ not _ a [ _ b [ … ] ] _ tail _ z-consistent with 2.2.2.4 except for the description of unique 2.3
2.4. The random hexadecimal immediate number is directly applied, compared with 2.2, the hexadecimal immediate number is replaced by the random hexadecimal immediate number,
2.4.1.$ rdm _ imm _ hex _ x _ y (hex: hexadecimal) correlation
2.4.1.1.$ rdm _ imm _ hex _ x _ y, any number in random [ x, y ] closed interval, x, y being in hexadecimal format
The implementation method comprises the following steps:
this is the same as 2.2.1.1 except that the resolution is carried out according to 16-ary system.
Example (c): $ rdm _ imm _ hex _19_1b, after generator processing, the random result at each time may be any value of 19, 1a, 1b
2.4.1.2.$ rdm _ imm _ hex _ x _ y _ not _ a [ _ b [ … ] ], random number in the closed interval of [ x, y ] except a. x, y, a are in hexadecimal format, and if there is _ b, then b is unlikely to occur
The implementation method comprises the following steps:
this is the same as 2.2.1.2, except that the resolution is carried out according to the 16-ary system.
Example (c): $ rdm _ imm _ hex _19_1b _ not _1a, after generator processing, the result of each random can be any value of 19, 1b, but certainly can not be 1 a; $ rdm _ imm _ hex _19_1b _ not _1a _1b, after being processed by the generator, the random result at each time is only 19
2.4.1.3.$ rdm _ imm _ hex _ x _ y _ tail _ z random [ x, y ] any number within the closed interval, x, y being in hexadecimal format, followed by a z-suffix
The realization method comprises the following steps:
this is the same as 2.2.1.3, except that the resolution is carried out according to the 16-ary system.
Example (c): $ rdm _ imm _ hex _19_1b _ tail _00, after being processed by the generator, the random result at each time can be any value of 1900, 1a00 and 1b00
2.4.1.4.$ rdm _ imm _ hex _ x _ y _ not _ a [ _ b [ … ] ] _ tail _ z random number in the closed interval of [ x, y ] except a, x, y, a is in hexadecimal format, if b exists, b is not possible, and then the random number is added with tail z
The implementation method comprises the following steps:
this is the same as 2.2.1.4 except that the resolution is carried out according to 16-ary system.
Example (c): $ rdm _ imm _ hex _19_1b _ not _1a _ tail _00, after being processed by the generator, the random result at each time can be any value of 1900 and 1b00
2.4.2.$ rdmc _ imm _ hex _ x _ y correlation
2.4.2.1.$ rdmc _ imm _ hex _ x _ y. implementation method of hexadecimal number in closed interval of [ x, y ] according to cycle:
this is the same as 2.2.2.1 except that the resolution is carried out according to 16-ary.
Example (c): the result of this multiple random operation of the generator is 19, 1b, 1a, 1b, and not 1a, 19, 1a, 1b
2.4.2.2.$ rdmc _ imm _ hex _ x _ y _ not _ a [ _ b [ … ] ], cycling hexadecimal numbers within a closed interval of [ x, y ] except a [, b [ … ] ], and the like
The implementation method comprises the following steps:
this is the same as 2.2.2.2, except that the resolution is carried out according to 16-ary system.
Example (c): $ rdmc _ imm _ hex _19_1b _ not _1 a. after generator processing, the random result may be 19, 1b, 1b, but not 19, 19, 1b
2.4.2.3.$ rdmc _ imm _ hex _ x _ y _ tail _ z hexadecimal numbers in the closed interval of the loop [ x, y ], followed by a z-tail
The implementation method comprises the following steps:
this is consistent with 2.2.2.3, except that the resolution is performed according to 16-ary.
Example (c): $ rdmc _ imm _ hex _19_1b _ tail _ 00. after generator processing, the random result may be 1900, 1b00, 1a00, but not 1900, 1900, 1a00
2.4.2.4.$ rdmc _ imm _ hex _ x _ y _ not _ a [ _ b [ … ] ] _ tail _ z-cycling hexadecimal numbers in a closed interval of [ x, y ] except a [, b [ … ] ] etc., and then appending a tail z to the randomly derived number
The implementation method comprises the following steps:
this is consistent with 2.2.2.4, except that the resolution is performed according to 16-ary.
Example (a): $ rdmc _ imm _ hex _19_1b _ not _1a _ tail _ 00. after generator processing, the random result may be 1900, 1b00, 1b00, but not 1900, 1900, 1b00
2.5. A random unique hexadecimal immediate is applied directly, similar to 2.3, except that the decimal is changed to hexadecimal.
2.5.1.$ rdm _ unique _ imm _ hex _ x _ y correlation
2.5.1.1.$ rdm _ unique _ imm _ hex _ x _ y-consistent with 2.4.1.1 except for 2.5 hexadecimal notation
2.5.1.2.$ rdm _ unique _ imm _ hex _ x _ y _ not _ a [ _ b [ … ] ], consistent with 2.4.1.2, except for the 2.5 hexadecimal notation
2.5.1.3.$ rdm _ unique _ imm _ hex _ x _ y _ tail _ z-consistent with 2.4.1.3, except for the 2.5 hexadecimal notation
2.5.1.4.$ rdm _ unique _ imm _ hex _ x _ y _ not _ a [ _ b [ … ] ] _ tail _ z-consistent with 2.4.1.4 except for the 2.5 hexadecimal description
2.5.2.$ rdmc _ unique _ imm _ hex _ x _ y correlation
2.5.2.1.$ rdmc _ unique _ imm _ hex _ x _ y-except for the 2.5 hexadecimal notation, the other symbols are identical to 2.4.2.1
2.5.2.2.$ rdmc _ unique _ imm _ hex _ x _ y _ not _ a [ _ b [ … ] ] -consistent with 2.4.2.2 except for the 2.5 hexadecimal notation
2.5.2.3.$ rdmc _ unique _ imm _ hex _ x _ y _ tail _ z-consistent with 2.4.2.3 except for the 2.5 hexadecimal description
2.5.2.4.$ rdmc _ unique _ imm _ hex _ x _ y _ not _ a [ _ b [ … ] ] _ tail _ z-consistent with 2.4.2.4 except for the 2.5 hexadecimal description
2.6. Implicit macros { }: in contrast to the use of display macros, implicit macros can be used directly without the need for predefining
The implementation method comprises the following steps:
and analyzing through a generator written by python, instantiating a display macro by the equivalent according to the line number of the equivalent when encountering the implicit macro, and then processing according to the method for displaying the macro.
Example (a):
2.7 $ label _ $ range _ num _ x _ y for building a layer
The implementation method comprises the following steps:
and analyzing by a generator written by python, and setting a value once according to the sequence from x to y each time label _ $ range _ num _ x _ y is met.
Example (a):
$rdm_repeat_3_3label_$range_num_1_3
a result label _1 is obtained; label _2and label _3
As shown in fig. 2, the present invention further provides a device for generating a random vector in CPU authentication, where the device 1 for generating a random vector in CPU authentication includes:
the writing random command sequence file module 11 is used for writing a random command sequence, and has a writing format and a semantic format, wherein the writing format is described later, and the semantic format is also a most core constraint expression method.
The module 11 for writing a random command sequence file comprises: creating and opening a blank file; completing the definition of the predefined type, wherein the specific predefined type is explained in the following; writing code using the defined variables and the direct application type; and (5) saving the file.
A test case generator processing module 12, configured to perform generator processing, where the tool is created by computer assembly language (python), and is configured to perform parsing according to a predetermined semantic meaning to generate a specific random instruction;
the test case generator processing module 12 specifically includes: the test case generator tool processes the file written in the step S1; the number of output assembly files is specified, such as 10,100,1000,10000.
The assembly file module 13 specifically includes: after the processing is finished, the required number of randomly finished assembly files are generated; the specific file suffix starts at 0 and increases until the required number minus 1.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
by means of the defined syntax, it can be seen that,
1. the method is not dependent on any particular architecture, i.e. the method is applicable to any architecture including riscv, x86, arm, etc.
2. The method has clear semantics, can directly distinguish all possible results, and is more intuitive relative to System Verilog type constraints.
3. The method is simple to operate, efficient and practical, and can create instruction stream combinations of any complex instructions (such as exception handling, mode switching and the like) through various rdm (random) combinations.
4. For the same ris file, multiple case files can be generated by calling generator for multiple times and used for verification work
Referring to fig. 3, an embodiment of the present application further provides an electronic device 200, where the electronic device 200 includes at least one memory 210, at least one processor 220, and a bus 230 connecting different platform systems.
The memory 210 may include readable media in the form of volatile memory, such as Random Access Memory (RAM)211 and/or cache memory 212, and may further include Read Only Memory (ROM) 213.
The memory 210 further stores a computer program, and the computer program can be executed by the processor 220, so that the processor 220 executes the steps of the method for generating a random vector in the embodiment of the present application, and a specific implementation manner of the method is consistent with the implementation manner and the achieved technical effect described in the embodiment of the method for generating a random vector, and details of some of the implementation manner are not repeated.
Accordingly, the processor 220 can execute the computer programs described above, and can execute the utility 214.
The electronic device 200 may also communicate with one or more external devices 240, such as a keyboard, pointing device, bluetooth device, etc., and may also communicate with one or more devices capable of interacting with the electronic device 200, and/or with any devices (e.g., routers, modems, etc.) that enable the electronic device 200 to communicate with one or more other computing devices. Such communication may be through input-output interface 250. Also, the electronic device 200 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the Internet) via the network adapter 260. The network adapter 260 may communicate with other modules of the electronic device 200 via the bus 230. It should be appreciated that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the electronic device 200, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage platforms, to name a few.
The embodiments of the present application further provide a computer-readable storage medium, where the computer-readable storage medium is used to store a computer program, and when the computer program is executed, the steps of the method for generating a random vector in the embodiments of the present application are implemented, and a specific implementation manner of the method is consistent with the implementation manner and the achieved technical effect described in the embodiments of the method for generating a random vector, and some contents are not described again.
Fig. 4 shows a program product 300 for implementing the random vector generation method, which may be a portable compact disc read only memory (CD-ROM) and includes program codes, and may be executed on a terminal device, such as a personal computer. However, the program product 300 of the present invention is not so limited, and in this application, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. Program product 300 may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
A computer readable storage medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable storage medium may also be any readable medium that can communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing. Program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the C programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In situations involving remote computing devices, the remote computing devices may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to external computing devices (e.g., through the internet using an internet service provider).
While the present application is described in terms of various aspects, including exemplary embodiments, the principles of the invention should not be limited to the disclosed embodiments, but are also intended to cover various modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for generating random vectors in CPU verification is characterized by comprising the following steps:
step S1: writing a random instruction sequence file, wherein the random instruction sequence file has a writing format and a semantic format;
step S2: processing a test case generator, wherein the tool is made by computer assembly language and used for analyzing according to the set semantics to generate a specific random instruction;
step S3: assembling the file, wherein the output random instruction sequence file is the assembling file, and once the assembling file is generated, simulation verification is carried out as required.
2. The method for generating a random vector in CPU authentication according to claim 1,
the step S1 specifically includes the following steps:
step S11: creating and opening a blank file;
step S12: completing the definition of the predefined type;
step S13: writing code using the defined variables and the direct application type;
step S14: and (5) saving the file.
3. The method for generating a random vector in CPU authentication according to claim 1,
the step S2 specifically includes the following steps:
step S21: processing the file by a test case generator tool;
step S22: the number of output assembly files is specified.
4. The method for generating a random vector in CPU authentication according to claim 1,
the step S3 specifically includes the following steps:
step S31: after the processing is finished, the required number of randomly finished assembly files are generated;
step S32: the specific file suffix starts at 0 and increases until the required number minus 1.
5. The method for generating a random vector in CPU authentication according to claim 1,
the semantic format in step S1 is divided into two types: predefined and direct application.
6. The method for generating a random vector in CPU authentication according to claim 5,
the predefined type includes several sub-types.
7. The method for generating a random vector in CPU authentication according to claim 5,
the direct application type includes several subtypes.
8. An apparatus for generating a random vector in CPU authentication, comprising:
the writing random instruction sequence file module is used for writing a random instruction sequence and has a writing format and a semantic format;
the test case generator processing module is used for carrying out test case generator processing, the tool is made by computer assembly language and used for analyzing according to set semantics and generating specific random instructions;
and the assembly file module is used for assembling the file, wherein the output random instruction sequence file is the assembly file, and once the assembly file is generated, simulation verification can be carried out as required.
9. An electronic device, characterized by an electronic device memory and a processor, the memory storing a computer program which, when executed by the processor, carries out the steps of the method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1-7.
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