CN114036064A - Method and device for generating assembly code file of test case and electronic equipment - Google Patents

Method and device for generating assembly code file of test case and electronic equipment Download PDF

Info

Publication number
CN114036064A
CN114036064A CN202111445893.7A CN202111445893A CN114036064A CN 114036064 A CN114036064 A CN 114036064A CN 202111445893 A CN202111445893 A CN 202111445893A CN 114036064 A CN114036064 A CN 114036064A
Authority
CN
China
Prior art keywords
random value
instruction
target instruction
test point
target
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111445893.7A
Other languages
Chinese (zh)
Inventor
席鹏飞
李健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Eswin Computing Technology Co Ltd
Original Assignee
Beijing Eswin Computing Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Eswin Computing Technology Co Ltd filed Critical Beijing Eswin Computing Technology Co Ltd
Priority to CN202111445893.7A priority Critical patent/CN114036064A/en
Publication of CN114036064A publication Critical patent/CN114036064A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3684—Test management for test design, e.g. generating new test cases
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3688—Test management for test execution, e.g. scheduling of test suites

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

The application provides a method and a device for generating an assembly code file of a test case and electronic equipment, and relates to the technical field of computers. The method comprises the following steps: determining at least one target instruction meeting preset limiting conditions from the instruction set test point file, and reading test point information of the at least one target instruction; acquiring a random value generation condition corresponding to at least one target instruction, generating at least one random value corresponding to at least one target instruction according to the random value generation condition corresponding to at least one target instruction, and generating an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of at least one target instruction and at least one random value. The embodiment of the application realizes coverage of the critical scene, improves the coverage rate of the critical scene, and can comprehensively verify the instruction set information so as to discover potential abnormality.

Description

Method and device for generating assembly code file of test case and electronic equipment
Technical Field
The application relates to the technical field of computers, in particular to a method and a device for generating an assembly code file of a test case and electronic equipment.
Background
RISCV (read as "RISC-FIVE") is an open Instruction Set Architecture (ISA) built based on the principles of Reduced Instruction Set Computing (RISC), V denoted as a fifth generation RISC (reduced instruction set computer), RISC, which is meant to contain a small number of instructions that are very frequently used and provide some necessary instructions to support the operating system and high level languages. In a computer developed according to this principle, the RISC-V instruction set is an open Instruction Set Architecture (ISA) established based on the Reduced Instruction Set Computing (RISC) principle, and the RISCV is a fully new instruction set established based on the continuous development and maturity of the instruction set.
The existing RISCV instruction set test scheme is to edit an assembly code file of a test case corresponding to an RISCV instruction set test point file by manually selecting a critical value, a typical value and a small amount of user-defined values as input source operands, and further edit the assembly code of the test case corresponding to the source operands, thereby testing a common functional scene, for example, performing integer addition and subtraction through the RISCV instruction set, specifically, when performing logic and operation, selecting "64 'h ffff _ ffff _ ffff _ ffff and 64' h0000_0000_ 0000" as the critical values, selecting "64 'h 5555_5555_5555_5555 and 64' h AAAA _ AAAA" as the typical values, selecting the critical values, the typical values and the user-defined values to construct a test point, and further editing the assembly code of the test case corresponding to the test point of the target instruction, to verify each functional scenario.
However, for various instructions, there is 64-bit or 32-bit random space per input source operand, which means 264Or 232Individual values, e.g. 2 for the logical AND operation described above64*264Or 232*232The combination is characterized in that the combination is basically incapable of being completely covered, most combination scenes of source operands are equivalent, the instruction test points are constructed by selecting the critical values, the typical values and a small number of custom values, limited critical scenes can be verified, all critical scenes cannot be covered, for example, the coverage rate of the critical scenes is insufficient, various test points of an instruction set cannot be comprehensively verified, and some exceptions are ignored.
Disclosure of Invention
The embodiment provides a method, a device, an electronic device, a computer-readable storage medium and a computer program product for generating an assembly code file of a test case, which are used for solving the technical problem of insufficient coverage rate of a critical scene.
According to an aspect of the embodiments of the present application, there is provided a method for generating an assembly code file of a test case, the method including:
determining at least one target instruction meeting preset limiting conditions from the instruction set test point file, and reading test point information of the at least one target instruction; the instruction set test point file comprises at least one instruction and test point information of the at least one instruction;
acquiring a random value generation condition corresponding to at least one target instruction, and generating at least one random value corresponding to at least one target instruction according to the random value generation condition corresponding to at least one target instruction;
and generating an assembly code file of the test case corresponding to the test point file of the instruction set according to the test point information of the at least one target instruction and the at least one random value.
In one possible implementation, the test point information includes at least one source operand and a value corresponding to the source operand;
generating at least one random value corresponding to at least one target instruction according to a random value generation condition corresponding to at least one target instruction, including:
obtaining a value of at least one source operand of at least one target instruction, and determining a value range of the source operand according to the value of the source operand;
determining the value range of a random value according to the value range of the source operand;
and generating at least one random value corresponding to at least one target instruction according to the random value generation condition and the value range of the random value.
In one possible implementation manner, generating at least one random value corresponding to at least the target instruction according to the random value generation condition and the value range of the random value includes:
if the random value generation condition comprises a seed setting condition, acquiring a seed set for at least one target instruction, and generating at least one random value corresponding to at least one target instruction according to the value range of the random value and the seed set for at least one target instruction.
In one possible implementation manner, generating at least one random value corresponding to at least the target instruction according to the random value generation condition and the value range of the random value includes:
and if the random value generation condition comprises a set iteration frequency condition, acquiring the iteration frequency of the random value set for the at least one target instruction, and determining the at least one random value corresponding to the at least one target instruction according to the value range of the random value and the iteration frequency of the random value.
In one possible implementation manner, generating an assembly code file of a test case corresponding to an instruction set test point file according to test point information of at least one target instruction and at least one random value includes:
generating assembly codes of test cases corresponding to the target instructions according to the test point information of the target instructions and at least one random value of the target instructions;
and combining the test case assembly codes corresponding to the target instructions according to a preset rule to generate the assembly codes of the test cases corresponding to the instruction files.
In one possible implementation manner, the test point information further includes an instruction unique identifier; the values of the source operands comprise typical values, critical values and user-defined values;
generating a test case assembly code corresponding to each target instruction according to the test point information of each target instruction and at least one random value of each target instruction, wherein the test case assembly code comprises the following steps:
taking at least one of a typical value, a critical value, a user-defined value and a random value as an input value of a source operand of a target instruction;
and calling a test case assembly template corresponding to each target instruction, filling the instruction unique identifier of each target instruction and the input value of the source operand into the corresponding test case assembly template, and generating the assembly code of the test case corresponding to each target instruction.
In one possible implementation manner, the test case assembly template includes a unique identifier of the target instruction and a placeholder corresponding to an input value of the source operand.
According to another aspect of the embodiments of the present application, there is provided in one possible implementation manner a method including:
the target instruction acquisition module is used for determining at least one target instruction meeting a preset limiting condition from the instruction set test point file and reading test point information of the at least one target instruction; the instruction set test point file comprises at least one instruction and test point information of the at least one instruction;
the random value generation module is used for acquiring a random value generation condition corresponding to at least one target instruction and generating at least one random value corresponding to at least one target instruction according to the random value generation condition corresponding to at least one target instruction;
and the assembly code generating module is used for generating an assembly code file of the test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value.
According to another aspect of embodiments of the present application, there is provided an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method as provided in the first aspect when executing the program.
According to a further aspect of embodiments of the present application, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method as provided by the first aspect.
According to yet another aspect of embodiments of the present application, there is provided a computer program product comprising computer instructions stored in a computer-readable storage medium, which, when read by a processor of a computer device from the computer-readable storage medium, cause the processor to execute the computer instructions, so that the computer device performs the steps of implementing the method as provided by the first aspect.
The technical scheme provided by the embodiment of the application has the following beneficial effects:
the method comprises the steps of firstly determining at least one target instruction meeting preset specified conditions from an instruction file, and reading test point information of the at least one target instruction; and then acquiring a random value generation condition corresponding to at least one target instruction, generating at least one random value corresponding to at least one target instruction according to the random value generation condition corresponding to at least one target instruction, and generating an assembly code file of the test case corresponding to the instruction set test point file according to the test point information of at least one target instruction and at least one random value. The embodiment of the application realizes coverage of the critical scene, improves the coverage rate of the critical scene, can comprehensively verify the test points of the instruction set, and further finds potential abnormality.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments of the present application will be briefly described below.
Fig. 1 is a schematic flowchart of a method for generating an assembly code file of a test case according to an embodiment of the present application;
fig. 2 is a schematic diagram of instructions and test point information stored in an instruction set test point file according to an embodiment of the present application;
fig. 3 is a schematic diagram of an assembly code file for generating a test case from an instruction set test point file according to an embodiment of the present application;
FIG. 4 is a diagram illustrating a test case assembly template according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of an assembly code file of a test case corresponding to an instruction file set according to an embodiment of the present application;
fig. 6 is a schematic diagram of the number of test cases generated by the target instruction under the condition of the same random value according to the embodiment of the present application;
fig. 7 is a schematic structural diagram of a device for generating an assembly code file of a test case according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the embodiments set forth below in connection with the drawings are exemplary descriptions for explaining technical solutions of the embodiments of the present application, and do not limit the technical solutions of the embodiments of the present application.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the terms "comprises" and/or "comprising," when used in this specification in connection with embodiments of the present application, specify the presence of stated features, information, data, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, information, data, steps, operations, elements, components, and/or groups thereof, as embodied in the art. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein indicates at least one of the items defined by the term, e.g., "a and/or B" may be implemented as "a", or as "B", or as "a and B".
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The terms referred to in this application will first be introduced and explained:
RISCV (read as "RISC-FIVE") is an open Instruction Set Architecture (ISA) built based on the principle of Reduced Instruction Set Computing (RISC), V is expressed as a fifth generation RISC (reduced instruction set computer), the reduced instruction set computer RISC is an open Instruction Set Architecture (ISA) built based on the principle of Reduced Instruction Set Computing (RISC), and RISCV is a new instruction set built on the basis of the continuous development and maturity of instruction sets.
The instruction set is a set of instructions used by the CPU to calculate and control the computer system, and each new CPU is designed to define a series of instruction systems that cooperate with other hardware circuits. Whether the instruction set is advanced or not also relates to the performance exertion of the CPU, and the instruction set is also an important mark for embodying the performance of the CPU.
A terminal, which is a device having a wireless transceiving function in this embodiment of the present application, may be referred to as a terminal (terminal), a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), an access terminal, a vehicle-mounted terminal, an industrial control terminal, a UE unit, a UE station, a mobile station, a remote terminal, a mobile device, a UE terminal, a wireless communication device, a UE agent, or a UE apparatus. The terminal device may be fixed or mobile, for example, the terminal device may be a mobile phone (mobile phone), a tablet (pad), a desktop, a notebook, a kiosk, a vehicle-mounted terminal, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in self driving (self driving), a wireless terminal in remote surgery (remote medical supply), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation safety, a wireless terminal in smart city (smart city), a wireless terminal in smart home (smart home), a cellular phone, a cordless phone, a session initiation protocol (session initiation protocol) phone, a wireless local loop (SIP) phone, a wireless local loop (remote local) terminal, a personal digital assistant (wllocal digital assistant), a PDA), a handheld device with wireless communication capabilities, a computing device or other processing device connected to a wireless modem, a wearable device, a terminal device in a future mobile communication network or a terminal device in a public mobile land network (PLMN) for future evolution, etc.
In order to solve at least one technical problem or place needing improvement in the related art, the application provides a method, a device, an electronic device, a computer readable storage medium and a computer program product for generating an assembly code file of a test case, wherein the scheme includes that at least one target instruction meeting preset specified conditions is determined from an instruction set test point file, and test point information of the at least one target instruction is read; and then acquiring a random value generation condition corresponding to at least one target instruction, generating at least one random value corresponding to at least one target instruction according to the random value generation condition corresponding to at least one target instruction, and generating an assembly code file of the test case corresponding to the instruction set test point file according to the test point information of at least one target instruction and at least one random value. The coverage of the critical scene can be realized, the coverage rate of the critical scene is improved, the instruction set information can be comprehensively verified, and then potential faults can be found.
The technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application will be described below through descriptions of several exemplary embodiments. It should be noted that the following embodiments may be referred to, referred to or combined with each other, and the description of the same terms, similar features, similar implementation steps and the like in different embodiments is not repeated.
The embodiment of the application provides a method for generating an assembly code file of a test case, as shown in fig. 1, the method includes:
step S101, determining at least one target instruction meeting preset limiting conditions from an instruction set test point file, and reading test point information of the at least one target instruction; the instruction set test point file comprises at least one instruction and test point information of the at least one instruction.
The test point file of the instruction set in the embodiment of the present application is a set of instructions and a set of test point information corresponding to the instructions, and specifically, the test point file of the instruction set in the embodiment of the present application may be an excel file.
The test point file of the instruction set of the embodiment of the application comprises at least one instruction AND test point information of the at least one instruction, the instruction set can refer to a RISCV instruction set, AND the instruction set can comprise logic AND, logic integer AND ANDI, logic plus ADD, logic integer plus ADDI AND other instructions.
The test point file of the instruction set test point file comprises a target instruction and part of test point information of the target instruction, and the test point information in the test point file of the instruction set comprises some typical values, boundary values and user-defined values which are taken by source operands.
It should be emphasized that the test point in the embodiment of the present application is not limited to any one or a combination of several of the above critical values, typical values, and user-defined values, and the above combination cannot cover all critical scenarios, and a random value is also introduced, that is, the test point is a combination of any one or several of the critical values, typical values, user-defined values, and random values, for example, for the operation of two source operands, the test point may be a combination of a random value and a random value, a combination of a critical value and a random value, a combination of a typical value and a critical value, and the like, and the determination of the random value is detailed in the following.
The test point information in the embodiment of the application comprises a unique identifier of an instruction, at least one source operand and values of the source operands.
The unique identifier of the instruction may be an instruction name, such as an instruction name of a logical AND instruction "RV 64I _ logical _ AND", where "RV 64I" is a basic integer instruction set, a 64-bit register bit width, AND the basic integer instruction is named "I" (prefixes RV32, RV64, AND RV128 represent register bit widths), AND includes an integer calculation instruction, an integer load, an integer store, AND a control flow instruction, AND an "I" class instruction with a corresponding bit width must be implemented in the design of RISC-V with different register bit widths, that is, the "I" class instruction must be implemented.
In the embodiment of the application, various instructions and test point information of the various instructions are stored in the instruction set test point file, but not all the instructions need to generate a code file of a corresponding test case, so that some limiting conditions are set, and a target instruction is screened from the instruction set test point file by presetting the limiting conditions.
Specifically, the preset limiting condition may be "inst _ only", "inst _ category _ only", "inst _ exclusive", and "inst _ category _ exclusive", where "inst _ only" is used to limit assembly code of a test case generating a specified instruction, for example, a code file that limits only a test case generating a corresponding to a "logical and" instruction is generated, and then the "logical and" instruction is a target instruction; "inst _ category _ only" is used to define a code file for generating a test case of an instruction of a specified category, such as a logical integer plus "ADDI", where "I" identifies an integer instruction, defines an assembly code of a test case for generating an instruction whose source operand is an integer, determines an instruction using a source operand bit integer as a target instruction, and may be of a type of "/M/a/F/D/C" in addition to I, and corresponds to multiply-divide, atomic, single-precision, double-precision, or compressed instruction types, respectively; "inst _ exclusive" and "inst _ only" are opposite, and are used for limiting the code file which does not generate the test case of the specified category, for example, limiting the code file which does not generate the test case corresponding to the logic subtraction instruction, so that the other instructions except the logic subtraction instruction are target instructions; "inst _ category _ exclusive" and "inst _ category _ only" are used in contrast to each other to define a code file that does not generate test cases for instructions of a specified category, such as a code file that defines test cases that do not generate instructions that originally operate as floating point numbers, and so on.
The method and the device for reading the excel file read by calling the python openpyxl module read the instruction set test point file, read the excel file and need to introduce the python openpyxl module, and particularly, when one excel file is read, two modules, namely a Path module and an openpyxl module, need to be introduced, wherein the Path module is used for setting a Path and a file name, and the excel file is read by the openpyxl module.
In addition, it should be emphasized that, in the embodiment of the present application, a plurality of instructions and test point information of each instruction are stored in the instruction set test point file, the test point information in the instruction set test point file is recorded according to a certain rule, and the openpyxl module also follows the rule when reading the instruction set test point file, as shown in fig. 2, which exemplarily shows the instructions and the test point information stored in the instruction set test point file.
Line 1 represents the instruction as "AND", the operator "AND", AND the operands are "rs 1", "rs 2", AND "rd", where "rs 1" AND "rs 2" are the source operands AND "rd" is the destination operand; the involved arithmetic logic is x [ rd ] ═ x [ rs1] & x [ rs2], namely, the result of the AND bit of the register x [ rs1] and the register x [ rs2] is written into x [ rd ], and the involved Macro command is Macro: TEST _ RR _ OP;
"AND _ rs1_ max" in line 2 indicates the maximum value taken by the source operand rs1 in the instruction "AND", the maximum value being "u 64' hfffff _ FFFF", note that "AND _ rs1_ max" is underlined to indicate that this is a critical value, "u" indicates an unsigned number, AND "s" indicates a signed number;
"AND _ rs1_ min" in line 3 represents the minimum value taken by the source operand rs1 in the instruction "AND", the maximum value is "u 64' h0000_0000_ 0000", note that "AND _ rs1_ min" is underlined, indicating that this is a critical value;
"and.rs 1. typical" in lines 4 to 7 indicates that typical values taken by the source operand rs1 in the instruction "AND" u64 'h 5555_5555_5555_5555 "," u 64' hAAAA _ AAAA "," u64 'hffff _ FFFF _ FFFE (next largest value) "AND" u 64' h0000_0000_0000_0001 (next smallest value) ";
similarly, "AND _ rs2_ max" in line 8 represents the maximum value taken by the source operand rs2 in the instruction "AND", the maximum value being "u 64' hfffff _ FFFF"; "AND _ rs2_ min" in the 9 th line represents the minimum value taken by the source operand rs2 in the instruction "AND", the maximum value is "u 64 ' h0000_0000_ 0000", AND "and.rs 2. min" in the 9 th to 12 th lines represents the typical values taken by the source operand rs1 in the instruction "AND" u64 ' h5555_5555_5555 "," u64 ' aaa _ AAAA "," u64 ' hffff _ FFFF _ FFFE ", AND" u64 ' h0000_0000_0000_0001 ".
Step S102, obtaining a random value generating condition corresponding to at least one target instruction, and generating at least one random value corresponding to at least one target instruction according to the random value generating condition corresponding to the at least one target instruction.
The random value generation condition in the embodiment of the present application is used to define a generated random value, such as setting a seed (seed) to a target instruction, where the setting of the seed affects the result of randomization, specifically, for example, setting the seed to 0, generating the same random value, setting the seed to 1, and generating a sequence random value, such as generating the sequence of random values to be "10, 20, 30, 40 … …".
In addition to setting seeds, the random value generation condition in the embodiment of the application may also set the number of iterations, for example, the number of iterations is 1, generate 1 group of random values, the assembly code of the test case corresponding to each group of target instructions in the assembly code file of the generated test case is 1 group, on the basis of the number of iterations being 1, limit the number of iterations to 2, generate two groups of random values, and regenerate one assembly code file of the assembly case, where in the assembly code file of the assembly test case assembly, the assembly code of the test case of each group of target instructions is 2 groups.
In the embodiment of the present application, the random value generation conditions corresponding to different target instructions may be different, and the random value generation conditions need to be set for each target instruction according to an actual situation, which is not limited in the embodiment of the present application.
Step S103, generating an assembly code file of the test case corresponding to the test point file of the instruction set according to the test point information of the at least one target instruction and the at least one random value.
After the test point information of the target instruction is read and the at least one random value corresponding to the target instruction is generated, the assembly code file of the test case corresponding to the test point file of the instruction set is generated according to the test point information of the target instruction and the at least one random value.
As shown in fig. 3, the process diagram exemplarily illustrates that the instruction set test point file is converted into the assembly code file of the test case in the embodiment of the present application, a target instruction is determined from the instruction set test point file, a python openpyxl module is used to read and analyze the target instruction and the test point information of the target instruction, then at least one random value corresponding to at least one target instruction is generated by using a random value generation condition, and the assembly code file of the test case corresponding to the instruction set test point file is generated according to the test point information and the random value of each target instruction.
The method comprises the steps of firstly determining at least one target instruction meeting preset specified conditions from an instruction set test point file, and reading test point information of the at least one target instruction; and then acquiring a random value generation condition corresponding to at least one target instruction, generating at least one random value corresponding to at least one target instruction according to the random value generation condition corresponding to at least one target instruction, and generating an assembly code file of the test case corresponding to the instruction set test point file according to the test point information of at least one target instruction and at least one random value. The embodiment of the application realizes coverage of the critical scene, improves the coverage rate of the critical scene, and can comprehensively verify the instruction set information so as to find potential faults.
The embodiment of the application provides a possible implementation manner, and the test point information comprises at least one source operand and a value corresponding to the source operand;
generating at least one random value corresponding to at least one target instruction according to a random value generation condition corresponding to at least one target instruction, including:
obtaining a value of at least one source operand of at least one target instruction, and determining a value range of the source operand according to the value of the source operand;
determining the value range of a random value according to the value range of the source operand;
and generating at least one random value corresponding to at least one target instruction according to the random value generation condition and the value range of the random value.
In the embodiment of the application, the random value is randomly generated through the random value generation condition, different instructions may correspond to different random value generation conditions, and the random value is generated according to the random value generation condition, but the random value is also the value of the operand, so that the random value needs to be located in the value range of the source operand, and the value range of the source operand is the value range of the random value.
Specifically, in continuation of the above example, the maximum value of the source operand rs1 is "u 64 'hfffff _ FFFF", and the minimum value is "u 64' h0000_0000_ 0000", so that the range of the generated random value is between "u 64 'h 0000_0000_0000_ 0000" and "u 64' hfffff _ FFFF".
After the value range of the random value is determined, at least one random value in the value range of the random value is generated according to the random value generation condition.
The embodiment of the present application provides a possible implementation manner, and the determining at least one random value corresponding to at least a target instruction according to a random value generation condition and a value range of the random value includes:
if the random value generation condition comprises a seed setting condition, acquiring a seed set for at least one target instruction, and generating at least one random value corresponding to at least one target instruction according to the value range of the random value and the seed set for at least one target instruction.
If the random value generation condition comprises a seed setting condition, the seed setting condition is a condition for setting seeds for a target instruction, if the random value generation condition of a certain target instruction is the seed setting condition, the target instruction is indicated to be provided with the seeds, the seed setting condition can influence the randomization result, and is used for appointing an integer value of an algorithm used for generating the random value.
After the value range of the random value and the seeds set for the target instruction are determined, at least one random value corresponding to the target instruction is generated.
The embodiment of the present application provides a possible implementation manner, and the determining at least one random value corresponding to at least a target instruction according to a random value generation condition and a value range of the random value includes:
if the random value generation condition comprises a set iteration frequency condition, acquiring the iteration frequency of the random value set for the at least one target instruction, and generating the at least one random value corresponding to the at least one target instruction according to the value range of the random value and the iteration frequency of the random value.
In the embodiment of the application, if the random value generation condition is the set iteration number condition, and if the random value generation condition includes the set iteration number condition, it indicates that the iteration number of the random value is set for the target instruction, the iteration number set for the random value of the target instruction needs to be obtained, the iteration number is 1, it indicates that only one group of random values is generated, the iteration number is 2, it indicates that two groups of random values are generated, and any random value in the two groups of random values is different.
Specifically, assuming that the random value generation condition set for a certain target instruction is only the second generation condition, if the number of iterations is 2, and the generated set of random values has "u 64 ' h0000_0000_0100_ 0000", "u 64 ' h0010_0000_0000_ 0000", "u 64 ' h0000_00EF _0000_ 0000" … …, each random value in the generated second set of random values is different from the first set of random values.
The embodiment of the present application provides a possible implementation manner, where an assembly code file of a test case corresponding to an instruction set test point file is generated according to test point information of at least one target instruction and at least one random value, and the method includes:
generating assembly codes of test cases corresponding to the target instructions according to the test point information of the target instructions and at least one random value of the target instructions;
and combining the test case assembly codes corresponding to the target instructions according to a preset rule to generate an assembly code file of the test case corresponding to the instruction set test point file.
The assembly code files of the test cases corresponding to the instruction set test point files are formed by combining the assembly code files of the test cases of the target instructions, the assembly codes of the test cases corresponding to the target instructions are generated firstly, and then the assembly codes corresponding to the target instructions are combined according to preset rules to generate the assembly codes of the test cases corresponding to the instruction set test point files, and detailed contents are shown in the subsequent part.
The embodiment of the application provides a possible implementation manner, and the test point information further comprises an instruction unique identifier; the values of the source operands comprise typical values, critical values and user-defined values;
generating assembly codes of test cases corresponding to the target instructions according to the test point information of the target instructions and at least one random value of the target instructions, wherein the assembly codes comprise:
selecting at least one input value as a source operand of a target instruction from a typical value, a critical value, a user-defined value and a random value;
and calling a test case assembly template corresponding to each target instruction, filling the instruction unique identifier, the source operand and the input value of the source operand of each target instruction into the corresponding test case assembly template, and generating the assembly code of the test case of each target instruction.
The values of the source operands in the embodiments of the present application include critical values, typical values, user-defined values, and random values. Wherein, the critical value comprises a maximum value and a minimum value; typical values may be next-to-large values, next-to-small values, etc.
For integer type source operands, typical values may be all 0, all 1, 10 interleave, 01 interleave, and may also be walking one and walking zero, where walking zero means that only one bit of a hexadecimal number is 0, and the change of the value can be realized by shifting the position of 0 to the left or right, for example, for the hexadecimal number "u 64 ' h1111_1111_1111_ 1110", the "u 64 ' h1111_1111_ 1101, u64 ' h1111_1111_ 1011, u64 ' h1111_1111_1111_0111, u64 ' h1111_1111_1110_1111 _1111_1111, … … u64 ' 1110_1111_1111_1111, u64 ' h _1111_1111, u64 ' h1011_1111_1111_1111, and u64 ' h1111_1111_ 1" which can be obtained after walking one, which is the same reason for the case that this embodiment is not repeated in this application, and this is no longer shifted to the right in this application.
For floating point type source operands, typical values may also be adjacent positive and negative norm boundary values, adjacent positive and negative non-norm boundary values, ± 0, ± 1, positive and negative infinity, static non-numbers (qNaN), signal non-numbers (sinan), and the like.
In the embodiment of the present application, the various values may be input values that are mutually combinable and serve as source operands, and taking an example that the target instruction includes two source operands, the input values of the two source operands may be a combination of a critical value and a critical value, a combination of a critical value and a typical value, a combination of a critical value and a user-defined value, a combination of a critical value and a random value, a combination of a typical value and a typical value, a combination of a typical value and a user-defined value, a combination of a user-defined value and a random value, and a combination of two and two of these may serve as input values of the two operands, so as to cover various test scenarios.
After the input value of each source operand of each target instruction is determined, the test case assembly template corresponding to each target instruction is called, and the unique identifier of each target instruction, the source operand and the input value of the source operand are filled into the corresponding test case assembly template, so that the assembly code of the test case corresponding to each target instruction is generated.
The test case assembly template in the embodiment of the application comprises the unique identifier of the target instruction, the source operand and the placeholder corresponding to the input value of the source operand, and the unique identifier of the target instruction, the source operand and the input value of the source operand can be filled in the corresponding placeholder by calling the openpyxl module, so that the assembly code of the test case corresponding to the target instruction is generated.
As shown in fig. 4, an exemplary test case assembly template is shown, where the test case assembly template is a logic and corresponding test case assembly template, the instruction unique identifier and the input values of the source operands need to be filled into corresponding placeholders, and the corresponding placeholders of other information, such as Macro commands Macro and the like, are left in the test case assembly template.
It should be emphasized that the assembly template of the test case is just one specific example, and other information may also be added to the assembly template of the test case, and may be set according to actual situations.
The embodiment of the present application provides a possible implementation manner, where the test case assembly template includes a unique identifier of a target instruction and a placeholder corresponding to an input value of a source operand, and specific contents of the foregoing embodiment are not described herein again.
As shown in fig. 5, which illustrates an assembly code file of a TEST case corresponding to an instruction set TEST point file, taking "TEST _ RR _ OP (ADD, x11, x26, x21, dummy,0 xffffffffffffffffffffff, 0x5d7d56aef11622f, x2,8, x 3)" as an example, TEST _ RR _ OP is a macro command, "0 xffffffffffffffffffffffffff" is an input value corresponding to an original operation rs1, "0 xffffffffffffffffffffffffffffffffffffffffffffffffff" is an input value corresponding to a source operand 2, it is obvious that "0 xffffffffffffffffffffffffffff" is a critical value, a maximum value of the source operand 1, and "0 x5d7d56aef11622 f" is a random value.
As shown in fig. 6, which exemplarily shows the number of generated test points for each target instruction under the same random value, the abscissa is the name of the target instruction, the ordinate is the number of test points corresponding to each target instruction, there are 100 RISCV instructions involved, and there are 309 test points generated because some floating point instructions have rounding modes; most of instructions have about 1000 test points, and include three source operation indexes, and each source operand is floating point type target instruction corresponding to the largest number of test points, for example, instruction fmadd.s can be as high as 70000, which cannot be realized by manpower.
An embodiment of the present application provides a device for generating an assembly code file of a test case, as shown in fig. 7, the device 70 for generating an assembly code file of a test case may include:
a target instruction obtaining module 710, configured to determine at least one target instruction meeting a preset limiting condition from the instruction set test point file, and read test point information of the at least one target instruction; the instruction set test point file comprises at least one instruction and test point information of the at least one instruction;
a random value generating module 720, configured to obtain a random value generating condition corresponding to at least one target instruction, and generate at least one random value corresponding to at least one target instruction according to the random value generating condition corresponding to at least one target instruction;
the assembly code generating module 730 is configured to generate an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value.
The method comprises the steps of firstly determining at least one target instruction meeting preset specified conditions from an instruction set test point file, and reading test point information of the at least one target instruction; and then acquiring a random value generation condition corresponding to at least one target instruction, generating at least one random value corresponding to at least one target instruction according to the random value generation condition corresponding to at least one target instruction, and generating an assembly code file of the test case corresponding to the instruction set test point file according to the test point information of at least one target instruction and at least one random value. The embodiment of the application realizes coverage of the critical scene, improves the coverage rate of the critical scene, and can comprehensively verify the instruction set information so as to find potential faults.
The embodiment of the application provides a possible implementation manner, and the test point information comprises at least one source operand and a value corresponding to the source operand;
a random value generation module comprising:
the source operand value range determining submodule is used for acquiring the value of at least one source operand of at least one target instruction and determining the value range of the source operand according to the value of the source operand;
the random value range determining submodule is used for determining the value range of the random value according to the value range of the source operand;
and the random value generation submodule is used for generating at least one random value corresponding to at least one target instruction according to the random value generation condition and the value range of the random value.
The embodiment of the present application provides a possible implementation manner, in which a random value generation submodule includes:
a random value generation first unit, configured to, if the random value generation condition includes a set seed condition, obtain a seed set for the at least one target instruction, and generate at least one random value corresponding to the at least one target instruction according to a value range of the random value and the seed set for the at least one target instruction;
the embodiment of the present application provides a possible implementation manner, in which a random value generation submodule includes:
and the random value generation second unit is used for acquiring the iteration times of the random value set for the at least one target instruction if the random value generation condition comprises a set iteration time condition, and determining the at least one random value corresponding to the at least one target instruction according to the value range of the random value and the iteration times of the random value.
The embodiment of the present application provides a possible implementation manner, and the assembly code generation module includes:
the target instruction test case assembly code generation module is used for generating the assembly code of the test case corresponding to each target instruction according to the test point information of each target instruction and at least one random value of each target instruction;
and the assembly code generation submodule is used for combining the test case assembly codes corresponding to the target instructions according to a preset rule to generate the assembly codes of the test cases corresponding to the instruction set test point file.
The embodiment of the application provides a possible implementation manner, and the test point information further comprises an instruction unique identifier; the values of the source operands comprise typical values, critical values and user-defined values;
the assembly code generation submodule further comprises:
an input value determining unit for selecting at least one input value as a source operand of the target instruction from the typical value, the critical value, the user-defined value and the random value;
and the test case assembly code generating unit is used for calling the test case assembly template corresponding to each target instruction, filling the instruction unique identifier of each target instruction and the input value of the source operand into the corresponding test case assembly template, and generating the assembly code of the test case corresponding to each target instruction.
The embodiment of the application provides a possible implementation manner, and the test case assembly template comprises a unique identifier of a target instruction and a placeholder corresponding to an input value of a source operand.
The apparatus of the embodiment of the present application may execute the method provided by the embodiment of the present application, and the implementation principle is similar, the actions executed by the modules in the apparatus of the embodiments of the present application correspond to the steps in the method of the embodiments of the present application, and for the detailed functional description of the modules of the apparatus, reference may be specifically made to the description in the corresponding method shown in the foregoing, and details are not repeated here.
The embodiment of the application provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to realize the steps of the generation method of the assembly code file of the test case, and compared with the prior art, the method can realize the following steps: the method comprises the steps of firstly determining at least one target instruction meeting preset specified conditions from an instruction set test point file, and reading test point information of the at least one target instruction; and then acquiring a random value generation condition corresponding to at least one target instruction, generating at least one random value corresponding to at least one target instruction according to the random value generation condition corresponding to at least one target instruction, and generating an assembly code file of the test case corresponding to the instruction set test point file according to the test point information of at least one target instruction and at least one random value. The embodiment of the application realizes coverage of the critical scene, improves the coverage rate of the critical scene, and can comprehensively verify the instruction set information so as to discover potential abnormality.
In an alternative embodiment, an electronic device is provided, as shown in FIG. 8, the electronic device 8000 shown in FIG. 8 including: a processor 8001 and memory 8003. Processor 8001 is coupled to memory 8003, such as via bus 8002. Optionally, the electronic device 8000 may further include a transceiver 8004, and the transceiver 8004 may be used for data interaction between the electronic device and other electronic devices, such as transmission of data and/or reception of data. In addition, the transceiver 8004 is not limited to one in practical applications, and the structure of the electronic device 8000 does not limit the embodiment of the present application.
Processor 8001 may be a CPU (Central Processing Unit), general purpose Processor, DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), or other Programmable logic device, transistor logic device, hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. Processor 8001 may also be a combination that implements computing functionality, e.g., comprising one or more microprocessor combinations, DSP and microprocessor combinations, and so forth.
Bus 8002 may include a path to transfer information between the aforementioned components. The bus 8002 may be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus 8002 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 8, but this is not intended to represent only one bus or type of bus.
The Memory 8003 may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical Disc storage, optical Disc storage (including Compact Disc, laser Disc, optical Disc, digital versatile Disc, blu-ray Disc, etc.), a magnetic Disc storage medium, other magnetic storage devices, or any other medium that can be used to carry or store a computer program and that can be Read by a computer, without limitation.
The memory 8003 is used to store computer programs for executing the embodiments of the present application, and is controlled by the processor 8001 to execute the programs. The processor 8001 is used to execute computer programs stored in the memory 8003 to implement the steps shown in the foregoing method embodiments.
The electronic device package may include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (personal digital assistant), a PAD (tablet computer), a PMP (portable multimedia player), a vehicle-mounted terminal (e.g., a car navigation terminal), etc., and a stationary terminal such as a digital TV, a desktop computer, etc., among others. The electronic device shown in fig. 5 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.
Embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, and when being executed by a processor, the computer program may implement the steps and corresponding contents of the foregoing method embodiments. Compared with the prior art, the method can realize that: the method comprises the steps of firstly determining at least one target instruction meeting preset specified conditions from an instruction set test point file, and reading test point information of the at least one target instruction; and then acquiring a random value generation condition corresponding to at least one target instruction, generating at least one random value corresponding to at least one target instruction according to the random value generation condition corresponding to at least one target instruction, and generating an assembly code file of the test case corresponding to the instruction set test point file according to the test point information of at least one target instruction and at least one random value. The embodiment of the application realizes coverage of the critical scene, improves the coverage rate of the critical scene, and can comprehensively verify the instruction set information so as to discover potential abnormality.
It should be noted that the computer readable medium in the present disclosure can be a computer readable signal medium or a computer readable medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present disclosure, a computer readable signal medium may comprise a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.
The embodiments of the application also provide a computer program product comprising a computer program which, when executed by a processor, is adapted to carry out the steps of the aforementioned method embodiments and the corresponding content. Compared with the prior art, the method can realize that: the method comprises the steps of firstly determining at least one target instruction meeting preset specified conditions from an instruction set test point file, and reading test point information of the at least one target instruction; and then acquiring a random value generation condition corresponding to at least one target instruction, generating at least one random value corresponding to at least one target instruction according to the random value generation condition corresponding to at least one target instruction, and generating an assembly code file of the test case corresponding to the instruction set test point file according to the test point information of at least one target instruction and at least one random value. The embodiment of the application realizes coverage of the critical scene, improves the coverage rate of the critical scene, and can comprehensively verify the instruction set information so as to discover potential abnormality.
It should be understood that, although each operation step is indicated by an arrow in the flowchart of the embodiment of the present application, the implementation order of the steps is not limited to the order indicated by the arrow. In some implementation scenarios of the embodiments of the present application, the implementation steps in the flowcharts may be performed in other sequences as desired, unless explicitly stated otherwise herein. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on an actual implementation scenario. Some or all of these sub-steps or stages may be performed at the same time, or each of these sub-steps or stages may be performed at different times, respectively. In a scenario where execution times are different, an execution sequence of the sub-steps or the phases may be flexibly configured according to requirements, which is not limited in the embodiment of the present application.
The above are only optional embodiments of partial implementation scenarios in the present application, and it should be noted that, for those skilled in the art, other similar implementation means based on the technical idea of the present application are also within the scope of protection of the embodiments of the present application without departing from the technical idea of the present application.

Claims (10)

1. A method for generating an assembly code file of a test case is characterized by comprising the following steps:
determining at least one target instruction meeting a preset limiting condition from an instruction set test point file, and reading test point information of the at least one target instruction; the instruction set test point file comprises at least one instruction and test point information of the at least one instruction;
acquiring a random value generation condition corresponding to the at least one target instruction, and generating at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction;
and generating an assembly code file of the test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value.
2. The method of claim 1, wherein the site information comprises at least one source operand and a value corresponding to the source operand;
the generating at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction includes:
obtaining a value of at least one source operand of the at least one target instruction, and determining a value range of the source operand according to the value of the source operand;
determining the value range of the random value according to the value range of the source operand;
and generating at least one random value corresponding to the at least one target instruction according to the random value generation condition and the value range of the random value.
3. The method according to claim 2, wherein the generating at least one random value corresponding to the at least one target instruction according to the random value generation condition and a value range of the random value includes:
if the random value generation condition comprises a seed setting condition, acquiring a seed set for the at least one target instruction, and generating at least one random value corresponding to the at least one target instruction according to the value range of the random value and the seed.
4. The method according to claim 2, wherein the generating at least one random value corresponding to the at least one target instruction according to the random value generation condition and a value range of the random value includes:
if the random value generation condition comprises a set iteration frequency condition, acquiring the iteration frequency of a random value set for the at least one target instruction, and determining the at least one random value corresponding to the at least one target instruction according to the value range of the random value and the iteration frequency of the random value.
5. The method of claim 1, wherein the generating an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value comprises:
generating assembly codes of test cases corresponding to the target instructions according to the test point information of the target instructions and at least one random value of the target instructions;
and combining the test case assembly codes corresponding to the target instructions according to a preset rule to generate the assembly codes of the test cases corresponding to the instruction set test point files.
6. The method of claim 5, wherein the test point information further comprises an instruction unique identifier; the values of the source operands comprise typical values, critical values and user-defined values;
the generating assembly codes of the test cases corresponding to the target instructions according to the test point information of the target instructions and at least one random value of the target instructions comprises the following steps:
selecting at least one input value from the typical value, the critical value, the user-defined value and the random value as a source operand of the target instruction;
and calling a test case assembly template corresponding to each target instruction, filling the instruction unique identifier of each target instruction and the input value of the source operand into the corresponding test case assembly template, and generating the assembly code of the test case corresponding to each target instruction.
7. The method of claim 6, wherein the testcase assembly template comprises a unique identifier of the target instruction and a placeholder corresponding to an input value of the source operand.
8. An apparatus for generating an assembly code file of a test case, comprising:
the target instruction acquisition module is used for determining at least one target instruction meeting a preset limiting condition from the instruction set test point file and reading test point information of the at least one target instruction; the instruction set test point file comprises at least one instruction and test point information of the at least one instruction;
a random value generation module, configured to obtain a random value generation condition corresponding to the at least one target instruction, and generate at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction;
and the assembly code generating module is used for generating an assembly code file of the test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory, characterized in that the processor executes the computer program to implement the steps of the method of any of claims 1-7.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
CN202111445893.7A 2021-11-30 2021-11-30 Method and device for generating assembly code file of test case and electronic equipment Pending CN114036064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111445893.7A CN114036064A (en) 2021-11-30 2021-11-30 Method and device for generating assembly code file of test case and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111445893.7A CN114036064A (en) 2021-11-30 2021-11-30 Method and device for generating assembly code file of test case and electronic equipment

Publications (1)

Publication Number Publication Date
CN114036064A true CN114036064A (en) 2022-02-11

Family

ID=80139341

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111445893.7A Pending CN114036064A (en) 2021-11-30 2021-11-30 Method and device for generating assembly code file of test case and electronic equipment

Country Status (1)

Country Link
CN (1) CN114036064A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114756474A (en) * 2022-04-27 2022-07-15 苏州睿芯集成电路科技有限公司 Method and device for generating random vector in CPU verification and electronic equipment
CN114880174A (en) * 2022-05-07 2022-08-09 苏州睿芯集成电路科技有限公司 Modularized and configurable fast regression method and device in CPU verification
CN115509909A (en) * 2022-09-26 2022-12-23 北京百度网讯科技有限公司 Test method, test device, electronic equipment and storage medium

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114756474A (en) * 2022-04-27 2022-07-15 苏州睿芯集成电路科技有限公司 Method and device for generating random vector in CPU verification and electronic equipment
CN114880174A (en) * 2022-05-07 2022-08-09 苏州睿芯集成电路科技有限公司 Modularized and configurable fast regression method and device in CPU verification
CN115509909A (en) * 2022-09-26 2022-12-23 北京百度网讯科技有限公司 Test method, test device, electronic equipment and storage medium
CN115509909B (en) * 2022-09-26 2023-11-07 北京百度网讯科技有限公司 Test method, test device, electronic equipment and storage medium

Similar Documents

Publication Publication Date Title
CN114036064A (en) Method and device for generating assembly code file of test case and electronic equipment
US10908925B2 (en) Dynamic loading method, and target file creation method and apparatus
CN110909356B (en) Secure multiparty computing method, apparatus, device and computer readable medium
US8769244B2 (en) SIMD parallel computer system, SIMD parallel computing method, and control program
CN118331539B (en) Divider, data processing method, system, equipment and computer medium
US11714604B2 (en) Device and method for binary flag determination
CN111124541A (en) Configuration file generation method, device, equipment and medium
CN117215650A (en) Register updating method and device, electronic equipment and readable storage medium
US7647368B2 (en) Data processing apparatus and method for performing data processing operations on floating point data elements
CN111384971B (en) Method, device and decoder for processing data in finite field
CN116680140A (en) Verification method, system, device and storage medium for processor
KR0146656B1 (en) Multi-nary or logic device
CN115344876A (en) Data processing method, device, equipment and storage medium
CN114461418A (en) Inter-process communication method and device and electronic equipment
CN110730044A (en) Radio frequency test channel positioning method and device, radio frequency test system and control terminal
CN109582279B (en) Data operation device and related product
CN116301766A (en) Method, device, equipment and medium for generating assembly code file of test case
CN112905181B (en) Model compiling and running method and device
CN114691141A (en) Method, apparatus, device and medium for code compiling
CN111552478A (en) Apparatus, method and storage medium for generating CUDA program
CN116737390B (en) Atomic operation processing method and device, electronic equipment and storage medium
CN112445525B (en) Data processing method, related equipment and computer readable medium
US7191203B2 (en) Method and system for high-speed multiplication
CN112989365B (en) Data processing method, device, equipment and storage medium
US20230259581A1 (en) Method and apparatus for floating-point data type matrix multiplication based on outer product

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: 100176 Room 101, 1f, building 3, yard 18, Kechuang 10th Street, Beijing Economic and Technological Development Zone, Beijing

Applicant after: Beijing ESWIN Computing Technology Co.,Ltd.

Address before: 100176 Room 101, 1f, building 3, yard 18, Kechuang 10th Street, Beijing Economic and Technological Development Zone, Beijing

Applicant before: Beijing yisiwei Computing Technology Co.,Ltd.

CB02 Change of applicant information