CN107463473A - Chip software and hardware simulated environment based on UVM and FPGA - Google Patents

Chip software and hardware simulated environment based on UVM and FPGA Download PDF

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Publication number
CN107463473A
CN107463473A CN201710783768.4A CN201710783768A CN107463473A CN 107463473 A CN107463473 A CN 107463473A CN 201710783768 A CN201710783768 A CN 201710783768A CN 107463473 A CN107463473 A CN 107463473A
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module
fpga
uvm
dut
sent
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CN107463473B (en
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洪灏
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Zhuhai Core Semiconductor Co Ltd
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Zhuhai Core Semiconductor Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a kind of chip software and hardware simulated environment based on UVM and FPGA.The simulated environment includes FPGA verification platforms, UVM verification platforms and IP master patterns.IP master patterns are connected with FPGA verification platforms, and driving FPGA carries out simulating, verifying, and is sent to UVM verification platforms using the result of FPGA checkings as site environment configuration.UVM verification platforms are connected with IP master patterns, and the result for calling the algorithm in IP master patterns to verify FPGA carries out UVM simulating, verifyings.The present invention connects FPGA verification platforms and UVM verification platforms by IP master patterns, has made a software and hardware simulating, verifying environment that can carry out FPGA checkings and UVM checkings simultaneously.Chip application layer is absorbed in FPGA checkings, completes the checking that chip code is directed to a large amount of arbitrary excitation scenes；Chip bottom is absorbed in UVM checkings, and the result that FPGA is verified further is verified by directly invoking the algorithm in IP master patterns；Two kinds of checkings cooperate, and accelerate the cycle of chip checking, improve the quality of chip checking.

Description

Chip software and hardware simulated environment based on UVM and FPGA
Technical field
The present invention relates to chip emulation to verify field, more particularly to a kind of chip software and hardware emulation based on UVM and FPGA Environment.
Background technology
In recent years, as the appearance of extensive SOC and multi core design, special integrated chip (ASIC) design more and more multiple Miscellaneous, the function complexity of chip greatly increases so that the checking of chip requires more and more higher.How chip is completed in a short time Functional verification, ensure that logic function is correct, higher requirement is proposed to the completeness of verification environment, automation and reusability.
FPGA checkings write test case using hardware description language to design to be measured, and synthesis goes out netlist simultaneously after simple simulation Download on Target Board and debugged, judge whether designed function is correct by observing output waveform.Traditional FPGA Checking constructs test case, workload is big, always someone will to slip, difficult one by one using orientation test for all function points To accomplish all standing, relatively it is adapted to the chip checking large-scale, complexity is low.Although in view of the above-mentioned problems, FPGA accidental validations Appearance chip code can be allowed to travel through more scenes.But FPGA accidental validations are verified primarily directed to application layer, The content of chip bottom can not be captured, it is impossible to some information of chip internal are obtained, if code coverage, scene composition feelings Condition, performance statistics etc.), the problem of can not existing to chip, positions.
Verified compared to FPGA, UVM checkings have OOP, constraint arbitrary excitation, the inspection of Power coverage rate, asserted Deng attribute, it is easier to carry out positioning problems.Verification environment and verification methodology based on UVM can create it is solid, reusable, Automation, easy care, the testing process component for having interoperability, have obtained industry and have generally approved and use.But due to emulation Limited speed, UVM checkings can not travel through too many scene, be adapted to small-sized, complicated chip checking.
The content of the invention
The purpose of the present invention aims to provide a kind of chip software and hardware simulated environment based on UVM and FPGA, accelerates chip and tests The cycle of card, the efficiency and quality for improving chip checking.
In order to realize the purpose of the present invention, this invention takes following technical scheme：
A kind of chip software and hardware simulated environment based on UVM and FPGA, including FPGA verification platforms, UVM verification platforms；Its It is characterised by：The simulated environment also includes IP master patterns；The IP master patterns are connected with FPGA verification platforms, driving FPGA carries out simulating, verifying, and is sent to UVM verification platforms using the result of FPGA checkings as site environment configuration；The UVM Verification platform is connected with IP master patterns, and the result for calling the algorithm in IP master patterns to verify FPGA carries out UVM emulation and tested Card.
Further, the IP master patterns include control module, print module, algorithm model, excitation generator, first Bus driver；The control module is bi-directionally connected with algorithm model, the first bus driver respectively, and is produced with print module, excitation Raw device, UVM verification platforms unidirectionally connect；The print module is connected with algorithm model；It is described excitation generator respectively with algorithm Model, the connection of the first bus driver；First bus driver is bi-directionally connected with FPGA verification platforms；
The control module control excitation generator produces pumping signal, and control algolithm model is generated according to chip to be measured and calculated Pumping signal is sent to FPGA verification platforms by method, the first bus driver of control, and control print module is set in algorithm model Error print point, that is, print breakpoint；The print module by algorithm model set printing breakpoint, problem of implementation it is quick Positioning；Pumping signal is transmitted directly to algorithm model and emulated by the excitation generator, and simulation result is sent into control Molding block；Pumping signal is sent to FPGA verification platforms by the first bus driver and emulated by the excitation generator, and Simulation result is sent to control module by the first bus driver；
The simulation result that the control module exports FPGA verification platforms and the simulation result of algorithm model output are carried out Compare, and the result that comparative result is FPGA checkings is sent to UVM verification platforms as site environment configuration.
Further, the FPGA verification platforms include fpga chip and the second bus driver；Second bus is driven It is dynamic to be bi-directionally connected respectively with the first bus driver, fpga chip；Second bus driver is received by the first bus driver to swash The pumping signal of generator output is encouraged, and pumping signal is sent to fpga chip；The fpga chip is according to the excitation of input Signal is emulated, and simulation result is sent into the first bus driver by the second driving bus, and then is sent to control mould Block.
Further, the FPGA verification platforms also include hardware external equipment；The hardware external equipment and FPGA cores Piece is bi-directionally connected, and receives FPGA driving, and result is fed back into fpga chip.
Further, the UVM verification platforms include test case module, test case configuration module, data configuration module, Reference model, scoring board, DUT (design under testbench, design to be measured) modules (as follows) and the first monitoring Device；The test case module is connected with control module, test case configuration module；The test case configuration module respectively with Reference model, DUT module connection；The data configuration module is connected with reference model, DUT module respectively；The reference model It is connected with algorithm model, scoring board；The DUT module is sequentially connected with the first monitor, scoring board；
The result of the FPGA checkings of the test case module receive and control module output simultaneously produces random test use-case hair Give test case configuration module；The random test use-case of the test case configuration module storage test case module output is simultaneously Random test use-case is respectively configured to reference model and DUT module；The data configuration module produce random data and by this A little random data are respectively configured to reference model and DUT module；
The algorithm that the reference model is directly invoked in algorithm model is imitated the random data under random test use-case Very, and by simulation result it is sent to scoring board；The random data that the DUT module is directed under random test use-case is emulated, And simulation result is sent to the first monitor；First monitor says that the simulation result of DUT module output is sent to score Plate；The simulation result that the DUT module that the scoring board gathers the first monitor exports and the simulation result of reference model output It is compared, and is printed comparative result as the UVM results verified.
Further, the data configuration module includes random data generator, the second driver and the 3rd monitor； The random data generator is sequentially connected with the second driver, DUT module；The random data generator produces random number According to random data is sent into DUT module by the second driver and drives DUT module to be emulated；The random data production Raw device is sequentially connected with the second driver, the 3rd monitor, reference model；3rd monitor is received by the second driver The random data of random data generator output, and random data is sent to reference model under the driving of the second driver and entered Row emulation.
Further, the test case module includes arbitrary excitation and random sequence generator；The arbitrary excitation with Control module, random sequence generator connection, the result of the FPGA checkings of receive and control module output simultaneously produce arbitrary excitation field Scape is sent to random sequence generator；The random sequence generator is concurrent according to arbitrary excitation scene generation random test use-case Give test case configuration module.
Further, the test case configuration module includes random sequence scheduler, the first driver, the second monitoring Device；The random sequence scheduler is connected with random sequence generator, is received and is stored the random of random sequence generator output Test case；The random sequence scheduler is sequentially connected with the first driver, DUT module, will be random by the first driver Test case is sent to DUT module and drives DUT module to be emulated；The random sequence scheduler and the first driver, Two monitors and reference model are sequentially connected；Second monitor is defeated by the first driver reception random sequence scheduler The random test use-case gone out, and random test use-case is sent to reference model under the driving of the first driver and emulated.
Further, the test case configuration module also includes coverage rate statistical module；The coverage rate statistical module It is connected with the first driver, the random test use-case of random sequence scheduler output is received by the first driver, is surveyed to random The coverage rate of example on probation is counted.
Further, the DUT module includes DUT and virtual interface；The virtual interface and the first driver, DUT connect Connect, receive the random test use-case of the first driver output and be sent to DUT；The virtual interface and the second driver, DUT connect Connect, receive the random data of the second driver output and be sent to DUT；The DUT connects successively with virtual interface, the first monitor Connect, emulated for the random data under random test use-case and simulation result is sent to the first monitoring by virtual interface Device, and then it is sent to scoring board.
Further, the UVM verification platforms also include top-level module；The top-level module includes emulation script, control Platform, assert, memory；The console is sequentially connected with emulation script, DUT, loading emulation scripted code, by the various of encapsulation Configuration parameter is output to whole UVM verification platforms；The console is connected with memory, and the order for receiving emulation script is completed to deposit The initialization of reservoir；The memory is bi-directionally connected with DUT, and data interaction is carried out with DUT；It is described to assert and console and virtual Interface is connected, and the order of emulation script is received by console, monitors virtual interface in real time.
Further, the top-level module also includes performance test module, Debug test modules；The console and property Energy test module, the connection of Debug test modules, performance test is carried out to whole UVM verification platforms and Debug is tested；The property Energy test module is for judging whether the performance of system meets expection；The Debug test modules, that is, eliminate fault test mould Block, whether completed for the elimination of detecting system failure.
Further, the UVM verification platforms also include self-defined library file；The self-defined library file respectively with reference Model, scoring board and the connection of test case configuration module, all global variables, event, the print control of encapsulation are sent to Reference model, scoring board and test case configuration module.
Beneficial effect of the present invention：
From above technical scheme, the present invention connects FPGA verification platforms and UVM verification platforms by IP master patterns, A software and hardware simulating, verifying environment that can carry out FPGA checkings and UVM checkings is simultaneously made.Wherein, FPGA checkings are absorbed in Chip application layer, complete the checking that chip code is directed to a large amount of arbitrary excitation scenes；IP master patterns drive FPGA verification platforms Simulating, verifying is carried out, and UVM verification platforms are sent to using the result of FPGA checkings as site environment configuration；UVM checkings are absorbed in In chip bottom, the result that FPGA is verified further is verified by directly invoking the algorithm in IP master patterns；Two kinds Checking cooperates, and accelerates the cycle of chip checking, improves the quality of chip checking.Meanwhile the present invention in IP by marking Error print point is set using print module in quasi-mode type, it is possible to achieve the fast positioning of problem；The present invention in UVM by verifying The collection of coverage rate can be realized in platform using coverage rate statistical module.
Brief description of the drawings
In order to illustrate the embodiments of the present invention more clearly, simple Jie is done to the required accompanying drawing used in embodiment below Continue.Drawings in the following description are only the embodiment in the present invention, for one of ordinary skill in the art, are not being paid On the premise of going out creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the general structure block diagram of the present invention；
Embodiment
Below in conjunction with the accompanying drawings, the present invention will be described in detail.
In order that the purpose of the present invention, technical scheme, advantage are more clearly understood, below in conjunction with drawings and Examples to this Invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, not For limiting the present invention.
As shown in figure 1, a kind of chip software and hardware simulated environment based on UVM and FPGA, including FPGA verification platforms, UVM Verification platform, IP master patterns.IP master patterns are connected with FPGA verification platforms, and driving FPGA carries out simulating, verifying, and will The result of FPGA checkings is sent to UVM verification platforms as site environment configuration.UVM verification platforms are connected with IP master patterns, The algorithm in IP master patterns is called to carry out simulating, verifying.Due to algorithm model from FPGA checking and UVM checking in solely It is vertical to come out, now only need to modify to the algorithm in algorithm model, you can complete to different DUT (design under Testbench, design to be measured) (as follows) simulating, verifying.If mistake occur in FPGA checkings, UVM verification platforms can utilize Wrong scene list in site environment configuration, problem emulation positioning is carried out, then carry out batch recurrence, it is ensured that the solution of problem.
As shown in figure 1, IP master patterns include control module, print module, algorithm model, excitation generator, first total Line drives.Control module is bi-directionally connected with algorithm model, the first bus driver respectively, and with print module, excitation generator, UVM verification platforms unidirectionally connect.Print module is connected excitation generator with algorithm model and driven respectively with algorithm model, the first bus Dynamic connection.First bus driver is bi-directionally connected with FPGA verification platforms.
Control module control excitation generator produces pumping signal, control algolithm model according to chip generating algorithm to be measured, Control the first bus driver that pumping signal is sent into FPGA verification platforms, control print module sets mistake in algorithm model Print point, that is, print breakpoint.IP master patterns set in algorithm model printing breakpoint by print module, problem of implementation it is fast Speed positioning.Pumping signal is transmitted directly to algorithm model and emulated by excitation generator, and simulation result is sent into control Module.Meanwhile encourage generator that pumping signal is sent into FPGA verification platforms by the first bus driver and emulated, and will Simulation result is sent to control module by the first bus driver.Simulation result that control module exports FPGA verification platforms with The simulation result of algorithm model output is compared, and the result that comparative result is FPGA checkings is configured as site environment and sent out Give UVM verification platforms.
In the present embodiment, then algorithm model is controlling first by C model or MATLAB model construction master patterns In the presence of module, master pattern is rewritten according to the implementation of actual chips, obtains accurate algorithm.
In the present embodiment, the FPGA results verified are allocated to UVM verification platforms by control module by way of printing.
As shown in figure 1, FPGA verification platforms include fpga chip, the second bus driver and hardware external equipment.Second Bus driver is bi-directionally connected with the first bus driver, fpga chip respectively, and it is defeated to receive actuation generator by the first bus driver The pumping signal gone out, and pumping signal is sent to fpga chip；Fpga chip is emulated according to the pumping signal of input, and Simulation result is sent to the first bus driver by the second driving bus, and then is sent to control module.Hardware external equipment It is bi-directionally connected with fpga chip, receives FPGA driving, and result is fed back into fpga chip.
As shown in figure 1, UVM verification platforms include test case module, test case configuration module, data configuration module, Reference model, scoring board, DUT module, the first monitor, top-level module and self-defined library file.Test case module and control Molding block, the connection of test case configuration module.Test case configuration module is connected with reference model, DUT module respectively.Data are matched somebody with somebody Module is put to be connected with reference model, DUT module respectively.Reference model is connected with algorithm model, scoring board.DUT module and first Monitor, scoring board are sequentially connected.Top-level module is connected with DUT module.Self-defined library file respectively with reference model, scoring board And test case configuration module connection.
The result of the FPGA checkings of test case module receive and control module output simultaneously produces random test use-case and is sent to Test case configuration module.The random test use-case of test case configuration module storage test case module output will simultaneously be surveyed at random Example on probation is respectively configured to reference model and DUT module.Data configuration module produces random data and divides these random data Reference model and DUT module are not allocated to it.
The algorithm that reference model is directly invoked in algorithm model emulates to the random data under random test use-case, and Simulation result is sent to scoring board.The random data that DUT module is directed under random test use-case is emulated, and emulation is tied Fruit is sent to the first monitor.First monitor says that the simulation result of DUT module output is sent to scoring board.Scoring board is by first The simulation result of the DUT module output of monitor collection will compare knot compared with the simulation result that reference model exports Fruit is printed as the UVM results verified.Scoring board can confirm that whether emulation is correct first according to the result of printing, then Error print point in reference model can problem of implementation positioning.
Self-defined library file by all global variables, event, the print control of encapsulation be sent to reference model, scoring board and Test case configuration module.Now UVM verification platforms can directly invoke the code in self-defined library file, and it is unnecessary to reduce Size of code, and directly modifications and extensions self-defined library files can be changed with the bottom completed to whole UVM verification platforms.
As shown in figure 1, test case module includes arbitrary excitation and random sequence generator.Arbitrary excitation and control mould Block, random sequence generator connection, the result of the FPGA checkings of receive and control module output simultaneously produce the transmission of arbitrary excitation scene To random sequence generator.Random sequence generator produces random test use-case according to arbitrary excitation scene and is sent to test and uses Example configuration module.
As shown in figure 1, test case configuration module includes random sequence scheduler, the first driver, the second monitor, covered Lid rate statistical module.Random sequence scheduler is connected with random sequence generator, is received and is stored random sequence generator output Random test use-case.Random sequence scheduler is sequentially connected with the first driver, DUT module, will be with by the first driver Machine test case is sent to DUT module and drives DUT module to be emulated.Random sequence scheduler and the first driver, second Monitor and reference model are sequentially connected.Second monitor by the first driver receive that random sequence scheduler exports with Machine test case, and random test use-case is sent to reference model under the driving of the first driver and emulated.Coverage rate Statistical module is connected with the first driver, and the random test use-case of random sequence scheduler output is received by the first driver, The coverage rate of test case is counted.
As shown in figure 1, data configuration module includes random data generator, the second driver and the 3rd monitor.With Machine data producer is sequentially connected with the second driver, DUT module.Random data generator produces random data, passes through second Random data is sent to DUT module and drives DUT module to be emulated by driver.Random data generator and the second driving Device, the 3rd monitor, reference model are sequentially connected.3rd monitor receives random data generator by the second driver and exported Random data, and random data is sent to reference model under the driving of the second driver and emulated.
As shown in figure 1, DUT module includes DUT and virtual interface.Virtual interface is connected with the first driver, DUT, is received The random test use-case of first driver output is simultaneously sent to DUT.Virtual interface is connected with the second driver, DUT, receives second The random data of driver output is simultaneously sent to DUT.DUT is sequentially connected with virtual interface, the first monitor, for random test Random data under use-case is emulated and simulation result is sent into the first monitor by virtual interface, and then is sent to meter Scoreboard.
As shown in figure 1, top-level module includes emulation script, console, asserted, memory, performance test module, Debug Test module.Console is sequentially connected with emulation script, DUT, loading emulation scripted code, and the various configuration parameters of encapsulation are defeated Go out to whole UVM verification platforms.Console is connected with memory, and the initialization of memory is completed in the order for receiving emulation script. Memory is bi-directionally connected with DUT, and data interaction is carried out with DUT.Assert and be connected with console and virtual interface, connect by console The order of emulation script is received, monitoring virtual interface in real time simultaneously can fast positioning interface problem.Console and performance test module, Debug test modules are connected, and performance test is carried out to whole UVM verification platforms and Debug is tested.Performance test module be for Judge whether the performance of system meets expection.Debug test modules, that is, fault test module is eliminated, be for detecting system event Whether the elimination of barrier is completed.
Described above is only the preferred embodiments of the present invention, and protection scope of the present invention is not limited merely to above-mentioned implementation Example, all technical schemes belonged under thinking of the present invention belong to protection scope of the present invention.It should be pointed out that for the art Those of ordinary skill for, some improvements and modifications without departing from the principles of the present invention, these improvements and modifications It should be regarded as protection scope of the present invention.

Claims (13)

1. a kind of chip software and hardware simulated environment based on UVM and FPGA, including FPGA verification platforms, UVM verification platforms；It is special Sign is：The simulated environment also includes IP master patterns；The IP master patterns are connected with FPGA verification platforms, drive FPGA Simulating, verifying is carried out, and UVM verification platforms are sent to using the result of FPGA checkings as site environment configuration；The UVM checkings Platform is connected with IP master patterns, and the result for calling the algorithm in IP master patterns to verify FPGA carries out UVM simulating, verifyings.
A kind of 2. chip software and hardware simulated environment based on UVM and FPGA according to claim 1, it is characterised in that：
The IP master patterns include control module, print module, algorithm model, excitation generator, the first bus driver；It is described Control module is bi-directionally connected with algorithm model, the first bus driver respectively, and flat with print module, excitation generator, UVM checkings Platform unidirectionally connects；The print module is connected with algorithm model；The excitation generator drives with algorithm model, the first bus respectively Dynamic connection；First bus driver is bi-directionally connected with FPGA verification platforms；
Control module control excitation generator produces pumping signal, control algolithm model according to chip generating algorithm to be measured, Control the first bus driver that pumping signal is sent into FPGA verification platforms, control print module sets mistake in algorithm model Print point, that is, print breakpoint；The print module by setting printing breakpoint in algorithm model, determine by the quick of problem of implementation Position；Pumping signal is transmitted directly to algorithm model and emulated by the excitation generator, and simulation result is sent into control Module；Pumping signal is sent to FPGA verification platforms by the first bus driver and emulated by the excitation generator, and will Simulation result is sent to control module by the first bus driver；
The control module by the simulation result that FPGA verification platforms export compared with the simulation result that algorithm model exports, And the result that comparative result is FPGA checkings is sent to UVM verification platforms as site environment configuration.
A kind of 3. chip software and hardware simulated environment based on UVM and FPGA according to claim 2, it is characterised in that：Institute Stating FPGA verification platforms includes fpga chip and the second bus driver；Second bus driver is driven with the first bus respectively Dynamic, fpga chip is bi-directionally connected；Second bus driver receives the excitation of excitation generator output by the first bus driver Signal, and pumping signal is sent to fpga chip；The fpga chip is emulated according to the pumping signal of input, and will be imitative True result is sent to the first bus driver by the second driving bus, and then is sent to control module.
A kind of 4. chip software and hardware simulated environment based on UVM and FPGA according to claim 3, it is characterised in that：Institute Stating FPGA verification platforms also includes hardware external equipment；The hardware external equipment is bi-directionally connected with fpga chip, receives FPGA Driving, and result is fed back into fpga chip.
A kind of 5. chip software and hardware simulated environment based on UVM and FPGA according to claim 2, it is characterised in that：
The UVM verification platforms include test case module, test case configuration module, data configuration module, reference model, meter Scoreboard, DUT module and the first monitor；The test case module is connected with control module, test case configuration module；Institute Test case configuration module is stated to be connected with reference model, DUT module respectively；The data configuration module respectively with reference model, DUT module connects；The reference model is connected with algorithm model, scoring board；The DUT module and the first monitor, scoring board It is sequentially connected；
The result of the FPGA checkings of test case module receive and control module output simultaneously produces random test use-case and is sent to Test case configuration module；The random test use-case of test case configuration module storage test case module output simultaneously will be with Machine test case is respectively configured to reference model and DUT module；The data configuration module produce random data and by these with Machine data are respectively configured to reference model and DUT module；
The algorithm that the reference model is directly invoked in algorithm model emulates to the random data under random test use-case, and Simulation result is sent to scoring board；The random data that the DUT module is directed under random test use-case is emulated, and will be imitative True result is sent to the first monitor；The simulation result that DUT module exports is sent to scoring board by first monitor；It is described Scoring board is compared the simulation result that the simulation result that the DUT module that the first monitor gathers exports exports with reference model Compared with, and printed comparative result as the UVM results verified.
A kind of 6. chip software and hardware simulated environment based on UVM and FPGA according to claim 5, it is characterised in that：Institute Stating data configuration module includes random data generator, the second driver and the 3rd monitor；The random data generator It is sequentially connected with the second driver, DUT module；The random data generator produces random data, will by the second driver Random data is sent to DUT module and drives DUT module to be emulated；The random data generator and the second driver, Three monitors, reference model are sequentially connected；3rd monitor receives random data generator by the second driver and exported Random data, and random data is sent to reference model under the driving of the second driver and emulated.
A kind of 7. chip software and hardware simulated environment based on UVM and FPGA according to claim 6, it is characterised in that：Institute Stating test case module includes arbitrary excitation and random sequence generator；The arbitrary excitation produces with control module, random sequence Raw device connection, the result of the FPGA checkings of receive and control module output simultaneously produce arbitrary excitation scene and are sent to random sequence generation Device；The random sequence generator produces random test use-case according to arbitrary excitation scene and is sent to test case configuration mould Block.
A kind of 8. chip software and hardware simulated environment based on UVM and FPGA according to claim 7, it is characterised in that：Institute Stating test case configuration module includes random sequence scheduler, the first driver, the second monitor；The random sequence scheduler It is connected with random sequence generator, receives and store the random test use-case of random sequence generator output；The random sequence Scheduler is sequentially connected with the first driver, DUT module, and random test use-case is sent into DUT module by the first driver And DUT module is driven to be emulated；The random sequence scheduler and the first driver, the second monitor and reference model according to Secondary connection；The random test use-case that second monitor is exported by the first driver reception random sequence scheduler, and Random test use-case is sent into reference model under the driving of first driver to be emulated.
A kind of 9. chip software and hardware simulated environment based on UVM and FPGA according to claim 8, it is characterised in that：Institute Stating test case configuration module also includes coverage rate statistical module；The coverage rate statistical module is connected with the first driver, is led to The random test use-case that the first driver receives the output of random sequence scheduler is crossed, the coverage rate of random test use-case is united Meter.
10. a kind of chip software and hardware simulated environment based on UVM and FPGA according to claim 7 or 8, its feature exist In：The DUT module includes DUT and virtual interface；The virtual interface is connected with the first driver, DUT, receives the first driving The random test use-case of device output is simultaneously sent to DUT；The virtual interface is connected with the second driver, DUT, receives the second driving The random data of device output is simultaneously sent to DUT；The DUT is sequentially connected with virtual interface, the first monitor, for random test Random data under use-case is emulated and simulation result is sent into the first monitor by virtual interface, and then is sent to meter Scoreboard.
A kind of 11. chip software and hardware simulated environment based on UVM and FPGA according to claim 10, it is characterised in that： The UVM verification platforms also include top-level module；The top-level module includes emulation script, console, asserted, memory；Institute State console to be sequentially connected with emulation script, DUT, loading emulation scripted code, the various configuration parameters of encapsulation are output to whole Individual UVM verification platforms；The console is connected with memory, and the initialization of memory is completed in the order for receiving emulation script；Institute State memory to be bi-directionally connected with DUT, data interaction is carried out with DUT；Described assert is connected with console and virtual interface, passes through control Platform processed receives the order of emulation script, monitors virtual interface in real time.
A kind of 12. chip software and hardware simulated environment based on UVM and FPGA according to claim 11, it is characterised in that： The top-level module also includes performance test module, Debug test modules；The console is surveyed with performance test module, Debug Die trial block is connected, and performance test is carried out to whole UVM verification platforms and Debug is tested；The performance test module is for sentencing Whether the performance of disconnected system meets expection；The Debug test modules, that is, fault test module is eliminated, is for detecting system Whether the elimination of failure is completed.
A kind of 13. chip software and hardware simulated environment based on UVM and FPGA according to claim 10, it is characterised in that： The UVM verification platforms also include self-defined library file；The self-defined library file respectively with reference model, scoring board and survey Example configuration module connection on probation, by all global variables, event, the print control of encapsulation be sent to reference model, scoring board and Test case configuration module.
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