CN112306882B - Chip algorithm module verification method and system based on C algorithm model - Google Patents
Chip algorithm module verification method and system based on C algorithm model Download PDFInfo
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- CN112306882B CN112306882B CN202011231291.7A CN202011231291A CN112306882B CN 112306882 B CN112306882 B CN 112306882B CN 202011231291 A CN202011231291 A CN 202011231291A CN 112306882 B CN112306882 B CN 112306882B
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Abstract
The application discloses a chip algorithm module verification method based on a C algorithm model, which develops related functional modules by expanding the existing C algorithm model, and moderately matches the C algorithm model with the hardware implementation of the algorithm on the premise of ensuring the function of the original C algorithm model, so that the C algorithm model is easy to integrate into a verification environment. And the transmission between the verification environment and the C model is realized through the DPI-C interface, so that the operation of the verification use case is completely automated. Meanwhile, files are not used as transmission media between the C model and the verification environment in the test process, so that storage space is saved. Because the C model is compiled independently, the development and the debugging of the C model are independent of the verification platform, the verification efficiency is improved, and the source code of the C algorithm model is not required to be provided for a verifier, so that the confidentiality of the algorithm code is ensured. In addition, the application also provides a chip algorithm module verification system based on the C algorithm model, and the technical effect of the chip algorithm module verification system corresponds to that of the method.
Description
Technical Field
The application relates to the technical field of computers, in particular to a chip algorithm module verification method and system based on a C algorithm model.
Background
Chip verification is an important link in the chip development process, and as the chip scale is larger and larger, the complexity of chip verification is higher and higher. For chips for realizing the algorithm functions, a large amount of data is usually required to be processed or a plurality of complex operations are required to be carried out, the processed result is greatly different from the original input data, and a corresponding algorithm model is required to be used as a reference when an algorithm module is verified.
Algorithm models are typically implemented using high-level languages, and there are typically several implementation methods:
the method 1 uses a verification language such as System Verilog to realize an algorithm model, integrates the algorithm model into a verification environment, and can compare the output result of a chip algorithm module with the output result of the algorithm model in real time in the running process of a verification case so as to judge the correctness of the result.
The method 2 uses a non-verification language to realize an algorithm model, processes input data based on the algorithm model, generates corresponding results, and stores the input data and the corresponding results in an input data file and a reference result file respectively. Reading data from an input data file as excitation in the running process of the verification use case, injecting the data into the chip algorithm module, storing an output result of the chip algorithm module into an output result file, and judging the correctness of the result by comparing the content of the output result file with the content of the reference result file after the running of the verification use case is finished.
The method 3, the algorithm model is realized by using the C language, the C algorithm model is independently compiled into an executable file, the executable file is operated by a $system System function in a System Verilog when the verification use case is operated, meanwhile, input data are transmitted to the executable file in a pre-agreed mode, a result generated by the executable file is written into a reference file, an output result of a chip algorithm module is stored into the result file, and after the verification use case is operated, the correctness of the result is judged by comparing the contents of the result file and the reference file.
And 4, realizing an algorithm model by using a C language, and importing the C algorithm model into a verification environment through a System Verilog and a DPI-C interface of C, and compiling the C algorithm model together with the verification environment. In the operation process of the verification use case, besides the input data is injected into the chip algorithm module, the imported C interface function is also called, the input data is input into the C algorithm model, the reference result is calculated, and the correctness of the result is judged by comparing the output result of the chip algorithm module with the reference result output by the C algorithm model.
The method 1 can realize real-time online comparison, but has obvious defects that the existing algorithm model cannot be reused, and the verification language is required to be used for secondary development, so that additional cost is increased.
The method 2 independently separates the generation of the reference result from the operation process of the verification case, and uses the file as a data transmission medium to transmit data, so that the method has the defects that the automatic verification is not easy to realize, and the number of the files to be saved is increased along with the increase of the excitation range, so that a large amount of extra storage space is required to be occupied.
Although the above method 3 integrates the operation of the algorithm model into the verification environment and can be controlled by the verification case, the disadvantage of the above method 2 is the same as that of the above method 3, but still requires the use of a file as a medium to transfer the result.
The method 4 needs to compile a reference model and a verification environment together, needs to put an algorithm source code into the verification environment, and a verification personnel packages a DPI-C interface on the basis of the algorithm model, so that the method has the defects that firstly, the algorithm model is integrated into the verification environment, when the verification case fails to run and the problem needs to be positioned through a comparison algorithm middle process, the algorithm model is not easy to independently debug, and an additional auxiliary means is needed; secondly, the confidentiality of the algorithm code cannot be guaranteed when cooperating with a third party.
To sum up, the verification scheme for the chip algorithm module at present needs to disclose the source code of the algorithm model, and the confidentiality of the algorithm code cannot be ensured; or the file is used as a data transmission medium, so that a large storage space is occupied; or the existing algorithm model cannot be reused, increasing development cost.
Disclosure of Invention
The purpose of the application is to provide a chip algorithm module verification method and system based on a C algorithm model, which are used for multiplexing the existing C algorithm model, and realizing the automatic verification of the chip algorithm module under the condition that a C algorithm model source code is not externally provided and a file is not used as a data transmission medium. The specific scheme is as follows:
in a first aspect, the present application provides a chip algorithm module verification method based on a C algorithm model, including:
the verification case module randomly generates configuration information on line according to constraint conditions and transmits the configuration information to the excitation generator through a first DPI-C interface;
the excitation generator generates excitation according to the configuration information, transmits the excitation to the first format conversion module, and transmits the excitation after format conversion to the verification case module through the first DPI-C interface;
the verification case module transmits the configuration information and the excitation after format conversion to the chip algorithm module respectively; the chip algorithm module generates an actual result and transmits the actual result to the checker;
capturing the configuration information and the format-converted excitation from an input port of a chip algorithm model, transmitting the configuration information to a C algorithm model through a second DPI-C interface, transmitting the format-converted excitation to a second format conversion module through a second DPI-C interface, and transmitting the format-converted excitation to the C algorithm model again; the algorithm model C generates a reference result, the reference result is transmitted to a third format conversion module, and the reference result after format conversion is transmitted to the checker through a third DPI-C interface;
The checker judges whether the actual result is consistent with the reference result, if so, the checker indicates that the verification case is successful in operation;
the first DPI-C interface, the second DPI-C interface and the third DPI-C interface are transmission interfaces between a C model and a verification environment; the C model is a model obtained by taking the C algorithm model as a core extension and comprises a C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module; c, compiling a model in advance independently;
the first format conversion module is used for converting the stimulus into a data format suitable for hardware processing, the second format conversion module is used for converting the stimulus into a data format suitable for C algorithm model processing, and the third format conversion module is used for converting the result into a data format suitable for hardware processing.
Preferably, the method further comprises:
when the actual result is inconsistent with the reference result, starting a file storage function through a dynamic switch;
storing the excitation after format conversion into an excitation file; saving the reference result after format conversion into a reference result file;
saving the actual result into an actual result file;
And repeating the verification process according to the excitation file, the reference result file and the actual result file, and positioning the problem.
Preferably, the excitation after format conversion is stored in an excitation file; storing the format-converted reference result into a reference result file, wherein the method comprises the following steps:
storing the original excitation and the excitation after format conversion into an original excitation file and an excitation file respectively; respectively storing the original reference result or the reference result after format conversion into an original reference result file and a reference result file;
judging whether the format conversion of the excitation is normal or not according to the original excitation file and the excitation file; and judging whether the format conversion of the reference file is normal or not according to the original reference result file and the reference result file.
Preferably, the verification case module randomly generates configuration information on line according to constraint conditions, including:
the verification use case module randomly generates configuration information on line according to constraint conditions, wherein the configuration information comprises any one or more of the following: task type, data type, number of data blocks, data block size, random seed.
Preferably, before the verification case module randomly generates the configuration information on line according to the constraint condition, the method further comprises:
expanding the C algorithm model into a C model;
compiling the model C;
creating a transmission interface between the C model and the verification environment;
the C model is integrated into the verification environment.
Preferably, the compiling the C model includes:
compiling all source codes except the test routine in the C model and linking the source codes into target files, compiling the codes of the test routine, and linking the target files to generate executable files.
Preferably, the creating a transmission interface between the C model and the verification environment includes:
creating a DPI-C interface used for transmitting configuration information from the verification case module to the incentive generator, and transmitting the incentive after format conversion from the first format conversion module to the verification case module to obtain a first DPI-C interface;
creating a DPI-C interface for transmitting configuration information from an input port of the algorithm module chip to the C algorithm model, and transmitting the excitation after format conversion from the input port of the algorithm module chip to a second format conversion module to obtain a second DPI-C interface;
and creating a DPI-C interface for transmitting the reference result after format conversion from a third format conversion module to an inspector, and obtaining a third DPI-C interface.
Preferably, the integrating the C model into the verification environment includes:
compiling a link C algorithm model to generate a library file; and when the verification use case is operated, linking the library file, and adding target parameters into the command line parameters.
Preferably, the method further comprises:
the coverage rate collector performs coverage rate analysis, and determines uncovered configuration according to analysis results; and modifying constraint conditions in the verification case module according to the uncovered configuration, or creating a new verification case and sending the new verification case to the verification case module.
In a second aspect, the present application provides a chip algorithm module verification system based on a C algorithm model, including: the system comprises a C algorithm model, a chip algorithm module, a verification case module, an excitation generator, a first format conversion module, a second format conversion module, a third format conversion module and a checker;
the verification case module is used for randomly generating configuration information on line according to constraint conditions and transmitting the configuration information to the excitation generator through a first DPI-C interface;
the excitation generator is used for generating excitation according to the configuration information, transmitting the excitation to the first format conversion module, and transmitting the excitation after format conversion to the verification case module through the first DPI-C interface;
The verification case module is used for transmitting the configuration information and the excitation after format conversion to the chip algorithm module respectively; the chip algorithm module is used for generating an actual result and transmitting the actual result to the inspector;
capturing the configuration information and the format-converted excitation from an input port of a chip algorithm model, transmitting the configuration information to a C algorithm model through a second DPI-C interface, transmitting the format-converted excitation to a second format conversion module through a second DPI-C interface, and transmitting the format-converted excitation to the C algorithm model again; the C algorithm model is used for generating a reference result, transmitting the reference result to the third format conversion module, and transmitting the reference result after format conversion to the checker through the third DPI-C interface;
the checker is used for judging whether the actual result is consistent with the reference result, if so, the check is used for indicating that the verification case is successful to run;
the first DPI-C interface, the second DPI-C interface and the third DPI-C interface are transmission interfaces between a C model and a verification environment; the C model is a model obtained by taking the C algorithm model as a core extension and comprises a C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module; c, compiling a model in advance independently;
The first format conversion module is used for converting the stimulus into a data format suitable for hardware processing, the second format conversion module is used for converting the stimulus into a data format suitable for C algorithm model processing, and the third format conversion module is used for converting the result into a data format suitable for hardware processing.
According to the chip algorithm module verification method based on the C algorithm model, the existing C algorithm model is expanded, related functional modules are developed, and the C algorithm model is moderately matched with hardware implementation of an algorithm on the premise that the function of the original C algorithm model is guaranteed, so that the C algorithm model is easy to integrate into a verification environment. And the transmission between the verification environment and the C model is realized through the DPI-C interface, so that the operation of the verification use case is completely automated. Meanwhile, files are not used as transmission media between the C model and the verification environment in the test process, so that storage space is saved. Because the C model is compiled independently, the development and the debugging of the C model are independent of the verification platform, the verification efficiency is improved, and the source code of the C algorithm model is not required to be provided for a verifier, so that the confidentiality of the algorithm code is ensured.
In addition, the application further provides a chip algorithm module verification system based on the C algorithm model, and the technical effects of the chip algorithm module verification system correspond to those of the method, and are not repeated here.
Drawings
For a clearer description of embodiments of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description that follow are only some embodiments of the present application, and that other drawings may be obtained from these drawings by a person of ordinary skill in the art without inventive effort.
FIG. 1 is a flowchart of a first embodiment of a method for verifying a chip algorithm module based on a C algorithm model provided in the present application;
fig. 2 is a schematic diagram of a verification environment of a first embodiment of a chip algorithm module verification method based on a C algorithm model provided in the present application;
FIG. 3 is a flow chart of the overall verification process provided herein;
FIG. 4 is a flow chart of the file save function provided herein;
figure 5 is a flow chart of the DPI-C interface creation process provided herein;
fig. 6 is a schematic diagram of a C model in a second embodiment of a method for verifying a chip algorithm module based on a C algorithm model provided in the present application;
fig. 7 is a schematic diagram of a verification environment of a second embodiment of a chip algorithm module verification method based on a C algorithm model provided in the present application.
Detailed Description
The core of the application is to provide a chip algorithm module verification method and system based on a C algorithm model, which is integrated into a verification environment by performing function expansion on the C algorithm model. In the verification process, data transmission between the C model and the verification environment is realized through the DPI-C interface, automatic operation of verification cases is realized, files are not used as transmission media between the C model and the verification environment, and storage space is saved. Moreover, since the C model is compiled independently, the development and debugging of the C model is independent of the verification platform, and the C algorithm model source code does not need to be provided to the verification personnel.
In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The following describes an embodiment of a chip algorithm module verification method based on a C algorithm model. Referring to fig. 1 and 2, an embodiment one includes:
S101, a verification case module randomly generates configuration information on line according to constraint conditions and transmits the configuration information to an excitation generator through a first DPI-C interface;
the DPI-C interface, direct programming interface C, is a programming mode of direct interaction between System Verilog (a hardware design and verification language, simply SV) and C.
S102, an excitation generator generates excitation according to configuration information, and transmits the excitation to a first format conversion module, and the excitation after format conversion is transmitted to a verification case module through a first DPI-C interface;
s103, the verification case module transmits the configuration information and the excitation after format conversion to the chip algorithm module respectively; the chip algorithm module generates an actual result and transmits the actual result to the inspector;
s104, capturing the configuration information and the excitation after format conversion from an input port of the chip algorithm model, transmitting the configuration information to the C algorithm model through a second DPI-C interface, transmitting the excitation after format conversion to a second format conversion module through the second DPI-C interface, and transmitting the excitation after format conversion to the C algorithm model again; the algorithm model C generates a reference result, transmits the reference result to a third format conversion module, and transmits the reference result after format conversion to the checker through a third DPI-C interface;
Specifically, a monitor is arranged in the verification platform, the monitor is used for monitoring whether the verification case module transmits configuration information and the excitation after format conversion to the chip algorithm module, and if so, the configuration information and the excitation after format conversion are captured from an input port of the chip algorithm module.
S105, the checker judges whether the actual result is consistent with the reference result, if so, the checker indicates that the verification case is successful in operation; otherwise, the verification case fails to run. And when all verification cases of the chip algorithm module are successfully operated, indicating that the chip algorithm module passes the verification.
Verification is a process for checking whether the function of the chip design is correct, and verification use cases and verification environments are two elements of chip verification. In the verification process, an algorithm model is needed, the algorithm model uses a high-level language to realize functions and algorithms of a circuit, the functions of the algorithm model are verified in software algorithm verification, and in chip verification, the algorithm model is used as a reference standard for detecting whether chip design is correct or not. In this embodiment, the C algorithm model is used as a reference model in the verification process of the chip algorithm module.
For convenience of distinction, the present embodiment refers to an original C algorithm model as a C algorithm model, and refers to a model obtained by adding related functional modules to the original C algorithm model and expanding the same as the C algorithm model.
Before verification is executed, a C algorithm model is used as a core, a related functional module is developed, matching of the C algorithm model and hardware is achieved, and the independent running function of the C algorithm model is reserved, so that the C model is obtained. And compiling the C model into a cmodel.o file independently, providing the cmodel.o file and the C model API function statement for a verifier, developing a corresponding DPI-C interface function by the verifier based on the C model API, compiling DPI-C interface codes and linking the cmodel.o file of the C model, and generating a library file containing the DPI-C interface. When the verification case operates, the library files are linked, and the corresponding functions of the C model are used by calling the related DPI-C interface, so that the C model is organically combined with the verification environment, and the automatic verification of the chip algorithm module is realized.
To sum up, as shown in fig. 3, the whole verification process includes:
s301, expanding a C algorithm model into a C model;
s302, compiling a C model;
s303, creating a transmission interface between the C model and the verification environment;
s304, integrating the C model into a verification environment;
s305, a verification workflow, i.e., S101 to S105, is performed.
In this embodiment, the first DPI-C interface, the second DPI-C interface, and the third DPI-C interface are transmission interfaces between the C model and the verification environment. The C model obtained based on C algorithm model expansion specifically comprises the following steps: the system comprises a C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module. Each format conversion module is used for converting data from a data format suitable for hardware processing to a data format suitable for C algorithm model processing or converting data from a data format suitable for C algorithm model processing to a data format suitable for hardware processing.
The goal of the algorithm is either a large amount of arbitrary data, or target data that meets a specific rule, or both. The range of the former excitation is generally large, and the generation rule of the latter excitation varies greatly depending on the complexity of the algorithm. For algorithms with a large excitation range, a method for generating excitation in advance needs to save a large amount of data, and for algorithms with relatively complex excitation generation rules, a method for generating excitation by means of simple constraints in a verification platform has become less easy. Considering the specificity of the algorithm excitation, the embodiment adopts the C language to realize the excitation generator, and develops and debugges together with the C algorithm model.
The embodiment can realize the automatic verification of the chip algorithm module without generating intermediate files. In the regression test process, if the verification case fails to run, only the result can be seen, but the corresponding stimulus cannot be known, and in the embodiment, the stimulus is randomly generated under a certain constraint condition, so that the stimulus is difficult to completely reproduce. Therefore, in this embodiment, a dynamic switch of the file saving function is provided, and in order to save storage space, the dynamic switch is turned off by default, and when verification fails, the dynamic switch may be turned on. After the regression test is finished, the excitation and the results of all verification cases which fail to run are saved in the corresponding files, so that the verification personnel can reproduce and position the problems conveniently.
Thus, as shown in fig. 4, as a preferred embodiment, the present embodiment further includes:
s401, when the actual result is inconsistent with the reference result, starting a file storage function through a dynamic switch;
s402, storing the excitation after format conversion into an excitation file, and storing a reference result after format conversion into a reference result file;
s403, storing the actual result into an actual result file;
s404, repeating the verification process according to the excitation file, the reference result file and the actual result file, and positioning the problem.
On this basis, it is possible to consider that the excitation before and after format conversion and the results before and after format conversion are simultaneously saved, so that it is possible to check whether an error occurs in the relevant format conversion module. Therefore, the above S402 may specifically be: storing the original excitation and the excitation after format conversion into an original excitation file and an excitation file respectively; respectively storing the original reference result or the reference result after format conversion into an original reference result file and a reference result file; judging whether the stimulated format conversion is normal or not according to the original stimulated file and the stimulated file, namely judging whether the first format conversion module is normal or not; and judging whether the format conversion of the reference file is normal or not according to the original reference result file and the reference result file, namely judging whether the third format conversion module is normal or not.
In some specific embodiments, the foregoing process of compiling the C model specifically includes: compiling all source codes except the test routine in the C model and linking the source codes into target files, compiling the codes of the test routine, and linking the target files to generate executable files.
As shown in fig. 5, in some specific embodiments, the process of creating a transmission interface between the C model and the verification environment specifically includes:
s501, creating a DPI-C interface used for transmitting configuration information from the verification case module to the incentive generator, and transmitting the incentive after format conversion from the first format conversion module to the verification case module to obtain a first DPI-C interface;
s502, creating a DPI-C interface for transmitting configuration information from an input port of an algorithm module chip to a C algorithm model, and transmitting the excitation after format conversion from the input port of the algorithm module chip to a second format conversion module to obtain a second DPI-C interface;
s503, creating a DPI-C interface used for transmitting the reference result after format conversion from the third format conversion module to the checker, and obtaining a third DPI-C interface.
In some specific embodiments, the process of integrating the C model into the verification environment specifically includes: compiling a link C algorithm model to generate a library file; and (3) linking the library file when the verification use case is operated, and adding target parameters into the command line parameters.
According to the chip algorithm module verification method based on the C algorithm model, the existing C algorithm model is expanded, related functional modules are developed, and on the premise that the functions of the original C algorithm model are guaranteed, the C algorithm model is moderately matched with hardware implementation of the algorithm, so that the C algorithm model is easy to integrate into a verification environment. And the transmission between the verification environment and the C model is realized through the DPI-C interface, so that the operation of the verification use case is completely automated. Meanwhile, files are not used as transmission media between the C model and the verification environment in the test process, so that storage space is saved. Because the C model is compiled independently, the development and the debugging of the C model are independent of the verification platform, the verification efficiency is improved, and the source code of the C algorithm model is not required to be provided for a verifier, so that the confidentiality of the algorithm code is ensured.
The second embodiment of the chip algorithm module verification method based on the C algorithm model provided in the present application is described in detail below. The second embodiment is described in detail with reference to the practical application, and the coverage collector is added to the first embodiment.
The coverage collector has the main functions of: performing coverage rate analysis, and determining uncovered configuration according to an analysis result; and modifying constraint conditions in the verification case module according to the uncovered configuration, or creating a new verification case and sending the new verification case to the verification case module.
In the embodiment, the C model is connected with the verification environment through the DPI-C interface, and automatic operation of verification cases and automatic comparison of results are realized under the condition that files are not used as data transmission media. Referring to fig. 3 and 7, the implementation procedure of the second embodiment is as follows:
s301, expanding the C algorithm model into a C model.
The C algorithm model is expanded, related functional modules are added, and matching with hardware is realized while the C algorithm model can be ensured to independently run and be easy to debug, so that the C algorithm model is easy to integrate into a verification environment. The C algorithm model extension is shown in fig. 6, where the dashed boxes and dashed arrows represent optional functions that can be enabled or disabled by the dynamic switch control. The C model specifically comprises:
(1) And the test routine module is used for receiving the input parameters and taking the parameters as configuration information of the algorithm.
(2) And the excitation generator is used for generating corresponding excitation according to the configuration information and the algorithm requirement rule.
(3) And the C algorithm model, namely the existing verified C algorithm model, is used for receiving the configuration information and the excitation, and processing the excitation according to the rule required by the algorithm according to the configuration information to obtain a corresponding result which is used as a reference result of the algorithm.
(4) And the format conversion module is used for enabling the excitation generated by the excitation generator to be suitable for the C algorithm model, and the hardware needs to process multiple groups of excitation in parallel according to a specific mode so as to improve the performance of the hardware algorithm. The format conversion module is used for realizing conversion between excitation or results of different data formats, and comprises the following steps: a format conversion module 1 (i.e., the aforementioned first format conversion module) for converting the excitation format suitable for the C algorithm model into an excitation format suitable for hardware processing; a format conversion module 2 (i.e. the aforementioned second format conversion module) for converting the excitation format suitable for hardware processing into an excitation format suitable for the C algorithm model; the format conversion module 3 (i.e. the aforementioned third format conversion module) is configured to convert the result generated by the C algorithm model into a result consistent with the actual output format of the hardware.
(5) And the file storage module is used for respectively storing the excitation generated by the excitation generator and the reference result generated by the C algorithm model into an original excitation file and an original result file, and storing the excitation and the reference result which are converted by the format conversion module 1 and the format conversion module 3 and are consistent with the hardware processing format in the format conversion module into corresponding excitation files and result files.
It can be understood that the file storage module is mainly used for developing and verifying the initial debugging stage, and by comparing the excitation or the result before and after format conversion, whether the excitation is correctly injected into the chip algorithm module can be intuitively checked, and whether the result output by the chip algorithm module is consistent with the result stored in the file. After the verification environment is stable, in the process of carrying out regression testing through a large number of verification cases, the file storage module can be forbidden, so that a large number of files are prevented from being generated, and excessive extra storage space is occupied.
S302, compiling the C model.
Compiling a C model, and generating a cmodel.o file for verification and a cmodel_tool executable file for debugging functions, wherein the specific steps are as follows:
(1) All source code in the C model except the test routine is compiled and linked into a cmodel.o file, and the command is exemplified as follows:
gcc$(CFLAGS)-c stimulus.c
gcc$(CFLAGS)-c algo_core.c
gcc$(CFLAGS)-c convert.c
gcc$(CFLAGS)-c file_op.c
ld-r-o cmodel.o stimulus.o algo_core.o convert.o file_op.o
wherein, stinulus.c is an excitation generator source code file, algo_core.c is a C algorithm model source code file, overt.c is a format conversion module source code file, and file_op.c is a file storage module source code file.
(2) Compiling test routine codes, and linking the generated cmodel.o files to generate an executable file, wherein the command is exemplified as follows:
gcc$(CFLAGS)-c test.c
gcc-o cmodel_tool test.o cmodel.o
The test.c is a test routine code file, and the cmodel_tool is an executable file, and the executable file is mainly used for developing and verifying an initial debugging stage and debugging when a verification case with operation failure occurs in a later regression test process.
S303, creating a transmission interface between the C model and the verification environment.
I.e. develop a DPI-C interface, in particular as follows:
(1) A first DPI-C interface is developed for transferring configuration information from the verification environment to the stimulus generator and transferring the stimulus converted by the format conversion module 1 back to the DPI-C interface function of the verification environment, examples being as follows:
void dpi_gen_stimulus(const algo_config_t*cfg,svOpenArrayHandle hdata)；
the cfg is a pointer of a configuration information structure body algo_config_t type, configuration information is contained in the pointer, the pointer is transmitted to a C model by a System Verilog, hdata is a variable of an open array svOpenArrayHandle type, and the pointer is filled and stimulated by the C model and is transmitted back to the System Verilog.
(2) A second DPI-C interface is developed for communicating configuration information and stimuli to the C-algorithm model and driving the DPI-C interface function of which the C-algorithm model is to begin operation, examples being as follows:
void dpi_algo_start(const algo_config_t*cfg,const svOpenArrayHandle hdata)；
the cfg is a variable of the type algo_config_t of the configuration information structure body, configuration information is contained in the cfg, the hdata is a variable of the type of open array svOpenArrayHandle, and the cfg and the hdata are both transmitted to the C model by the System Verilog.
(3) A third DPI-C interface is developed for transferring the result converted by the format conversion module 3 from the C-model to the DPI-C interface of the verification environment, examples being as follows:
void dpi_get_ref_result(const algo_config_t*cfg,svOpenArrayHandle hresult)；
cfg is a variable of the type algo_config_t of the configuration information structure body, configuration information is contained in the cfg and is transmitted to a C model by the System Verilog, hresult is a variable of the type of open array svOpenArrayHandle, a reference result is filled by the C model, and the reference result is transmitted back to the System Verilog.
S304, integrating the C model into a verification environment.
The method comprises the following steps:
(1) Compiling a link C algorithm model to generate a library file, wherein the command is exemplified as follows:
gcc$(CFLAGS)-fPIC-c dpi_c_if.c
gcc-fPIC-shared-o dpi_c_lib.so dpi_c_if.o cmodel.o
wherein dpi_c_if.c is the DPI-C interface source code file and dpi_c_lib.so is the generated library file.
(2) The library file is linked when the verification use case is run, the following parameters are added in the command line parameters, and examples are as follows:
-sv_lib dpi_c_lib
s305, executing a verification workflow.
The structure diagram of the verification environment integrated with the C model is shown in fig. 6, and the verification flow is as follows:
(1) Generating configuration information: configuration information required by the algorithm is generated through reasonable constraint conditions in the verification environment, and the configuration information comprises information such as task type, data block number, data block size, random seed and the like.
(2) The configuration information is transferred to the stimulus generator, and the stimulus after format conversion is transferred to the verification case module: and packaging the generated configuration information according to a predefined data format, transmitting the configuration information to an incentive generator through the DPI-C interface as parameters of the DPI-C interface, starting the incentive generator to generate incentives, converting the incentives through a format conversion module 1, and transmitting the converted incentives back to a verification use case module.
(3) Injecting the stimulus into the chip algorithm module: and injecting the configuration information and the excitation into the chip algorithm module through corresponding interfaces respectively, and driving the chip algorithm module to start working.
(4) Transmitting excitation to model C: the monitor grabs configuration information and excitation from the input port of the chip algorithm module, transmits the configuration information and excitation to the C model through the DPI-C interface, and transmits the configuration information and excitation to the C algorithm model after conversion by the format conversion module 2.
(5) Comparing the reference result with the actual result output by the chip algorithm module: the checker obtains the reference result which is generated by the C algorithm model and converted by the format conversion module 3 through the DPI-C interface, and after receiving the actual result output by the chip algorithm module, the checker sequentially reads data from the reference result and compares the actual result output by the chip algorithm module with the reference result. If the verification cases are inconsistent, indicating that the verification cases fail to run; if all the results of the verification case are consistent with the reference result, the verification case is indicated to run successfully. And when all verification cases of the chip algorithm module are successfully operated, indicating that the chip algorithm module passes the verification.
(6) Collecting coverage information, and creating a corresponding verification case for the uncovered configuration: when the verification cases are successfully operated, the coverage rate information is recorded, when all the verification cases are successfully operated, the coverage rate collector checks which configurations are not covered by analyzing the coverage rate information, creates corresponding verification cases or modification constraint conditions for the uncovered configurations, then operates again and collects the coverage rate information, and improves the coverage rate through continuous iteration until all the configurations are covered.
Therefore, the chip algorithm module verification method based on the C algorithm model provided by the embodiment has at least the following four advantages:
the method has the advantages that 1, the C algorithm model is moderately matched with hardware, the C algorithm model is integrated into a UVM (universal verification methodology) verification environment through a DPI-C interface, and the System Verilog invokes the related functions of the C model, so that the automatic operation of verification cases and the on-line comparison of results are realized.
The advantage 2 is that files are not used as data transmission media of the verification case and the C model in regression test, namely excitation files and result files are not needed to be generated, and when the excitation range and the quantity of the algorithm are huge, the use files often occupy a large amount of extra storage space, and at the moment, the advantage of the embodiment is obvious.
The method has the advantages that 3, through collecting and analyzing coverage rate information, uncovered conditions can be found in time, constraint conditions can be conveniently modified or new verification cases can be created according to the uncovered conditions, the verification coverage rate is improved through continuous iteration, the completeness of verification is ensured, and the verification cannot be completed in a verification mode of generating incentives in advance.
Advantage 4, compile the C model independently into cmodel.o file, offer the verification personnel together with algorithm API interface, is used for capsulating DPI-C interface, therefore the development and debugging of the C model is independent of verifying the platform, the advantage brought is: on the one hand, the method has the advantage of layered development, the algorithm personnel is focused on the development of the algorithm, the verification personnel is focused on the development of the verification platform and the verification case, and if the output result of the chip algorithm module is inconsistent with the output result of the C algorithm model in the running process of the verification case, the algorithm personnel and the verification personnel can independently debug the respective modules based on the same configuration and excitation respectively, so that the problem of the modules per se can be quickly confirmed or eliminated; on the other hand, the C algorithm model source code need not be provided to the verifier, which has significant advantages in terms of code confidentiality when cooperating with a third party.
The following describes a chip algorithm module verification system based on a C algorithm model provided in the embodiments of the present application, and the chip algorithm module verification system based on a C algorithm model described below and the chip algorithm module verification method based on a C algorithm model described above may be referred to correspondingly.
The chip algorithm module verification system based on the C algorithm model of this embodiment, as shown in fig. 2, includes: the system comprises a C algorithm model, a chip algorithm module, a verification case module, an excitation generator, a first format conversion module, a second format conversion module, a third format conversion module and a checker.
The verification case module is used for randomly generating configuration information on line according to constraint conditions and transmitting the configuration information to the excitation generator through the first DPI-C interface;
the excitation generator is used for generating excitation according to the configuration information and transmitting the excitation to the first format conversion module, and the excitation after format conversion is transmitted to the verification case module through the first DPI-C interface;
the verification case module is used for transmitting the configuration information and the excitation after format conversion to the chip algorithm module respectively; the chip algorithm module is used for generating an actual result and transmitting the actual result to the inspector;
Capturing the configuration information and the excitation after format conversion from an input port of a chip algorithm model, transmitting the configuration information to a C algorithm model through a second DPI-C interface, transmitting the excitation after format conversion to a second format conversion module through the second DPI-C interface, and transmitting the excitation after format conversion to the C algorithm model again; the C algorithm model is used for generating a reference result, transmitting the reference result to the third format conversion module, and transmitting the reference result after format conversion to the checker through the third DPI-C interface;
the checker is used for judging whether the actual result is consistent with the reference result, if so, the checker indicates that the verification case is successful to run;
the first DPI-C interface, the second DPI-C interface and the third DPI-C interface are transmission interfaces between a C model and a verification environment; the C model is a model obtained by taking the C algorithm model as a core extension and comprises a C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module; c, compiling a model in advance independently;
the first format conversion module is used for converting the excitation into a data format suitable for hardware processing, the second format conversion module is used for converting the excitation into a data format suitable for C algorithm model processing, and the third format conversion module is used for converting the result into a data format suitable for hardware processing.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The foregoing has outlined rather broadly the more detailed description of the present application and the principles and embodiments of the present application have been presented in terms of specific examples, which are provided herein to assist in the understanding of the method and core concepts of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. The chip algorithm module verification method based on the C algorithm model is characterized by comprising the following steps of:
the verification case module randomly generates configuration information on line according to constraint conditions and transmits the configuration information to the excitation generator through a first DPI-C interface;
the excitation generator generates excitation according to the configuration information, transmits the excitation to the first format conversion module, and transmits the excitation after format conversion to the verification case module through the first DPI-C interface;
the verification case module transmits the configuration information and the excitation after format conversion to the chip algorithm module respectively; the chip algorithm module generates an actual result and transmits the actual result to the checker;
capturing the configuration information and the format-converted excitation from an input port of a chip algorithm model, transmitting the configuration information to a C algorithm model through a second DPI-C interface, transmitting the format-converted excitation to a second format conversion module through a second DPI-C interface, and transmitting the format-converted excitation to the C algorithm model again; the algorithm model C generates a reference result, the reference result is transmitted to a third format conversion module, and the reference result after format conversion is transmitted to the checker through a third DPI-C interface;
The checker judges whether the actual result is consistent with the reference result, if so, the checker indicates that the verification case is successful in operation;
the first DPI-C interface, the second DPI-C interface and the third DPI-C interface are transmission interfaces between a C model and a verification environment; the C model is a model obtained by taking the C algorithm model as a core extension and comprises a C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module; c, compiling a model in advance independently;
the first format conversion module is used for converting the stimulus into a data format suitable for hardware processing, the second format conversion module is used for converting the stimulus into a data format suitable for C algorithm model processing, and the third format conversion module is used for converting the result into a data format suitable for hardware processing.
2. The method as recited in claim 1, further comprising:
when the actual result is inconsistent with the reference result, starting a file storage function through a dynamic switch;
storing the excitation after format conversion into an excitation file; saving the reference result after format conversion into a reference result file;
Saving the actual result into an actual result file;
and repeating the verification process according to the excitation file, the reference result file and the actual result file, and positioning the problem.
3. The method of claim 2, wherein the format-converted stimulus is saved to a stimulus file; storing the format-converted reference result into a reference result file, wherein the method comprises the following steps:
storing the original excitation and the excitation after format conversion into an original excitation file and an excitation file respectively; respectively storing the original reference result or the reference result after format conversion into an original reference result file and a reference result file;
judging whether the format conversion of the excitation is normal or not according to the original excitation file and the excitation file; and judging whether the format conversion of the reference file is normal or not according to the original reference result file and the reference result file.
4. The method of claim 1, wherein the verification case module randomly generates configuration information on-line according to a constraint condition, comprising:
the verification use case module randomly generates configuration information on line according to constraint conditions, wherein the configuration information comprises any one or more of the following: task type, data type, number of data blocks, data block size, random seed.
5. The method of claim 1, further comprising, prior to the verifying the use-case module randomly generating configuration information online according to a constraint:
expanding the C algorithm model into a C model;
compiling the model C;
creating a transmission interface between the C model and the verification environment;
the C model is integrated into the verification environment.
6. The method of claim 5, wherein compiling the C model comprises:
compiling all source codes except the test routine in the C model and linking the source codes into target files, compiling the codes of the test routine, and linking the target files to generate executable files.
7. The method of claim 5, wherein creating a transport interface between the C-model and the verification environment comprises:
creating a DPI-C interface used for transmitting configuration information from the verification case module to the incentive generator, and transmitting the incentive after format conversion from the first format conversion module to the verification case module to obtain a first DPI-C interface;
creating a DPI-C interface for transmitting configuration information from an input port of the algorithm module chip to the C algorithm model, and transmitting the excitation after format conversion from the input port of the algorithm module chip to a second format conversion module to obtain a second DPI-C interface;
And creating a DPI-C interface for transmitting the reference result after format conversion from a third format conversion module to an inspector, and obtaining a third DPI-C interface.
8. The method of claim 5, wherein integrating the C-model into the verification environment comprises:
compiling a link C algorithm model to generate a library file; and when the verification use case is operated, linking the library file, and adding target parameters into the command line parameters.
9. The method of any one of claims 1-8, further comprising:
the coverage rate collector performs coverage rate analysis, and determines uncovered configuration according to analysis results; and modifying constraint conditions in the verification case module according to the uncovered configuration, or creating a new verification case and sending the new verification case to the verification case module.
10. A chip algorithm module verification system based on a C algorithm model, comprising: the system comprises a C algorithm model, a chip algorithm module, a verification case module, an excitation generator, a first format conversion module, a second format conversion module, a third format conversion module and a checker;
the verification case module is used for randomly generating configuration information on line according to constraint conditions and transmitting the configuration information to the excitation generator through a first DPI-C interface;
The excitation generator is used for generating excitation according to the configuration information, transmitting the excitation to the first format conversion module, and transmitting the excitation after format conversion to the verification case module through the first DPI-C interface;
the verification case module is used for transmitting the configuration information and the excitation after format conversion to the chip algorithm module respectively; the chip algorithm module is used for generating an actual result and transmitting the actual result to the inspector;
capturing the configuration information and the format-converted excitation from an input port of a chip algorithm model, transmitting the configuration information to a C algorithm model through a second DPI-C interface, transmitting the format-converted excitation to a second format conversion module through a second DPI-C interface, and transmitting the format-converted excitation to the C algorithm model again; the C algorithm model is used for generating a reference result, transmitting the reference result to the third format conversion module, and transmitting the reference result after format conversion to the checker through the third DPI-C interface;
the checker is used for judging whether the actual result is consistent with the reference result, if so, the check is used for indicating that the verification case is successful to run;
the first DPI-C interface, the second DPI-C interface and the third DPI-C interface are transmission interfaces between a C model and a verification environment; the C model is a model obtained by taking the C algorithm model as a core extension and comprises a C algorithm model, an excitation generator, a first format conversion module, a second format conversion module and a third format conversion module; c, compiling a model in advance independently;
The first format conversion module is used for converting the stimulus into a data format suitable for hardware processing, the second format conversion module is used for converting the stimulus into a data format suitable for C algorithm model processing, and the third format conversion module is used for converting the result into a data format suitable for hardware processing.
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