CN110618929A - Verification platform and verification method of symmetric encryption algorithm based on UVM - Google Patents
Verification platform and verification method of symmetric encryption algorithm based on UVM Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3664—Environments for testing or debugging software
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3688—Test management for test execution, e.g. scheduling of test suites
Abstract
The invention discloses a verification platform of a symmetric encryption algorithm based on UVM, which comprises a top layer, a test case and a verification environment. The verification environment is derived from uvm _ env, integrates and connects required components to work, and comprises a register model, a sequence generator, a sequence, transaction data, a driver, a coverage rate statistic device, an input monitor, an output monitor, a score board, a reference model, an input interface and an output interface, wherein: generating transaction data through the sequence, transmitting the random excitation to the reference model and the DUT module through driving, then transmitting the operation results of the reference model and the DUT module to the scoring board, and performing data comparison and judging on the functional verification condition by the scoring board, and performing coverage rate check through the coverage rate model to ensure that the functional verification simulation is normal. The invention does not limit the symmetric encryption algorithm, can realize the function verification of various encrypted symmetric algorithms, and the verification platform has good reusability and reusability.
Description
Technical Field
The invention relates to the field of cryptographic algorithm verification, in particular to a verification platform and a verification method of a symmetric encryption algorithm based on UVM.
Background
The current integrated circuit industry is rapidly increased in China, the manufacturing technology of integrated circuits is continuously developed, the integration level of chips is rapidly improved, the gate level scale of the chips is developed from ten thousand gate levels to millions of gate levels at present many years, and the functional complexity which can be realized on the chips even exceeds the development speed of the integration level predicted by the moore's law. Due to the rapid increase of the functional complexity of the chip, the verification work occupies most of the whole development period, and the time to market of the chip is seriously influenced.
The traditional verification method is that a simple verification platform is built by using verilog language, the verification structure lacks hierarchical design, and meanwhile, the project verification engineering is poor in reusability, so that development and maintenance among projects are difficult and the reusability is low. The traditional verification method can not meet the verification requirement of the current design more and more, and the appearance of the universal verification methodology aims to improve the verification capability of the current verification method.
The universal verification methodology introduced a new verification language, SystemVerilog (SV). The SV comprises RTL design, test platform design, assertion and coverage rate statistical functions, and the general verification methodology is a development set of SV language and comprises a plurality of verification function objects to realize a plurality of verification methods. By using the universal verification methodology, the module verification reusability can be enhanced, the chip development efficiency can be improved, and the chip development period can be shortened.
Currently, there are three general verification methodologies based on systemveilog: VMM, OVM, and UVM. Wherein the UVM inherits most of the advantages of OVM while adopting register solution RAL of Synopsys in VMM. UVM overcomes the defects of OVM and VMM, represents the development direction of the current general verification methodology, and is the mainstream general verification methodology in the industry at present.
The conventional verification symmetric cryptographic algorithm is mainly operated on an FPGA hardware platform for functional verification through a verilog writing verification platform method. Meanwhile, the method is suitable for directional testing, and non-directional testing is difficult to perform through various different test vectors, so that the efficiency of verifying the symmetric encryption algorithm is low, and reuse cannot be realized.
Disclosure of Invention
The invention aims to provide a verification platform of a symmetrical encryption algorithm based on UVM, which improves the verification capability and reusability of the symmetrical encryption algorithm.
A further object of the invention is a method for verification of a UVM-based symmetric encryption algorithm.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a verification platform of a symmetrical encryption algorithm based on UVM comprises a top layer, a test case and a verification environment, the verification work of the symmetrical encryption algorithm is completed through the combined connection of three modules, the verification environment is derived from UVM _ env, and required components are integrally connected for working, wherein: the top layer comprises a DUT module, data connection is carried out between the DUT module and the test case, meanwhile, the DUT module and the verification environment carry out operation result comparison, and the purpose of verifying the DUT module is achieved; the verification environment can realize the connection and data transmission of each component and complete the system verification function.
The top layer carries out function simulation verification on a symmetric encryption algorithm (DUT) by calling a test case, and carries out function simulation through a large amount of non-directional tests and a small amount of directional tests of the test case, so that various functions and operations of the DUT are ensured to be normal. The test cases comprise a large number of non-directional tests and a small number of directional tests, and meanwhile, a large number of constraints are set, so that a large number of verification verifications are provided for DUT verification, the coverage rate of verification functions is close to 100%, and the verification effect of the verification platform is determined to a large extent by the number of the test cases.
Preferably, the components include a register model, a sequencer, a sequence, transaction data, a driver, a coverage statistic, an input monitor, an output monitor, a scoreboard, a reference model, an input interface, and an output interface, wherein:
the register model (register model) is derived from uvm _ reg, stable and quick communication between a driver and a reference model in a verification environment can be realized, and the operation on the reference model can be quickly realized by configuring the register model;
the sequence generator (sequence) is derived from uvm _ sequence, stores and packs the sequence and sends out, when the sequence data is needed, the sequence generator will check whether the sequence needs to be sent, if yes, the sequence is sent directly, otherwise, the sequence is generated and sent;
the sequence (sequence) is derived from uvm _ sequence, the sequence is the source of the verification platform excitation generation, and different sequences are only required to be set as default sequences of a sequence generator in a test case to generate different verification excitations;
the transaction data (transaction) is derived from uvm _ sequence _ item, and comprises 2 input variables and 2 output variables of a symmetric encryption algorithm module, wherein the input variables are random data, and the data plus a keyword rand ensures the randomness of verification excitation;
the driver is derived from uvm _ driver, obtains transaction data required by verification by applying to the sequencer, and then transmits the transaction data to the DUT module and the reference model through the interface so as to drive the DUT module and the reference model to perform function simulation;
the coverage rate statistics device (coverage) is derived from uvm _ subscriber, completes the statistics of the coverage rate of the functional coverage point through a functional coverage group (coveragegroup) and a sampling function sample (), and collects all the occurred values or changed conditions of data or expressions;
the input monitor (in _ monitor) is derived from uvm _ monitor, the input monitor extracts transaction data through an interface and then transmits the transaction data to the reference model and the coverage rate statistic device to ensure that the feedback of the image is obtained by verification;
the output monitor (out _ monitor) is derived from uvm _ monitor and is used for detecting the output result of the DUT module, after the computation of the DUT module is finished, effective information of the computation result is put into transaction data, then the transaction data is transmitted to the reference model for comparison, and whether the DUT module correctly outputs the computation data is verified;
the scoring board (scoreboard) is derived from uvm _ scoreboard and is used for comparing the operation output result of the DUT module with the calculation output result of the reference model and judging whether the operation of the current DUT module is normal or not according to the comparison result;
the reference model (reference model) is a behavior model for simulating the DUT module, and the reference model adopts a high-level programming language to build a functional model of the DUT, so that the calculation work of the DUT module can be completed quickly; the reference model is not derived from the UVM general verification methodology, but is an indispensable component of the present verification platform
The input interface (interface _ in) is a channel for transmitting data to the DUT module by the verification platform, because the code of the DUT is written by using a hardware description language Verilog and belongs to a static example; and the UVM general verification methodology is an abstract object on the basis of an SV language and belongs to a dynamic instance. Therefore, the two data cannot be directly connected, so that an input interface is needed to transmit the data from the verification platform to the DUT module;
the output interface (interface _ out) is a channel for transmitting data to the verification platform by the DUT module, because the code of the DUT is written by using a hardware description language Verilog and belongs to a static example; and the UVM general verification methodology is an abstract object on the basis of an SV language and belongs to a dynamic instance. The two data cannot be directly connected so an output interface is required to transfer the data from the DUT module to the verification platform.
Preferably, the register model comprises a control register, a status register, an input register and an output register.
Preferably, the sequence comprises a random sequence, a special sequence and a directional sequence, so that the verification of the verification platform is more comprehensive.
Preferably, the coverage statistics are coverage models built by SV language.
Preferably, the input monitor transmits transaction-like data to the reference model and the coverage statistics via a first-in-first-out storage area FIFO or port.
Preferably, the output monitor transmits the transaction class data to the reference model via a first-in-first-out storage area FIFO.
Preferably, the reference model and the score counting board perform data communication through a first-in first-out storage area FIFO, so that data disorder is prevented from being generated when a large amount of data are compared, the verification result of the verification platform is prevented from being influenced, meanwhile, the method can ensure that data verification does not need to wait, and the possibility of system downtime is reduced.
Preferably, the reference model is built by adopting C language, a test algorithm is completed before verification, an expected result can be obtained only by directly transmitting data to carry out operation in the later verification process, and meanwhile, a C code function can be conveniently called in SV language through a DPI interface.
A verification method of a UVM-based symmetric encryption algorithm verification platform is applied to the verification platform and comprises the following steps:
s1: building a verification platform according to a preset structure, initializing each component of the UVM verification platform and starting the verification platform through a run _ test statement;
s2: the drive of the verification platform sends a sequence request to the sequencer, then the sequencer drives a sequence to acquire transaction data, the sequencer sends the transaction data to the drive, then the drive data transmits the data to the DUT module through the input interface, and finally the DUT module is driven to carry out operation;
s3: after the operation of the DUT module is finished, transmitting the result to an output monitor of the verification platform through an output interface, converting the result into transaction data through the output monitor, and then transmitting the transaction data to a score board through FIFO for storage;
s4: the reference model processes the transaction data acquired from the input monitor by using a model function of C language, obtains expected output through calculation, transmits the calculated data to the score board module for comparison, and obtains a simulation verification result according to the comparison result;
s5: and establishing a functional coverage rate model through a coverage rate statistics device to test the verification effect of the verification platform, then connecting the functional coverage rate model with the UVM verification platform to perform data sampling, and finally outputting a coverage rate report through software. Through checking the coverage rate report, a designer can modify the test cases or add constraint conditions in time so as to completely verify each function of the DUT module
Compared with the prior art, the technical scheme of the invention has the beneficial effects that:
according to the invention, the DUT module is called through the top layer to perform function simulation verification, and function simulation is performed through a large amount of non-directional tests and a small amount of directional tests of the test cases, so that each function and operation of the DUT are ensured to be normal.
Drawings
FIG. 1 is a schematic diagram of a verification platform according to the present invention.
Fig. 2 is a schematic flow chart of a verification method in the embodiment.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the patent;
for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product;
it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
Example 1
The embodiment provides a verification platform based on a UVM symmetric encryption algorithm, as shown in fig. 1, which includes a top layer, test cases, and a verification environment, where the verification environment is derived from UVM _ env, and integrates and connects required components for work, where: the top layer comprises a DUT module, data connection is carried out between the DUT module and the test case, meanwhile, the DUT module and the verification environment carry out operation result comparison, and the purpose of verifying the DUT module is achieved; the verification environment can realize the connection and data transmission of each component and complete the system verification function.
The components include a register model, a sequencer, a sequence, transaction data, a driver, a coverage statistics engine, an input monitor, an output monitor, a scoreboard, a reference model, an input interface, and an output interface, wherein:
the register model (register model) is derived from uvm _ reg, stable and quick communication between a driver and a reference model in a verification environment can be realized, and the operation on the reference model can be quickly realized by configuring the register model;
the sequence generator (sequence) is derived from uvm _ sequence, stores and packs the sequence and sends out, when the sequence data is needed, the sequence generator will check whether the sequence needs to be sent, if yes, the sequence is sent directly, otherwise, the sequence is generated and sent;
the sequence (sequence) is derived from uvm _ sequence, and different sequences are only required to be set as default sequences of the sequence generator in the test case to generate different verification stimuli;
the transaction data (transaction) is derived from uvm _ sequence _ item, and comprises 2 input variables and 2 output variables of a symmetric encryption algorithm module, wherein the input variables are random data, and data and a keyword rand;
the driver is derived from uvm _ driver, and the driver applies for transaction data required by verification to the sequencer and then transmits the transaction data to the DUT module and the reference model through the interface;
the coverage rate statistics device (coverage) is derived from uvm _ subscriber, completes the statistics of the coverage rate of the functional coverage point through a functional coverage group (coveragegroup) and a sampling function sample (), and collects all the occurred values or changed conditions of data or expressions;
the input monitor (in _ monitor) is derived from uvm _ monitor, the input monitor extracts transaction data through an interface and then transmits the transaction data to a reference model and a coverage rate statistic device to ensure that the verification is fed back;
the output monitor (out _ monitor) is derived from uvm _ monitor, after the DUT module finishes calculating, effective information of a calculation result is put into transaction data, then the transaction data is transmitted to a reference model for comparison, and whether the DUT module correctly outputs the calculation data is verified;
the scoring board (scoreboard) is derived from uvm _ scoreboard and is used for comparing the operation output result of the DUT module with the calculation output result of the reference model and judging whether the operation of the current DUT module is normal or not according to the comparison result;
the reference model (reference model) is a behavior model for simulating a DUT module, and the model adopts a high-level programming language to build a functional model of the DUT;
the input interface (interface _ in) is a channel for transmitting data to the DUT module by the verification platform;
the output interface (interface _ out) is a channel for the DUT module to transmit data to the verification platform.
The register model includes a control register, a status register, an input register, and an output register.
The sequences include random sequences, special sequences, and directed sequences.
The coverage rate statistic device is a coverage rate model established through an SV language.
The input monitor transmits the transaction type data to the reference model and the coverage rate statistics device through a first-in first-out storage area FIFO or a port.
The output monitor transmits the transaction type data to the reference model through the first-in first-out storage area FIFO.
And the reference model and the score counting board are in data communication through a first-in first-out storage area FIFO.
And the reference model is built by adopting C language, and a test algorithm is completed before verification.
In a specific implementation, the verification platform according to the UVM-based symmetric encryption algorithm, as shown in fig. 2, includes the following steps:
s10: initializing each component of a verification platform of a symmetric encryption algorithm and starting the verification platform by using a run _ test statement;
s20: starting a preset test case, generating a large amount of random transaction data, special transaction data and oriented transaction data through a sequence, and providing complete verification excitation for a verification platform;
s30: judging whether the current test case runs completely, if the test case runs completely, performing coverage constraint check, otherwise, running functional simulation verification, respectively sending the test sequence to the reference model and the DUT module, and performing related functional operation;
s40: after functional simulation verification, transmitting a calculation result of the reference model and a calculation result of the DUT module to a scoring board through a port and an interface respectively;
s50: and the score board compares the calculation result of the reference model with the calculation result of the DUT module, indicates that the functional verification is correct when the calculation result of the DUT module is consistent with the calculation result of the reference model, and continuously judges whether the test case operation is finished. If the operation result of the DUT module is inconsistent with the calculation result of the reference model, indicating that the function verification is wrong, and performing coverage rate constraint check at the moment;
s60: and when the score board inspection error occurs or the test case is completely run, performing coverage rate constraint inspection, and if the current coverage rate constraint meets a preset coverage rate condition, successfully verifying the platform. If the current coverage rate constraint does not meet the preset coverage rate condition, judging whether the current coverage rate is improved;
s70: when judging whether the coverage rate is improved or not, if the coverage rate is improved, increasing a test case or modifying constraint conditions, and if the coverage rate cannot be improved or is not maintained, increasing a directional test;
s80: and after the test cases are added or the constraint conditions are modified, if quantitative tests are added, judging that the test cases are completely operated.
The same or similar reference numerals correspond to the same or similar parts;
the terms describing positional relationships in the drawings are for illustrative purposes only and are not to be construed as limiting the patent;
it should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A verification platform based on UVM symmetric encryption algorithm is characterized by comprising a top layer, test cases and a verification environment, wherein the verification environment is derived from UVM _ env and integrates and connects required components for working, and the verification platform comprises: the top layer comprises a DUT module, data connection is carried out between the DUT module and the test case, meanwhile, the DUT module and the verification environment carry out operation result comparison, and the purpose of verifying the DUT module is achieved; the verification environment can realize the connection and data transmission of each component and complete the system verification function.
2. A verification platform for UVM based symmetric cryptographic algorithms according to claim 1, wherein the components include register models, sequencers, sequences, transaction data, drivers, coverage statistics, input monitors, output monitors, scoreboards, reference models, input interfaces and output interfaces, wherein:
the register model (register model) is derived from uvm _ reg, stable and quick communication between a driver and a reference model in a verification environment can be realized, and the operation on the reference model can be quickly realized by configuring the register model;
the sequence generator (sequence) is derived from uvm _ sequence, stores and packs the sequence and sends out, when the sequence data is needed, the sequence generator will check whether the sequence needs to be sent, if yes, the sequence is sent directly, otherwise, the sequence is generated and sent;
the sequence (sequence) is derived from uvm _ sequence, and different sequences are only required to be set as default sequences of the sequence generator in the test case to generate different verification stimuli;
the transaction data (transaction) is derived from uvm _ sequence _ item, and comprises 2 input variables and 2 output variables of a symmetric encryption algorithm module, wherein the input variables are random data, and data and a keyword rand;
the driver is derived from uvm _ driver, and the driver applies for transaction data required by verification to the sequencer and then transmits the transaction data to the DUT module and the reference model through the interface;
the coverage rate statistics device (coverage) is derived from uvm _ subscriber, completes the statistics of the coverage rate of the functional coverage point through a functional coverage group (coveragegroup) and a sampling function sample (), and collects all the occurred values or changed conditions of data or expressions;
the input monitor (in _ monitor) is derived from uvm _ monitor, the input monitor extracts transaction data through an interface and then transmits the transaction data to a reference model and a coverage rate statistic device to ensure that the verification is fed back;
the output monitor (out _ monitor) is derived from uvm _ monitor, after the DUT module finishes calculating, effective information of a calculation result is put into transaction data, then the transaction data is transmitted to a reference model for comparison, and whether the DUT module correctly outputs the calculation data is verified;
the scoring board (scoreboard) is derived from uvm _ scoreboard and is used for comparing the operation output result of the DUT module with the calculation output result of the reference model and judging whether the operation of the current DUT module is normal or not according to the comparison result;
the reference model (reference model) is a behavior model for simulating a DUT module, and the model adopts a high-level programming language to build a functional model of the DUT;
the input interface (interface _ in) is a channel for transmitting data to the DUT module by the verification platform;
the output interface (interface _ out) is a channel for the DUT module to transmit data to the verification platform.
3. A verification platform for a UVM based symmetric encryption algorithm according to claim 2 wherein the register model includes a control register, a status register, an input register and an output register.
4. An authentication platform for a UVM based symmetric encryption algorithm according to claim 2 wherein the sequences include random sequences, special sequences and directed sequences.
5. A verification platform for UVM based symmetric encryption algorithms according to claim 2, characterized in that said coverage statistics are coverage models built by SV language.
6. An authentication platform for a UVM based symmetric cryptographic algorithm according to claim 2, characterized in that the input monitor transmits transaction class data to the reference model and the coverage statistics through a first-in-first-out storage area FIFO or port.
7. An authentication platform for a UVM based symmetric encryption algorithm according to claim 2 wherein the output monitor transfers transaction class data to the reference model via a first-in-first-out storage area FIFO.
8. An authentication platform for a UVM based symmetric encryption algorithm according to claim 2 wherein the reference model is in data communication with the score-counting board via a first-in-first-out storage area FIFO.
9. The verification platform of the UVM-based symmetric encryption algorithm according to claim 8, wherein the reference model is constructed in C language and a test algorithm is completed before verification.
10. A verification method of a UVM-based symmetric encryption algorithm verification platform, wherein the verification method is applied to the verification platform of any one of claims 2 to 9, and the verification method comprises the following steps:
s1: building a verification platform according to a preset structure, initializing each component of the UVM verification platform and starting the verification platform through a run _ test statement;
s2: the drive of the verification platform sends a sequence request to the sequencer, then the sequencer drives a sequence to acquire transaction data, the sequencer sends the transaction data to the drive, then the drive data transmits the data to the DUT module through the input interface, and finally the DUT module is driven to carry out operation;
s3: after the operation of the DUT module is finished, transmitting the result to an output monitor of the verification platform through an output interface, converting the result into transaction data through the output monitor, and then transmitting the transaction data to a score board through FIFO for storage;
s4: the reference model processes the transaction data acquired from the input monitor by using a model function of C language, obtains expected output through calculation, transmits the calculated data to the score board module for comparison, and obtains a simulation verification result according to the comparison result;
s5: establishing a functional coverage rate model through a coverage rate statistics device to test the verification effect of a verification platform, then connecting the functional coverage rate model with a UVM verification platform to perform data sampling, and finally outputting a coverage rate report; by viewing the coverage rate report, the test cases can be modified or the constraint conditions can be added in time so as to completely verify the functions of the DUT module.
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