CN117541896B

CN117541896B - UVM-based rasterization module verification system, method and storage medium

Info

Publication number: CN117541896B
Application number: CN202410026348.1A
Authority: CN
Inventors: 江靖华; 张坚
Original assignee: Shenliu Micro Intelligent Technology Shenzhen Co ltd
Current assignee: Shenliu Micro Intelligent Technology Shenzhen Co ltd
Priority date: 2024-01-09
Filing date: 2024-01-09
Publication date: 2024-04-09
Anticipated expiration: 2044-01-09
Also published as: CN117541896A

Abstract

The application discloses a rasterization module verification system, a rasterization module verification method and a storage medium based on UVM, comprising the following steps: the preprocessing component is used for converting the primitive data before processing into the primitive data after processing which can be used by the hardware rasterization module to be detected through a preprocessing function; the proxy component is used for simultaneously providing the register configuration data and the processed primitive data as inputs to the hardware rasterization module to be tested and the reference model, and acquiring an actual processing result and a reference processing result through a bus interface; and the scoreboard is used for carrying out similarity analysis on the actual processing result and the reference processing result to obtain a comparison result. The data meeting the format requirement can be input to the to-be-detected rasterization module through preprocessing, so that the to-be-detected rasterization module can be driven normally; the technical problem that the performance of the to-be-detected rasterization module cannot be judged through accurate comparison due to unordered output fragments in the prior art can be solved through similarity comparison, and the reliability of the rasterization module verification is improved.

Description

UVM-based rasterization module verification system, method and storage medium

Technical Field

The application relates to the technical field of UVM verification and GPU, in particular to a system, a method and a storage medium for verifying a rasterization module based on UVM.

Background

With the continuous development of technology, the rendering technology based on GPU is more widely applied, and common 3D animation, games, autopilot and the like are realized by the rendering technology of a computer. The rendering process can be basically broken down into two main tasks: visibility and coloration. Rasterization can be said to be one way to solve the visibility problem. Visibility mainly refers to what parts of a three-dimensional object are visible and what parts are obscured by other objects, resulting in the invisibility of those parts. Along with the increase of the complexity and the continuous perfection of the functions of the GPU chip, the requirements on chip verification are higher and higher, and the proportion of verification work time to the whole design period is also greatly increased.

The verification process of the traditional GPU rasterization module is mainly to write testbenches through Verilog, various test vectors are troublesome to generate and cannot be reused, and the traditional verification method cannot meet the requirements of the complex design of the traditional rasterization module.

Disclosure of Invention

The main object of the present application is to provide a system, a method and a storage medium for verifying a rasterized module based on UVM, which can solve the technical problem that the rasterized module cannot be verified conveniently and effectively in the prior art.

To achieve the above object, a first aspect of the present application provides a UVM-based rasterized module authentication system, the authentication system comprising: the UVM verification platform is connected with the hardware rasterization module to be tested;

the UVM verification platform comprises an agent component, a bus interface, a reference model, a preprocessing component and a scoreboard;

the agent component is used for acquiring and analyzing the sequence transaction, acquiring register configuration data and pre-processing primitive data, and transmitting the pre-processing primitive data to the preprocessing component;

the preprocessing component is used for converting each pre-processed primitive data into preprocessed primitive data which can be used by the hardware rasterization module to be detected through a preprocessing function;

the proxy component is also used for simultaneously taking the register configuration data and the preprocessed primitive data as the input of the hardware rasterization module to be tested and the reference model, respectively transmitting and providing the input of the hardware rasterization module to be tested and the input of the reference model, acquiring the actual processing result of the hardware rasterization module to be tested for executing the rasterization logic operation according to the register configuration data and the preprocessed primitive data through the bus interface, and acquiring the reference processing result of the reference model for executing the rasterization logic operation according to the register configuration data and the preprocessed primitive data;

And the scoreboard is used for carrying out similarity analysis on the obtained actual processing result and the obtained reference processing result to obtain a comparison result.

To achieve the above object, a second aspect of the present application provides a method for verifying a UVM-based rasterization module, including:

acquiring and analyzing sequence transactions, and acquiring register configuration data and primitive data before processing;

converting the primitive data before each process into the primitive data after the pretreatment which can be used by the hardware rasterization module to be tested through a pretreatment function;

the register configuration data and the preprocessed primitive data are simultaneously used as the input of the hardware rasterization module to be tested and the reference model, and are respectively transmitted and provided for the hardware rasterization module to be tested and the reference model;

acquiring an actual processing result of executing the rasterization logic operation by the hardware rasterization module to be tested according to the register configuration data and the preprocessed primitive data;

acquiring a reference processing result of the reference model for executing the rasterization logic operation according to the register configuration data and the preprocessed primitive data;

and carrying out similarity analysis on the obtained actual processing result and the reference processing result to obtain a comparison result.

To achieve the above object, a third aspect of the present application provides a computer-readable storage medium storing a computer program, which when executed by a processor, causes the processor to perform the steps of:

To achieve the above object, a fourth aspect of the present application provides a computer device, including a memory and a processor, the memory storing a computer program, which when executed by the processor causes the processor to perform the steps of:

By adopting the embodiment of the application, the method has the following beneficial effects:

the data meeting the format requirement can be input to the to-be-detected rasterization module through preprocessing, so that the to-be-detected rasterization module can be normally driven, and rasterization operation is executed; the preprocessing is combined with the UVM platform, so that randomized configuration data can be realized, test vectors of different scenes are generated, the integrity of function verification of the rasterization module is ensured, and the verification efficiency of the rasterization module is greatly improved; the technical problem that the performance of the to-be-detected rasterization module cannot be judged through accurate comparison due to unordered output fragments in the traditional method can be solved through similarity comparison, and the reliability of the rasterization module verification is improved; the rasterization verification platform constructed based on the UVM verification methodology is clear in structure and high in portability and reusability, and the problems that the conventional Verilog is complicated in generating various test vectors and cannot be reused in writing testbenchmarks are solved; and UVM object-oriented programming, constraint random excitation, function coverage rate checking, assertion and other attributes are easy to locate problems of the to-be-detected rasterization module.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Wherein:

FIG. 1 is a block diagram of a UVM-based rasterized module authentication system in an embodiment of the present application;

FIG. 2 is a flowchart of a method for verifying a UVM-based rasterization module in an embodiment of the present application;

fig. 3 is a block diagram of a computer device in an embodiment of the invention.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

As shown in fig. 1, in one embodiment, a UVM-based rasterized module authentication system is provided that includes: the UVM verification platform 10 is connected with the hardware rasterization module 20 to be tested;

the UVM verification platform 10 includes a proxy component 11, a reference model 12, a preprocessing component 13, a scoreboard 14, and a bus interface 15;

the agent component 11 is configured to acquire and parse the sequence transaction, acquire register configuration data and primitive data before processing, and transmit the primitive data before processing to the preprocessing component 13;

the preprocessing component 13 is configured to convert each pre-processed primitive data into preprocessed primitive data that can be used by the hardware rasterization module to be tested through a preprocessing function;

the proxy component 11 is further configured to simultaneously use the register configuration data and the preprocessed primitive data as inputs of the hardware to be tested rasterizing module and the reference model 12, respectively transmit the inputs to the hardware to be tested rasterizing module and the reference model 12, acquire an actual processing result of the hardware to be tested rasterizing module for executing the rasterizing logic operation according to the register configuration data and the preprocessed primitive data through the bus interface 15, and acquire a reference processing result of the reference model 12 for executing the rasterizing logic operation according to the register configuration data and the preprocessed primitive data;

And the scoreboard 14 is used for carrying out similarity analysis on the obtained actual processing result and the reference processing result to obtain a comparison result.

Specifically, the UVM-based rasterization module verification system is a UVM verification system for GPU rasterization module verification. The UVM verification platform 10 includes various UVM components, for example, a proxy component 11, a reference model 12, a preprocessing component 13, a scoreboard 14, a bus interface 15, and the like, and the UVM components may be connected and communicate by way of ports port and fifo, and the like, without being limited thereto.

The DUT module under test includes a hardware under test rasterizer module 20. A rasterization module for rasterizing (raster): the GPU graphics rendering module processes the vector graphics into a series of pixel points.

When different test cases are operated, an authentication Environment (ENV) is instantiated first, all the related components are packaged in the authentication environment for connection and instantiated together, so that the purposes of verifying different scenes can be achieved by only modifying the sequences of the different test cases without changing fixed components.

The authentication Environment (ENV) in the present authentication platform is derived from the UVM _env class for encapsulating the stationary components of the UVM authentication platform 10, resembling a container; when running different test cases (testcase), the verification Environment (ENV) is only needed to be instantiated in the different test cases (testcase), so that the instantiation of the fixed components can be realized, and the components in the verification platform can be connected with each other. The components of the verification Environment (ENV) instantiation of the present solution have a proxy component 11 and a scoreboard 14 (SCB), wherein each proxy component 11 internally encapsulates one or more of a driver (driver), a monitor (monitor), and a Sequencer (SQR), among others.

The test cases (testcase) in the verification platform are derived from uvm _test class and are mainly responsible for configuring the verification platform by designating different sequences to generate different test cases (testcase), and the different test cases (testcase) realize specific test items for each function, so that each function verification of the rasterization module is realized, and possible problems are found.

The testbench top layer (test_top) in the verification platform is positioned at the top layer of the whole verification platform, DUT code files to be tested and UVM component code files are added into the top layer, clock and reset signals are generated, interfaces, the verification platform and a rasterization module are declared and instantiated, and the verification platform and the rasterization module are connected, initialized and the like.

The bus interface 15 is a system interface, and the UVM verification platform 10 of this embodiment may perform data communication with the hardware rasterization module 20 to be tested through one or more of the AXI bus interface 15, the HWPE bus interface 15, the HCI bus interface 15, and the like.

The system interface in the verification platform is a bridge for data interaction between the verification platform and the hardware to be tested rasterization module 20, and after the DUT and the system interface are instantiated in the testbench top layer (test_top), the data interaction can be directly performed in a parameter calling mode.

The proxy component 11 in the present verification platform is derived from the uvm agent class and is a package for one or more components of a driver (driver), a monitor (monitor), and a Sequencer (SQR). Each proxy component 11 may constitute a separate small entity, the use of proxy components 11 greatly improving the reusability of the verification platform.

The proxy component 11 may request acquisition and parsing of sequential transactions from the sequencer through its encapsulated driver to obtain register configuration data and pre-processing primitive data. The processing component transmits the primitive data before processing to the preprocessing component 13, and the preprocessing component 13 performs format conversion on the primitive data before processing to obtain the primitive data after preprocessing.

The preprocessed primitive data may be repackaged or packed into sequential transactions awaiting invocation.

The method and the device verify that the sequence transaction or transaction class in the platform is derived from the uvm _sequence_item class, the input data or the output data of the rasterization module are packaged, the input variables are all set to random variables of the rand type, and the randomness of the initialization of the input variables is ensured.

The hardware to be tested rasterizer module (ras module) 20 inputs data in a specific format and therefore the present application incorporates a preprocessing component 13. The preprocessing component 13 comprises preprocessing functions that can transform the data. Specifically, the pre-processed primitive data is preprocessed to convert the pre-processed primitive data into an input format usable by the hardware to be tested rasterizer 20. For example, the primitive data before processing is converted into data of an input format such as 32bit or 64bit, which is not limited thereto.

Wherein the primitive data before processing includes one or more of position data (e.g., screen coordinates, etc.), vertex data (e.g., vertex attributes, etc.), primitive context information, etc.; the preprocessed primitive data includes: and the preprocessed position data, attribute data, primitive context information and other parameters.

The primitive context information, i.e., the primitive context structure, is used to describe the primitive.

The register list contains various configuration parameters, the values of which can be configured in the tb environment or manually defined, and the configuration data of the register can be obtained after the configuration is completed. The register configuration data may include, but is not limited to, openGL rasterization configuration parameters, primitive context length, whether to turn on bypass/sequence mode registers, input/output addresses, binary registers, etc.

The register stores some common parameter data or configuration data, such as the number of the primitive information needed by the placement of the rasterization module, so that the rasterization module can conveniently and directly take the corresponding primitive, the time for searching the primitive is reduced, the efficiency of the rasterization module for processing the primitive is improved, the data stored in the register cannot be too much, and most of the primitive data still needs to be issued to the rasterization module. The personalized parameter data, such as the color, coordinates and other primitive data of the triangle to be drawn, is sent to the rasterization module, and the size and the number of the triangle to be drawn can be stored in the register configuration data. Of course, the foregoing is merely illustrative, and the register configuration data and the primitive data are specifically set according to the actual application scenario, which is not limited in this application.

The proxy component 11 is further configured to obtain register configuration data and preprocessed primitive data from the obtained sequential transaction, and use the register configuration data and the preprocessed primitive data as inputs of the hardware rasterization module 20 to be tested and the reference model 12 at the same time.

The hardware to be tested rasterizing module 20 executes the rasterizing logic operation according to the preprocessed primitive data and the combined register configuration data, and obtains the actual processing result.

The reference model 12 may be a Cmodel reference model 12 written in C language, although other languages may be used, and the present application is not limited in this regard. Reference model 12 simulates the behavior of the GPU rasterizing module by software. The reference model 12 (Cmodel) in the present verification platform is a very important part of the UVM verification platform 10, which is a model simulating the behavior of the rasterization module, and the present verification platform adopts a C language to write a function, and the SystemVerilog can connect to a C code through a DPI interface.

The reference model 12 simulates the hardware under test rasterizing module 20, and performs a rasterizing logic operation according to the preprocessed primitive data and the combined register configuration data to obtain a reference processing result.

The UVM verification platform 10 may also package the actual processing results into sequential transactions for transmission to the scoreboard 14, and may also package the reference processing results into sequential transactions for transmission to the scoreboard 14.

The scoreboard 14 is used primarily for output comparison of the reference model 12 and the hardware-to-be-rasterized module. Scoreboards 14 (SCBs) in the present verification platform are derived from the uvm _scoreboard class for comparing the output of DUT modules under test to the expected value of the reference model 12 (Cmodel) output. The source of the scoreboard 14 (SCB) data is the output of the reference model 12 (Cmodel) and the output of the hardware under test rasterizer module 20 sampled by the output agent component.

Fragments output by the rasterization module have disorder, and output data cannot be compared sequentially according to a traditional comparison method. Based on this, the present application provides a similarity analysis and comparison mechanism, wherein the output of the reference model 12 and the output of the hardware to be tested rasterization module 20 are used as input data of the scoreboard 14, the scoreboard 14 calculates two sets of data by using a comparison script, and analyzes the similarity of the two sets of data, so as to finally obtain a similarity proportion of the data, and the similarity proportion does not meet the requirement and prompts error reporting information, thereby realizing an automatic comparison process.

According to the embodiment, the output data is subjected to similarity analysis, and the script is adopted to automatically realize comparison of output results, so that the verification reliability of the rasterization module is improved.

In a specific embodiment, the reference model 12 and the preprocessing component 13 may be integrated into the same component. The preprocessing component 13 is the prototype interface function in the reference model 12 Cmodel. The functions that the reference model 12 (Cmodel) mainly implements are xst_ras_data_pretreament (), xst_binding (), xst_ras (), and so on. And a rasterization module verification platform based on the combination of the UVM and the Cmodel primitive interface functions is adopted, so that the hierarchical structure is more obvious, the portability and the reusability are strong, and the verification efficiency is higher.

According to the embodiment, data meeting the format requirement can be input to the to-be-detected rasterization module through preprocessing, so that the to-be-detected rasterization module can be normally driven, and rasterization operation is executed; the preprocessing is combined with the UVM platform, so that randomized configuration data can be realized, test vectors of different scenes are generated, the integrity of function verification of the rasterization module is ensured, and the verification efficiency of the rasterization module is greatly improved; the technical problem that the performance of the to-be-detected rasterization module cannot be judged through accurate comparison due to unordered output fragments in the traditional method can be solved through similarity comparison, and the reliability of the rasterization module verification is improved; the rasterization verification platform constructed based on the UVM verification methodology is clear in structure and high in portability and reusability, and the problems that the conventional Verilog is complicated in generating various test vectors and cannot be reused in writing testbenchmarks are solved; and UVM object-oriented programming, constraint random excitation, function coverage rate checking, assertion and other attributes are easy to locate problems of the to-be-detected rasterization module.

In one embodiment, UVM verification platform 10 further comprises a sequence class, and agent component 11 comprises an input agent component;

the input agent component includes: an input driver, an input monitor, an input sequencer;

an input driver for sending a first sequence request to an input sequencer;

an input sequencer for acquiring a first sequence of transactions requested by an input driver from a sequence class and transmitting the acquired first sequence of transactions to the input driver;

the input driver is further configured to parse the obtained first sequence, obtain primitive data before processing, and transmit the primitive data before processing to the preprocessing component 13;

a sequence class for encapsulating the preprocessed primitive data obtained from the preprocessing component 13, generating a second sequence of transactions;

an input driver for sending a third sequence request to the input sequencer;

the input sequence generator is further used for acquiring a third sequence transaction requested by the input driver from the sequence class and transmitting the acquired third sequence transaction to the input driver;

the input driver is further used for analyzing the acquired third sequence and acquiring register configuration data;

An input driver for transmitting register file configuration data to the hardware registers via the bus interface 15 to configure the hardware registers;

the input driver is further used for sending a second sequence request to the input sequence generator after the hardware register configuration is determined to be completed or the hardware rasterization module is determined to be started;

the input sequence generator is further used for acquiring a second sequence transaction requested by the input driver from the sequence class and transmitting the acquired second sequence transaction to the input driver;

the input driver is also used for analyzing the acquired second sequence and acquiring preprocessed primitive data;

the input driver is further configured to sequentially transmit different preprocessed primitive data to the hardware to be tested rasterizer 20 through the bus interface 15 according to a time sequence, so as to drive the hardware to be tested rasterizer 20 to execute a rasterization operation.

Specifically, the sequences involved are the source of stimulus generation, and different stimuli can be generated by setting different sequences in different test cases.

The proxy component 11 includes an input proxy component and an output proxy component.

The input agent component mainly encapsulates input drivers of input ports, input monitors, input Sequencers (SQR).

The driver in the verification platform is derived from uvm _driver, obtains sequence transactions or transaction classes through a sequence generator (sqr), and then transmits the sequence transactions or transaction classes to the hardware to be tested rasterization module 20 through a system interface, and finally drives the hardware to be tested rasterization module 20.

The monitor (monitor) in the present verification platform is derived from the UVM _monitor class, and the function of the input monitor is to obtain the sequential transaction or transaction class through the bus interface 15, and then pass the sequential transaction or transaction class to the reference model 12 (Cmodel) through fifo or port of UVM.

The Sequencer (SQR) in the present verification platform derives from the uvm _sequencer class, and is the medium for communication between the sequence and the driver (driver) which drives the sequence to obtain the sequence transaction or class of transactions by sending requests to the Sequencer (SQR) and sends the sequence transaction or class of transactions to the driver (driver).

The sequences or sequence classes in the verification platform are derived from uvm _sequence classes, the sequences are sources of stimulus generation, and different stimuli can be generated by setting different sequences as default sequences (default sequences) of a sequence generator (sqr) in a test case (testcase).

The Sequencer (SQR) is a communication medium between the sequence and the drive, and by sending a request to the sequencer SQR, the sequencer SQR obtains a transaction class or sequence transaction from the sequence and then sends it to the drive; the driver involved transfers the transaction class or sequence transaction obtained from the sequencer SQR to the hardware under test rasterizer 20 via the bus interface 15, and finally drives the hardware under test rasterizer 20.

In this embodiment, preprocessing is performed first, so that the driver is input to send the first sequence request to the input sequencer; an input sequencer for acquiring a first sequence of transactions requested by an input driver from a sequence class and transmitting the acquired first sequence of transactions to the input driver; the input driver is further configured to parse the obtained first sequence, obtain primitive data before processing, and transmit the primitive data before processing to the preprocessing component 13; a sequence class for encapsulating the preprocessed primitive data obtained from the preprocessing component 13, resulting in a second sequence of transactions.

An input driver for sending a third sequence request to the input sequencer; the input sequence generator is further used for acquiring a third sequence transaction requested by the input driver from the sequence class and transmitting the acquired third sequence transaction to the input driver; the input driver is further used for analyzing the acquired third sequence and acquiring register configuration data; the input driver is further configured to transmit register file configuration data to the hardware registers via the bus interface 15 to configure the hardware registers.

The input driver is further used for sending a second sequence request to the input sequence generator after the hardware register configuration is determined to be completed or the hardware rasterization module is determined to be started; the input sequence generator is further used for acquiring a second sequence transaction requested by the input driver from the sequence class and transmitting the acquired second sequence transaction to the input driver; the input driver is also used for analyzing the acquired second sequence and acquiring preprocessed primitive data; the input driver is further configured to sequentially transmit different preprocessed primitive data to the hardware to be tested rasterizer 20 through the bus interface 15 according to a time sequence, so as to drive the hardware to be tested rasterizer 20 to execute a rasterization operation.

The hardware to be tested rasterizer module 20 performs a rasterization operation based on the acquired preprocessed primitive data and the register configuration data read from the hardware registers.

In addition, the sequence class is also used for randomly generating different register configuration data according to the acquired register list and randomly generating different third sequence transactions according to the different register configuration data.

The input monitor is used for monitoring the input of the hardware rasterization module 20 to be tested, capturing the register file configuration data and the preprocessed primitive data through the bus interface 15, and transmitting the preprocessed primitive data and the register file list to the reference model 12 through the UVM communication port.

In another embodiment, the register configuration data and the preprocessed primitive data may be packaged and transmitted to the reference model 12, the input monitor monitors the input of the hardware under test rasterizing module 20, grabs the data transmitted to the hardware under test rasterizing module 20 each time through the bus interface 15, and notifies the reference model 12 after determining that the data is successfully transmitted to the hardware under test rasterizing module 20, so as to instruct the reference model 12 to continue to perform the rasterizing operation. If the data is not successfully transmitted to the hardware to be tested rasterizing module 20, the reference model 12 is informed to pause the execution of the rasterizing operation so as to realize the operation synchronization with the hardware to be tested rasterizing module 20, and the condition that the reference model 12 and the hardware to be tested rasterizing module 20 are not synchronous in operation when the data transmission is problematic is avoided, and useless operation is reduced.

The verification principle of the present embodiment is specifically described as follows:

the testbench top layer is located at the top layer of the whole verification platform, and through importing relevant codes of UVM components, all components of UVM and the hardware to be tested grating module 20 are instantiated, all bus interfaces 15 relevant to the hardware to be tested grating module 20 are declared and instantiated, the initial verification platform and the hardware to be tested grating module 20 comprise codes for generating clock and reset signals, connecting the verification platform and the hardware to be tested grating module 20, and importing the reference model 12, and the verification platform is started through running test cases.

The driver sends a request to the sequencer SQR to obtain a transaction class that refers to all relevant input variables of the hardware-under-test rasterizer 20 and that has randomized constraints, which are then transferred into the hardware-under-test rasterizer 20 by calling the bus interface 15, ultimately driving the hardware-under-test rasterizer 20.

After the calculation is completed by the rasterizing module, the obtained output result is transmitted back to the output monitor through the interface and converted into a transaction class to be stored, and then transmitted to the scoreboard 14 through the UVM port, before the calculation is completed by the rasterizing module, the verification platform reference model 12 and the driver need to wait, no operation is required in the waiting period, and when the value of the status register of the rasterizing module is read to be the value corresponding to the end mark, the calculation of the rasterizing module is ended.

The reference model 12Cmodel processes the transaction class acquired from the input monitor to obtain the expected output.

The scoreboard 14 component compares the output of the reference model 12 with the output of the hardware under test rasterizer module 20 to yield a validation result.

In one embodiment, the proxy component 11 further comprises an output proxy component;

the output agent component includes: an output monitor;

And the output monitor is used for monitoring the output of the hardware rasterization module 20 to be tested, and acquiring an actual processing result obtained after the hardware rasterization module 20 to be tested executes the rasterization logic operation according to the register configuration data and the preprocessed primitive data through the bus interface 15.

Specifically, the output monitor (monitor) is also derived from UVM _monitor class, and is used for detecting the output of the rasterization module, waiting until the calculation of the rasterization module is finished, putting the valid data at the output end into a transaction class or a sequence transaction through the bus interface 15, and then transmitting the transaction class or the sequence transaction to the scoreboard 14 (SCB) through fifo of UVM for comparison to verify whether the output of the rasterization module is correct.

The output agent component includes: an output monitor of the output port.

And an output monitor, configured to monitor an output of the hardware rasterization module 20 to be tested, and obtain an actual processing result obtained after the hardware rasterization module 20 to be tested performs a rasterization logic operation according to the register configuration data and the preprocessed primitive data through a bus interface 15 (for example, any one of the HCI bus interface 15 and the HWPE bus interface 15).

The output monitor places the actual processing results at the output into the transaction class and then passes the results to the scoreboard 14 for comparison via the UVM communications port.

In one embodiment, UVM verification platform 10 includes an AXI bus, a HWPE bus, and an HCI bus;

the UVM verification platform 10 performs communication transmission of different data with the hardware rasterization module 20 to be tested through an AXI bus, a HWPE bus and an HCI bus;

or alternatively;

UVM verification platform 10 includes an AXI bus and an HWPE bus;

the UVM verification platform 10 performs communication transmission of different data with the hardware rasterization module 20 to be tested through an AXI bus and an HWPE bus.

Specifically, if UVM verification platform 10 includes an AXI bus, an HWPE bus, and an HCI bus, corresponding bus interfaces 15 are AXI bus interface 15 (axi_if), HWPE bus interface 15 (hwpe_if), and HCI bus interface 15 (hci_if), respectively.

Wherein the AXI bus is used for configuring registers of the rasterizing module, i.e. transmitting register configuration data to the hardware registers. The HWPE bus is configured for configuring the processed primitive data required by the rasterizing module, where the processed primitive data includes one or more of vertex data, attributes, primitive context, and the like, and is used for fetching the primitive data from the binary register to the rasterizing module, and the HCI bus is used for collecting the actual processing result output by the hardware rasterizing module 20 to be tested.

The hardware to be tested rasterization module 20 (i.e. DUT module) and related interfaces are instantiated in the testbench top layer, and data interaction can be realized by means of parameter call.

Wherein, proxy component 11 comprises an AXI proxy component (axi_agent), an HCI proxy component (hci_agent), and a HWPE proxy component (hwpe_agent); sequence or sequence classes include AXI sequence (axi_seq), rasterizer sequence (ras_seq), register sequence (bin_seq), sequence transactions or transaction classes include AXI sequence transaction (axi_tr), HWPE sequence transaction (hwpe_tr), rasterizer sequence (ras_seq), register sequence (bin_seq) each provide HWPE sequence transaction, AXI sequence (axi_seq) provides AXI sequence transaction.

The HWPE bus may replace the HCI bus, in which case UVM verification platform 10 includes an AXI bus and a HWPE bus; respectively correspond to AXI bus interface 15 (axi_if) and HWPE bus interface 15 (hwpe_if).

The AXI protocol can save time, implement handshaking, and start the rasterizing module after determining that the register configuration is completed. The HCI bus may be replaced by a HWPE bus. Complexity: AXI bus > HWPE bus > HCI bus.

Different test cases can be configured through the three groups of bus interfaces 15 or the two groups of bus interfaces 15, the generation of the test cases can be provided by software, random configuration can be realized through the constraint of interface functions in the Cmodel of the verification platform, the verification scene of the rasterization module can be more comprehensively covered, and the functional correctness of the module is ensured.

In one embodiment, the input agent component includes: a first input agent component and a second input agent component;

the first input agent component comprises: a first input driver, a first input monitor, a first input sequencer;

the second input agent component includes: a second input driver, a second input monitor, a second input sequencer;

a first input driver for sending a sequence request to a first input sequencer;

a first input sequencer for retrieving a third sequence of transactions requested by the first input driver from the sequence class and transmitting the retrieved third sequence of transactions to the first input driver;

the first input driver is further configured to parse the acquired third sequence transaction, and transmit the obtained register configuration data to the hardware register through the AXI bus interface 15, so as to configure the hardware register;

the second input driver is used for sending a sequence request to the second input sequence generator after the hardware register configuration is determined to be completed or the hardware rasterization module is determined to be started;

a second input sequencer for retrieving a second sequence of transactions requested by a second input driver from the sequence class and transmitting the retrieved second sequence of transactions to the second input driver;

The second input driver is further configured to parse the acquired second sequence transaction, and transmit the obtained primitive data after different preprocessing to the hardware to be tested rasterization module 20 through the HWPE bus interface 15 according to the time sequence, so as to drive the hardware to be tested rasterization module 20 to execute rasterization operation.

Specifically, a first input proxy component is an AXI proxy component and a second input proxy component is a HWPE proxy component.

The first input sequencer sends a sequence request for requesting AXI sequence transactions. That is, the third sequence of transactions is an AXI sequence of transactions. The third sequence of transactions has stored therein register configuration data.

The second input sequencer sends a sequence request for requesting HWPE sequence transactions; the second sequential transaction is a HWPE sequential transaction. The second sequence of transactions has pre-processed primitive data stored therein.

More specifically, the output agent component, i.e. the HCI agent component, the output monitor obtains the actual processing result from the hardware rasterization module 20 to be tested through the HCI interface (hci_if), places the actual processing result of the output end or the valid data in the actual processing result into a transaction class, for example, into any one of the transaction classes axi_tr and hwpe_tr, and then transmits the transaction class (axi_tr or hwpe_tr) to the scoreboard 14 (SCB) through fifo of UVM for comparison, and verifies whether the rasterization module outputs correctly.

In one embodiment, reference model 12 includes a software rasterization module and software registers;

the software register is used for carrying out software register configuration according to the input register configuration data;

and the software rasterizing module is used for executing rasterizing logic operation according to the input preprocessed primitive data and the register configuration data read from the software register and outputting a reference processing result.

Specifically, the software rasterization module is a software rasterization function, and the software register is a software bintable function.

In one embodiment, the actual processing results include: the actual fragment data, the reference processing result includes: referencing fragment data;

the scoreboard 14 is specifically configured to perform data similarity analysis by calculating variances and/or standard deviations of all actual fragment data and reference fragment data, so as to obtain a similarity ratio or similarity for indicating the similarity of the fragment data, where the similarity ratio or similarity is used as a comparison result.

Specifically, the actual fragment data is actual fragment information data, the reference fragment data is reference fragment information data, and the actual fragment data and the reference fragment data are both rasterized data. The actual fragment data and the reference fragment data each contain one or more of information of coordinates, color attributes, and the like. fragmenting: and (3) the information of each grid formed after the primitive is processed by the rasterization module.

Specifically, the similarity of the fragment data output by the reference model 12 and the fragment data output by the hardware module can be compared through the function corrrow (), and finally, the similarity proportion or the similarity of the two fragment data can be obtained. The larger the similarity ratio or the higher the similarity, the closer the two outputs are represented. If the similarity ratio is lower than the ratio threshold or the similarity is lower than the similarity threshold, error reporting information can be output or prompted.

Because the fragments output by the rasterization module are unordered and the data size is huge, the sequential comparison cannot be directly performed. Therefore, in this embodiment, through the automation script, the output of the reference model 12 and the output of the hardware module are used as the data of the input end, the variance, standard deviation, and the like of all the data are calculated in the comparison script, and the data similarity analysis is performed, so as to finally obtain the similarity ratio of the data.

If the similarity ratio exceeds the ratio threshold or the similarity is higher than the similarity threshold, the verification is passed. If the similarity ratio is too low, errors will be reported and error types such as coordinates x, y, z and attributes will be displayed.

The traditional test standard is written based on Verilog, the output of the rasterization module cannot be directly compared, the verification platform comprises a script for processing the output result, the similarity analysis can be carried out on the output data, and the problem that the output data cannot be automatically compared by the rasterization module is solved.

Referring to fig. 2, the present application further provides a UVM-based rasterized module authentication method, which includes:

s100: acquiring and analyzing sequence transactions, and acquiring register configuration data and primitive data before processing;

s200: converting each pre-processed primitive data into pre-processed primitive data usable by the hardware rasterization module 20 to be tested by a pre-processing function;

s300: the register configuration data and the preprocessed primitive data are simultaneously used as the input of the hardware rasterization module to be tested and the reference model, and are respectively transmitted and provided for the hardware rasterization module to be tested and the reference model;

s400: acquiring an actual processing result of executing the rasterization logic operation by the hardware rasterization module to be tested according to the register configuration data and the preprocessed primitive data;

s500: acquiring a reference processing result of the reference model for executing the rasterization logic operation according to the register configuration data and the preprocessed primitive data;

s600: and carrying out similarity analysis on the obtained actual processing result and the reference processing result to obtain a comparison result.

Specifically, the UVM-based rasterization module validation method is applied to the UVM validation platform 10. Specific analysis is described above and will not be repeated here.

In step S600, similarity analysis is performed on the obtained actual processing result and the reference processing result to obtain a comparison result, which includes:

and carrying out data similarity analysis by calculating variances and/or standard deviations of all actual fragment data and reference fragment data to obtain a similarity proportion or similarity for indicating the similarity of the fragment data, wherein the similarity proportion or similarity is used as a comparison result.

Specifically, the actual fragment data is actual fragment information data, the reference fragment data is reference fragment information data, and the actual fragment data and the reference fragment data are both rasterized data. The actual fragment data and the reference fragment data each contain one or more of information of coordinates, color attributes, and the like.

Specifically, the similarity of the fragment data output by the reference model and the fragment data output by the hardware module can be compared through a function corrwith (), and finally, the similarity proportion or the similarity of the two fragment data can be obtained. The larger the similarity ratio or the higher the similarity, the closer the two outputs are represented. If the similarity ratio is lower than the ratio threshold or the similarity is lower than the similarity threshold, error reporting information can be output or prompted.

If the similarity ratio exceeds the ratio threshold or the similarity is higher than the similarity threshold, the verification is passed.

Wherein the similar proportion is the proportion of the same data in the total data amount.

The application combines primitive interface functions of UVM and Cmodel, and relates to three groups of bus interfaces, transaction classes, sequences, sequence generators (SQRs), drivers, monitors, agents, scoreboards, test cases, reference models, DUT rasterization modules to be tested, and the like. According to the method, different test cases are configured through three groups of bus interfaces, the test cases can be generated by software, a register configuration list can be generated by using a Cmodel interface function in the verification platform, position data, attribute data and graphic element context information, and input randomized parameter configuration can be realized through the interface function in the verification method.

According to the automatic data analysis comparison script of the verification platform, the output of the reference model and the output of the hardware module are used as data of the input end, all the data are calculated in the comparison script, the data similarity of the reference model and the hardware module is analyzed, the proportion of the data similarity is finally obtained, the similarity proportion does not meet the requirement, error reporting information is prompted, and the automatic comparison process is realized.

FIG. 3 illustrates an internal block diagram of a computer device in one embodiment. The computer device may specifically be a terminal or a server. In which a UVM verification platform is installed, as shown in fig. 3, the computer device comprises a processor, a memory and a network interface connected by a system bus. The memory includes a nonvolatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system, and may also store a computer program which, when executed by a processor, causes the processor to implement the steps of the method embodiments described above. The internal memory may also have stored therein a computer program which, when executed by a processor, causes the processor to perform the steps of the method embodiments described above. It will be appreciated by those skilled in the art that the structure shown in fig. 3 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is provided comprising a memory and a processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the steps of:

In one embodiment, a computer readable storage medium is provided, storing a computer program which, when executed by a processor, causes the processor to perform the steps of:

Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored in a non-transitory computer-readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. A UVM-based rasterized module validation system, the validation system comprising: the UVM verification platform is connected with the hardware rasterization module to be tested;

The preprocessing component is used for converting each piece of primitive data before processing into preprocessed primitive data which can be used by the hardware rasterization module to be detected through a preprocessing function;

the proxy component is further configured to simultaneously use the register configuration data and the preprocessed primitive data as inputs of a hardware to be tested rasterizing module and a reference model, respectively transmit the inputs to the hardware to be tested rasterizing module and the reference model, acquire an actual processing result of executing a rasterizing logic operation by the hardware to be tested rasterizing module according to the register configuration data and the preprocessed primitive data through a bus interface, and acquire a reference processing result of executing the rasterizing logic operation by the reference model according to the register configuration data and the preprocessed primitive data;

the scoreboard is used for carrying out similarity analysis on the obtained actual processing result and the obtained reference processing result to obtain a comparison result;

wherein the UVM verification platform further comprises a sequence class, the proxy component comprising an input proxy component;

The input driver is used for sending a first sequence request to the input sequence generator;

the input sequence generator is used for acquiring a first sequence transaction requested by the input driver from the sequence class and transmitting the acquired first sequence transaction to the input driver;

the input driver is further used for analyzing the acquired first sequence, acquiring the primitive data before processing, and transmitting the primitive data before processing to the preprocessing component;

the sequence class is used for packaging the preprocessed primitive data obtained from the preprocessing component to generate a second sequence transaction;

the input driver is used for sending a third sequence request to the input sequence generator;

the input driver is further configured to parse the obtained third sequence to obtain register configuration data;

the input driver is further used for transmitting the register column configuration data to the hardware register through the bus interface to configure the hardware register;

The input driver is further configured to send a second sequence request to the input sequencer after determining that the hardware register configuration is completed or determining that the hardware rasterization module is started;

the input driver is further used for analyzing the acquired second sequence and acquiring preprocessed primitive data;

the input driver is further used for sequentially transmitting different preprocessed primitive data to the hardware to be tested rasterization module through the bus interface according to the time sequence so as to drive the hardware to be tested rasterization module to execute rasterization operation.

2. The authentication system of claim 1, wherein the reference model and preprocessing component are integrated into the same component.

3. The authentication system of claim 1, wherein the proxy component further comprises an output proxy component;

the output agent component includes: an output monitor;

and the output monitor is used for monitoring the output of the hardware rasterization module to be tested, and acquiring an actual processing result obtained after the hardware rasterization module to be tested executes the rasterization logic operation according to the register configuration data and the preprocessed primitive data through a bus interface.

4. The authentication system of claim 1, wherein the UVM authentication platform comprises an AXI bus, a HWPE bus, and an HCI bus;

the UVM verification platform performs communication transmission of different data with the hardware rasterization module to be tested through an AXI bus, a HWPE bus and an HCI bus;

or alternatively;

the UVM verification platform comprises an AXI bus and a HWPE bus;

and the UVM verification platform performs communication transmission of different data with the hardware rasterization module to be tested through an AXI bus and an HWPE bus.

5. The authentication system of claim 1, wherein the input agent component comprises: a first input agent component and a second input agent component;

the second input agent component comprises: a second input driver, a second input monitor, a second input sequencer;

the first input driver is used for sending a sequence request to the first input sequence generator;

the first input sequence generator is used for acquiring a third sequence transaction requested by the first input driver from the sequence class and transmitting the acquired third sequence transaction to the first input driver;

The first input driver is further configured to parse the acquired third sequence transaction, and transmit the obtained register configuration data to the hardware register through the AXI bus interface, so as to configure the hardware register;

the second input driver is used for sending a sequence request to the second input sequence generator after determining that the configuration of the hardware register is completed or determining that the hardware rasterization module is started;

the second input sequence generator is used for acquiring a second sequence transaction requested by the second input driver from the sequence class and transmitting the acquired second sequence transaction to the second input driver;

the second input driver is further configured to parse the acquired second sequence transaction, and sequentially transmit the obtained primitive data after different preprocessing to the hardware to be tested rasterization module through the HWPE bus interface according to the time sequence, so as to drive the hardware to be tested rasterization module to execute rasterization operation.

6. The verification system of claim 1, wherein the reference model comprises a software rasterization module and a software register;

7. The authentication system of claim 1, wherein the authentication system comprises,

the actual processing result comprises: actual fragment data, the reference processing results include: referencing fragment data;

the scoreboard is specifically configured to perform data similarity analysis by calculating variances and/or standard deviations of all actual fragment data and reference fragment data, so as to obtain a similarity ratio or similarity for indicating the similarity of the fragment data, and take the similarity ratio or similarity as a comparison result.

8. A method for verifying a UVM-based rasterization module, applied to the UVM-based rasterization module verification system of any one of claims 1 to 7, comprising:

The register configuration data and the preprocessed primitive data are simultaneously used as the input of a hardware rasterization module to be tested and a reference model, and are respectively transmitted and provided for the hardware rasterization module to be tested and the reference model;

9. The method of claim 8, wherein the actual processing results comprise: actual fragment data, the reference processing results include: referencing fragment data;

and performing similarity analysis on the obtained actual processing result and the reference processing result to obtain a comparison result, wherein the similarity analysis comprises the following steps:

and carrying out data similarity analysis by calculating variances and/or standard deviations of all actual fragment data and reference fragment data to obtain a similarity proportion or similarity for indicating the similarity of the fragment data, and taking the similarity proportion or similarity as a comparison result.

10. A computer readable storage medium storing a computer program, which when executed by a processor causes the processor to perform the steps of the method according to any one of claims 8 to 9.