CN111950212B - Efficient multi-mode verification platform and method - Google Patents
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Abstract
The invention provides a high-efficiency multi-mode verification platform and a method, comprising the following steps: step 1, inputting test excitation into a multi-mode verification platform, and respectively calling library and IP by the multi-mode verification platform to perform software simulation verification; step 2, finding errors in the software simulation verification process, returning to the DUT catalog, and modifying the chip design file; and step 3, performing prototype verification of the FPGA hardware system without errors in the software simulation verification process. The method is compatible with software simulation verification under the FPGA development condition and prototype verification of an FPGA hardware system, the software simulation verification supports single testcase or multiple testcase parallel simulations, each testcase simulation result is stored in a space and cannot be covered, the multi-mode verification platform supports automatic reading of design files and real-time refreshing, automatic full compiling and manual step compiling can be supported, engineering file management difficulty is effectively avoided, and complex operations of engineering compiling and online debugging are reduced.
Description
Technical Field
The invention relates to the technical field of digital integrated circuit design and verification, in particular to a high-efficiency multi-mode verification platform and method.
Background
The well-known moore law states that the number of transistors that can be accommodated by the chip of an integrated circuit is doubled every 18 months, and the performance is doubled, so that the complexity of the chip is increased, and the chip brings a serious challenge to the verification work of a digital integrated circuit, and the current verification can be divided into two modes, namely software simulation verification and hardware system prototype verification.
The software simulation verification is performed by establishing test excitation through a language programming mode based on a verification methodology (UVM, VMM and the like), the verification mode has complex environment, and the programming, simulation and debugging work is heavy, and the actual application scene of the chip is difficult to consider.
The hardware system prototype verification is characterized in that the FPGA chip is utilized to realize the function of a designed digital integrated circuit, the correctness of the chip is directly verified on board-level hardware, the FPGA (Field Programmable GATE ARRAY) is a field programmable device, the actual chip production of the integrated circuit is not required, and the application of simulating various integrated circuits can be rapidly realized in a programming mode. Most of the current FPGA chips have huge logic, storage and IP resources, so that in the front-end verification of chip design, a system-level hardware verification platform can be built by utilizing the FPGA, and all or part of functions of the whole chip can be completed on the FPGA. Through FPGA board level debugging, hidden bugs in the chip design can be verified quickly, the effect of the chip design can be perceived intuitively, and defects of the system design or application limitations are found. Thereby reducing the verification period of the chip design.
Disclosure of Invention
The invention provides a high-efficiency multi-mode verification platform and a method, and aims to solve the problems of low verification efficiency, poor quality and difficult maintenance of a traditional verification platform.
To achieve the above object, an embodiment of the present invention provides an efficient multi-mode authentication platform, including:
the automatic module comprises a software simulation platform and a configuration file of chip design;
a config module comprising a global profile of a multi-mode verification platform;
And FPGA the FPGA module comprises an FPGA system prototype verification platform and a configuration file.
Wherein, the asic module includes:
an analog unit comprising an analog integrated circuit IP model;
The system comprises a bin unit, a storage unit and a control unit, wherein the bin unit comprises a common file processing script;
A config unit comprising dut.f, dut_fpga.f, modem.f, tb.f, TESTLIST, and software emulation required configuration files for chip design;
the doc unit is used for storing record files in the research and development process of the chip;
the lib unit is used for storing a chip design process library and a soft core IP;
models unit, wherein the models unit comprises a peripheral equipment model and a software simulation monitor for chip practical application;
The system comprises a sim unit, wherein the sim unit is provided with two subdirectory spaces task and run, the task comprises testcase libraries, and the run is a simulation result storage space;
a tb unit, which is a test stimulus for chip verification;
the verilog directory comprises a whole chip design file.
Wherein, fpga module includes:
a design input file comprising fpga _ edif units, fpga _ edif units, and fpga _hdl units;
A mem_init unit including initialization data of a memory;
The reports unit comprises an FPGA compiling report output storage space;
The result unit comprises an FPGA compiling result output storage space;
A run unit, which is a space for the FPGA to execute compiling;
and the tcl unit comprises configuration and script files for performing compiling and system prototype verification by the FPGA.
The embodiment of the invention also provides a high-efficiency multi-mode verification method, which comprises the following steps:
Step 1, inputting test excitation into a multi-mode verification platform, and respectively calling library and IP by the multi-mode verification platform to perform software simulation verification;
step 2, finding errors in the software simulation verification process, returning to the DUT catalog, and modifying the chip design file;
Step 3, executing prototype verification of the FPGA hardware system without errors in the software simulation verification process;
And step 4, finding errors in the process of executing the prototype verification of the FPGA hardware system, returning to the DUT catalog, modifying the chip design file, and carrying out software simulation verification and the prototype verification of the FPGA hardware system again.
Wherein, the step1 specifically includes:
simulation verification of a single testcase was performed:
step 1.1.1, adding a new testcase in the multi-mode verification platform, and inputting a simulation instruction;
step 1.1.2, the multimode verification platform analyzes the simulation instruction, including searching testcase definition, searching testcase required file, summarizing compiled macro definition and compiling instruction of simulation, running setting script before simulation, buffering result detection script when simulation is finished and establishing a storage catalog of simulation result;
step 1.1.3, reading files of the DUT and related configuration files;
Step 1.1.4, starting software simulation verification, and automatically running a software simulation verification result detection script after the software simulation verification is finished;
Step 1.1.5, checking a software simulation verification result, wherein the software simulation verification result comprises a simulated information record file and a report file for carrying out result data detection by an operation script;
step 1.1.6, finding that an error exists in the software simulation verification process, returning to the DUT catalog, modifying the chip design file, re-executing the current testcase software simulation verification, adding a new testcase in the software simulation verification process, and circulating the above operations until all functions of the chip design are covered.
Wherein, the step 1 further comprises:
and carrying out parallel simulation verification on a plurality of testcase during regression simulation:
Step 1.2.1, setting testcase a list, and adding the setting testcase list to the multi-mode verification platform;
Step 1.2.2, the multimode verification platform analyzes the simulation instructions, including searching for the definition of each testcase, searching for the file required by each testcase, summarizing the compiled macro definition and the compiling quality of each testcase simulation, running the set script before each testcase simulation and caching the result detection script when each testcase simulation is finished;
step 1.2.3, reading files of the DUT and related configuration files;
Step 1.2.4, starting software simulation verification, and automatically running a software simulation verification result detection script after each testcase software simulation verification is finished;
step 1.2.5, summarizing the simulation verification result of the software;
And step 1.2.6, checking a regression simulation report, wherein the regression simulation report comprises whether each testcase software simulation verification is correctly finished or not and the code coverage rate of the simulation.
Wherein, the step 4 specifically includes:
Performing FPGA full compiling and system prototype verification:
Step 4.1.1, analyzing the input instruction by the multi-mode verification platform, wherein the analysis comprises the steps of setting relevant variable values in the full compiling process of the FPGA, judging an operation mode and executing a setting script before compiling the FPGA;
step 4.1.2, starting Vivado software, automatically establishing FPGA engineering if no FPGA engineering is currently established, otherwise, automatically loading the FPGA engineering;
step 4.13, executing the comprehensive and comprehensive time sequence analysis, outputting a comprehensive result and a time sequence analysis report, and storing the output comprehensive result and time sequence analysis report by taking the date of the day as a version number;
step 4.1.4, executing the back end PR, outputting the result and the report of the back end PR, and storing the output result and report of the back end PR by taking the date of the day as a version number;
step 4.1.5, downloading a burning file of the FPGA, and performing board level debugging and verification;
And 4.1.6, detecting the verification result of the FPGA, when the verification result of the FPGA has a problem, modifying the FPGA configuration file, compiling the FPGA again, if errors on the design are found, modifying the DUT design file, returning to the software simulation verification of the chip design again, and if the verification result of the FPGA passes, ending the verification.
Wherein, the step 4 further comprises:
performing manual sub-step compiling of the FPGA:
Step 4.2.1, analyzing the input instruction by the multi-mode verification platform, wherein the analysis comprises the steps of setting relevant variable values in the full compiling process of the FPGA, judging an operation mode and executing a setting script before compiling the FPGA;
Step 4.2.2, starting Vivado software, automatically establishing the FPGA project if no FPGA project is established currently, otherwise, automatically loading the FPGA project;
Step 4.2.3, executing an FPGA compiling step analyzed by the instruction;
Step 4.2.4, outputting a result and a report after the current compiling step of the FPGA is finished, and storing the output result and report by taking the date of the day as a version number;
step 4.2.5, the results and reports are analyzed.
The scheme of the invention has the following beneficial effects:
The efficient multi-mode verification platform and the method provided by the embodiment of the invention are compatible with software simulation verification and FPGA hardware system prototype verification under the FPGA development condition, the software simulation verification supports single testcase or multiple testcase parallel simulations, each testcase simulation result has respective space to be saved and cannot be covered, the multi-mode verification platform supports automatic reading of design files and real-time refreshing, automatic full compiling and manual step compiling can be supported, engineering file management difficulty is effectively avoided, and complex operations of engineering compiling and on-line debugging are reduced.
Drawings
FIG. 1 is a schematic view of the overall structure of the present invention;
FIG. 2 is a schematic diagram showing the structure of an asec module according to the present invention;
FIG. 3 is a schematic diagram showing a specific structure of a fpga module of the present invention;
FIG. 4 is a flow chart of the present invention;
FIG. 5 is a schematic diagram of the overall verification process of the present invention;
FIG. 6 is a flow chart of a simulation verification of a single testcase of the present invention;
FIG. 7 is a flow chart of a plurality testcase of parallel simulation verification of the present invention;
FIG. 8 is a flow chart of FPGA full compilation and system prototype verification of the present invention;
FIG. 9 is a flow chart of manual, step-by-step compilation of an FPGA of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved more apparent, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
Aiming at the problems of low verification efficiency, poor quality and difficult maintenance of the existing verification platform, the invention provides an efficient multi-mode verification platform and method.
As shown in fig. 1, an embodiment of the present invention provides an efficient multi-mode authentication platform, comprising: the automatic module comprises a software simulation platform and a configuration file of chip design; a config module comprising a global profile of a multi-mode verification platform; and FPGA the FPGA module comprises an FPGA system prototype verification platform and a configuration file.
As shown in fig. 2, the asic module includes: an analog unit comprising an analog integrated circuit IP model; the system comprises a bin unit, a storage unit and a control unit, wherein the bin unit comprises a common file processing script; a config unit comprising dut.f, dut_fpga.f, modem.f, tb.f, TESTLIST, and software emulation required configuration files for chip design; the doc unit is used for storing record files in the research and development process of the chip; the lib unit is used for storing a chip design process library and a soft core IP; models unit, wherein the models unit comprises a peripheral equipment model and a software simulation monitor for chip practical application; the system comprises a sim unit, wherein the sim unit is provided with two subdirectory spaces task and run, the task comprises testcase libraries, and the run is a simulation result storage space; a tb unit, which is a test stimulus for chip verification; the verilog directory comprises a whole chip design file.
As shown in fig. 3, the fpga module includes: a design input file comprising fpga _ edif units, fpga _ edif units, and fpga _hdl units; a mem_init unit including initialization data of a memory; the reports unit comprises an FPGA compiling report output storage space; the result unit comprises an FPGA compiling result output storage space; a run unit, which is a space for the FPGA to execute compiling; and the tcl unit comprises configuration and script files for performing compiling and system prototype verification by the FPGA.
As shown in fig. 4 to 5, the embodiment of the present invention further provides an efficient multi-mode verification method, including: step 1, inputting test excitation into a multi-mode verification platform, and respectively calling library and IP by the multi-mode verification platform to perform software simulation verification; step 2, finding errors in the software simulation verification process, returning to the DUT catalog, and modifying the chip design file; step 3, executing prototype verification of the FPGA hardware system without errors in the software simulation verification process; and step 4, finding errors in the process of executing the prototype verification of the FPGA hardware system, returning to the DUT catalog, modifying the chip design file, and carrying out software simulation verification and the prototype verification of the FPGA hardware system again.
The high-efficiency multi-mode verification platform and the high-efficiency multi-mode verification method comprise software simulation verification and FPGA hardware system prototype verification, wherein the software simulation verification comprises simulation verification under the chip design condition and simulation verification under the FPGA development condition, the two verification methods are different in library and IP called in the simulation process, the DUT and the Testbench (test excitation) are identical, and the simulation is testcase identical. Returning to the DUT and modifying the design file when the bug is found in the software simulation flow, and executing the prototype verification flow of the FPGA hardware system until the bug is not found in the software simulation flow; and returning to the DUT, modifying the design file, and carrying out software simulation verification flow and FPGA hardware system prototype verification flow again when the bug is found by the FPGA hardware system prototype verification.
As shown in fig. 6, the step 1 specifically includes: simulation verification of a single testcase was performed: step 1.1.1, adding a new testcase in the multi-mode verification platform, and inputting a simulation instruction; step 1.1.2, the multimode verification platform analyzes the simulation instruction, including searching testcase definition, searching testcase required file, summarizing compiled macro definition and compiling instruction of simulation, running setting script before simulation, buffering result detection script when simulation is finished and establishing a storage catalog of simulation result; step 1.1.3, reading files of the DUT and related configuration files; step 1.1.4, starting software simulation verification, and automatically running a software simulation verification result detection script after the software simulation verification is finished; step 1.1.5, checking a software simulation verification result, wherein the software simulation verification result comprises a simulated information record file and a report file for carrying out result data detection by an operation script; step 1.1.6, finding that an error exists in the software simulation verification process, returning to the DUT catalog, modifying the chip design file, re-executing the current testcase software simulation verification, adding a new testcase in the software simulation verification process, and circulating the above operations until all functions of the chip design are covered.
According to the efficient multi-mode verification platform and the method disclosed by the embodiment of the invention, a single testcase simulation verification flow of software simulation verification is as follows: adding a new testcase and inputting a simulation instruction; the second step, the high-efficiency multi-mode verification platform analyzes simulation instructions, including searching testcase definitions, searching testcase files, summarizing compiled macro definitions and compiled instructions of simulation, running a set script before simulation, caching a result detection script when the simulation is finished, and establishing a storage catalog of simulation results; thirdly, reading files of the DUT and related configuration files; fourthly, starting software simulation, and automatically running a simulation result detection script after the simulation is finished; fifthly, checking simulation results, wherein the simulation results comprise simulated information record files and report files for detecting result data by running scripts; and sixthly, if the bug is found to exist, the simulation returns to the DUT catalog, the chip design file is modified, the simulation verification of testcase is re-executed, if the bug is not found to exist, another testcase is added, and the process is circulated until all functions of the chip design are covered.
As shown in fig. 7, the step 1 further includes: and carrying out parallel simulation verification on a plurality of testcase during regression simulation: step 1.2.1, setting testcase a list, and adding the setting testcase list to the multi-mode verification platform; step 1.2.2, the multimode verification platform analyzes the simulation instructions, including searching for the definition of each testcase, searching for the file required by each testcase, summarizing the compiled macro definition and the compiling quality of each testcase simulation, running the set script before each testcase simulation and caching the result detection script when each testcase simulation is finished; step 1.2.3, reading files of the DUT and related configuration files; step 1.2.4, starting software simulation verification, and automatically running a software simulation verification result detection script after each testcase software simulation verification is finished; step 1.2.5, summarizing the simulation verification result of the software; and step 1.2.6, checking a regression simulation report, wherein the regression simulation report comprises whether each testcase software simulation verification is correctly finished or not and the code coverage rate of the simulation.
According to the efficient multi-mode verification platform and the efficient multi-mode verification method disclosed by the embodiment of the invention, a plurality of testcase parallel simulation verification flows in the regression simulation of software simulation verification are as follows: firstly, setting testcase a list; step two, the efficient multi-mode verification platform analyzes simulation instructions, which comprises searching definitions of each testcase, searching files needed by each testcase, summarizing compiled macro definitions and compiling quality of each testcase simulation, running a set script before each testcase simulation, and caching a result detection script when each testcase simulation is finished; thirdly, reading files of the DUT and related configuration files; fourthly, starting software simulation, and automatically running a simulation result detection script after each testcase simulation is finished; fifthly, summarizing simulation results; and sixthly, checking a regression simulation report, wherein the regression simulation report comprises whether each testcase simulation is correctly finished or not, and the code coverage rate of the simulation.
As shown in fig. 8, the step 4 specifically includes: performing FPGA full compiling and system prototype verification: step 4.1.1, analyzing the input instruction by the multi-mode verification platform, wherein the analysis comprises the steps of setting relevant variable values in the full compiling process of the FPGA, judging an operation mode and executing a setting script before compiling the FPGA; step 4.1.2, starting Vivado software, automatically establishing FPGA engineering if no FPGA engineering is currently established, otherwise, automatically loading the FPGA engineering; step 4.13, executing the comprehensive and comprehensive time sequence analysis, outputting a comprehensive result and a time sequence analysis report, and storing the output comprehensive result and time sequence analysis report by taking the date of the day as a version number; step 4.1.4, executing the back end PR, outputting the result and the report of the back end PR, and storing the output result and report of the back end PR by taking the date of the day as a version number; step 4.1.5, downloading a burning file of the FPGA, and performing board level debugging and verification; and 4.1.6, detecting the verification result of the FPGA, when the verification result of the FPGA has a problem, modifying the FPGA configuration file, compiling the FPGA again, if errors on the design are found, modifying the DUT design file, returning to the software simulation verification of the chip design again, and if the verification result of the FPGA passes, ending the verification.
According to the efficient multi-mode verification platform and method disclosed by the embodiment of the invention, the FPGA full compiling and system prototype verification flow of the FPGA hardware system prototype verification is as follows: analyzing an input instruction, including setting related variable values in the full compiling process of the FPGA, judging an operation mode, and executing a setting script before compiling the FPGA; secondly, starting Vivado software, automatically building the FPGA project if the FPGA project is not built currently, otherwise, automatically loading the FPGA project; thirdly, performing comprehensive and comprehensive time sequence analysis, outputting a comprehensive result and a time sequence analysis report, and storing the comprehensive result and the time sequence analysis report by taking the date of the day as a version number; fourthly, executing the back end PR, outputting the result and the report of the back end PR, and storing the result and the report of the back end PR by taking the date of the day as a version number; fifthly, downloading a burning file of the FPGA, and performing board level debugging and verification; and sixthly, detecting an FPGA verification result, if a problem exists, modifying an FPGA configuration file, then compiling the FPGA again, if a bug on the design is found, modifying a DUT design file, then returning to a software simulation verification flow of the chip design again, and if verification is passed, ending verification.
As shown in fig. 9, the step 4 further includes: performing manual sub-step compiling of the FPGA: step 4.2.1, analyzing the input instruction by the multi-mode verification platform, wherein the analysis comprises the steps of setting relevant variable values in the full compiling process of the FPGA, judging an operation mode and executing a setting script before compiling the FPGA; step 4.2.2, starting Vivado software, automatically establishing the FPGA project if no FPGA project is established currently, otherwise, automatically loading the FPGA project; step 4.2.3, executing an FPGA compiling step analyzed by the instruction; step 4.2.4, outputting a result and a report after the current compiling step of the FPGA is finished, and storing the output result and report by taking the date of the day as a version number; step 4.2.5, the results and reports are analyzed.
According to the efficient multi-mode verification platform and the method disclosed by the embodiment of the invention, the FPGA manual sub-step compiling flow for prototype verification of the FPGA hardware system is as follows: analyzing an input instruction, including setting related variable values in the full compiling process of the FPGA, judging an operation mode, and executing a setting script before compiling the FPGA; secondly, starting Vivado software, automatically building the FPGA project if the FPGA project is not built currently, otherwise, automatically loading the FPGA project; thirdly, executing an FPGA compiling step of analyzing the instruction; fourthly, the FPGA finishes the current compiling step to output a result and a report, and the result and the report are saved by taking the date of the day as a version number; and fifthly, analyzing the result and reporting.
After the development project is established, the verification environment architecture of the development project is created by using the instructions, as shown in fig. 1,2 and 3, the programming design of the DUT is performed in the Verilog catalog in fig. 2, and after the DUT is programmed, the verification of the DUT is started, and the overall verification flow of the efficient multi-mode verification platform and method is shown in fig. 5, firstly, the verification of software simulation is performed, and secondly, the prototype verification of the FPGA hardware system is performed. The software simulation verification firstly executes a single testcase simulation verification, a new testcase is added, simulation instructions are input, the efficient multi-mode verification platform analyzes the simulation instructions, the efficient multi-mode verification platform searches for testcase definitions, searches for testcase required files, gathers compiled macro definitions and compiled instructions of simulation, runs a set script before simulation, caches a result detection script at the end of the simulation, establishes a save directory of simulation results, the efficient multi-mode verification platform automatically reads DUT files and related configuration files, starts software simulation, automatically runs the simulation result detection script after the simulation is ended, checks simulation results, comprises log files of the simulation and report files for result data detection by the running script, returns the DUT directory if the simulation finds that bug exists, modifies chip design files, re-executes the simulation verification of testcase, and if no bug exists, adds another testcase, and circulates in such a way until all functions of chip design are covered. After the software simulation verification is executed for a certain period, the prototype verification of the FPGA hardware system can be started to be executed, and the steps are as shown in fig. 8 and 9, and fig. 9 is a manual step compiling flow for performing FPGA engineering compiling and debugging, time sequence repairing and the like during early FPGA compiling. Fig. 8 is a flow chart of performing prototype verification of the FPGA hardware system by adopting automatic full compilation, analyzing an input instruction, including setting related variable values in the full compilation process of the FPGA, judging an operation mode, executing a setting script before the compilation of the FPGA, starting Vivado software, automatically building the FPGA project if no FPGA project is currently built, otherwise, automatically loading the FPGA project, performing comprehensive and comprehensive time sequence analysis, outputting a comprehensive result and a time sequence analysis report, storing with the date of the day as a version number, executing a back end PR, outputting a result and a report of the back end PR, storing with the date of the day as a version number, downloading a burn file of the FPGA, performing board level debugging and verification, detecting the verification result of the FPGA, modifying the FPGA configuration file if a problem exists, then re-compiling the FPGA, and ending the verification if the verification passes. If errors are found in the DUT in the prototype verification process of the FPGA hardware system or the later flow of the chip design, the DUT catalog is required to be returned, design files are modified, regression simulation and multiple testcase parallel software simulation verification shown in FIG. 7 are executed, testcase lists are set, the efficient multi-mode verification platform analyzes simulation instructions, the efficient multi-mode verification platform comprises searching for the definition of each testcase, searching for files required by each testcase, summarizing the definition and the compiling quality of the compiling macro of each testcase simulation, running the set scripts before each testcase simulation, caching the result detection scripts when each testcase simulation is finished, reading the files and the related configuration files, starting the software simulation verification, automatically running the simulation result detection scripts after each testcase simulation is finished, checking the simulation results of the regression simulation report, and checking whether each testcase simulation is correctly finished or not. And if necessary, the process of prototype verification of the FPGA hardware system is required to be carried out again after the software simulation is finished.
According to the efficient multi-mode verification platform and the efficient multi-mode verification method, a verification environment framework of a research and development project can be automatically created through input instructions, the efficient multi-mode verification platform and the efficient multi-mode verification method are compatible with software simulation verification and FPGA hardware system prototype verification, the software simulation verification supports two types of software simulation under chip design conditions and software simulation under FPGA development conditions, independent verification of one testcase and parallel verification of a plurality of testcase is supported, verification results are mutually independent and stored in respective spaces, the FPGA hardware system prototype verification adopts an FPGA chip of Xilinx and a Vivado design platform, design files are supported to be automatically read in and refreshed in real time, automatic full compiling and manual step compiling can be achieved, operation commands are simple and fast, the FPGA compiling results and reports are automatically stored, daily work is stored in different versions by taking the date of the day as a version number, verification efficiency and quality are improved, and the verification platform is simple to maintain and can be quickly transplanted into different research and development projects.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (6)
1. A multi-mode authentication platform, comprising:
the automatic module comprises a software simulation platform and a configuration file of chip design;
the asic module includes:
an analog unit comprising an analog integrated circuit IP model;
The system comprises a bin unit, a storage unit and a control unit, wherein the bin unit comprises a common file processing script;
A config unit comprising dut.f, dut_fpga.f, modem.f, tb.f, TESTLIST, and software emulation required configuration files for chip design;
the doc unit is used for storing record files in the research and development process of the chip;
the lib unit is used for storing a chip design process library and a soft core IP;
models unit, wherein the models unit comprises a peripheral equipment model and a software simulation monitor for chip practical application;
The system comprises a sim unit, wherein the sim unit is provided with two subdirectory spaces task and run, the task comprises testcase libraries, and the run is a simulation result storage space;
a tb unit, which is a test stimulus for chip verification;
a verilog directory, the verilog directory including a whole chip design file;
a config module comprising a global profile of a multi-mode verification platform;
FPGA module, wherein the FPGA module comprises an FPGA system prototype verification platform and a configuration file;
the fpga module includes:
a design input file comprising fpga _ edif units and fpga _hdl units;
A mem_init unit including initialization data of a memory;
The reports unit comprises an FPGA compiling report output storage space;
The result unit comprises an FPGA compiling result output storage space;
A run unit, which is a space for the FPGA to execute compiling;
and the tcl unit comprises configuration and script files for performing compiling and system prototype verification by the FPGA.
2. A multi-mode authentication method applied to the multi-mode authentication platform as claimed in claim 1, comprising:
Step 1, inputting test excitation into a multi-mode verification platform, and respectively calling library and IP by the multi-mode verification platform to perform software simulation verification;
step 2, finding errors in the software simulation verification process, returning to the DUT catalog, and modifying the chip design file;
Step 3, executing prototype verification of the FPGA hardware system without errors in the software simulation verification process;
And step 4, finding errors in the process of executing the prototype verification of the FPGA hardware system, returning to the DUT catalog, modifying the chip design file, and carrying out software simulation verification and the prototype verification of the FPGA hardware system again.
3. The multi-mode authentication method according to claim 2, wherein the step 1 specifically comprises:
simulation verification of a single testcase was performed:
step 1.1.1, adding a new testcase in the multi-mode verification platform, and inputting a simulation instruction;
step 1.1.2, the multimode verification platform analyzes the simulation instruction, including searching testcase definition, searching testcase required file, summarizing compiled macro definition and compiling instruction of simulation, running setting script before simulation, buffering result detection script when simulation is finished and establishing a storage catalog of simulation result;
step 1.1.3, reading files of the DUT and related configuration files;
Step 1.1.4, starting software simulation verification, and automatically running a software simulation verification result detection script after the software simulation verification is finished;
Step 1.1.5, checking a software simulation verification result, wherein the software simulation verification result comprises a simulated information record file and a report file for carrying out result data detection by an operation script;
Step 1.1.6, finding that an error exists in the software simulation verification process, returning to the DUT catalog, modifying the chip design file, re-executing the current testcase software simulation verification, adding a new testcase in the software simulation verification process, and cycling the steps 1.1.1 to 1.1.6 until all functions of the chip design are covered.
4. The multi-mode authentication method according to claim 2, wherein the step 1 further comprises:
and carrying out parallel simulation verification on a plurality of testcase during regression simulation:
Step 1.2.1, setting testcase a list, and adding the setting testcase list to the multi-mode verification platform;
Step 1.2.2, the multimode verification platform analyzes the simulation instructions, including searching for the definition of each testcase, searching for the file required by each testcase, summarizing the compiled macro definition and the compiling quality of each testcase simulation, running the set script before each testcase simulation and caching the result detection script when each testcase simulation is finished;
step 1.2.3, reading files of the DUT and related configuration files;
Step 1.2.4, starting software simulation verification, and automatically running a software simulation verification result detection script after each testcase software simulation verification is finished;
step 1.2.5, summarizing the simulation verification result of the software;
And step 1.2.6, checking a regression simulation report, wherein the regression simulation report comprises whether each testcase software simulation verification is correctly finished or not and the code coverage rate of the simulation.
5. The multi-mode authentication method according to claim 2, wherein the step 4 specifically comprises:
Performing FPGA full compiling and system prototype verification:
Step 4.1.1, analyzing the input instruction by the multi-mode verification platform, wherein the analysis comprises the steps of setting relevant variable values in the full compiling process of the FPGA, judging an operation mode and executing a setting script before compiling the FPGA;
step 4.1.2, starting Vivado software, automatically establishing FPGA engineering if no FPGA engineering is currently established, otherwise, automatically loading the FPGA engineering;
step 4.13, executing the comprehensive and comprehensive time sequence analysis, outputting a comprehensive result and a time sequence analysis report, and storing the output comprehensive result and time sequence analysis report by taking the date of the day as a version number;
step 4.1.4, executing the back end PR, outputting the result and the report of the back end PR, and storing the output result and report of the back end PR by taking the date of the day as a version number;
step 4.1.5, downloading a burning file of the FPGA, and performing board level debugging and verification;
And 4.1.6, detecting the verification result of the FPGA, when the verification result of the FPGA has a problem, modifying the FPGA configuration file, compiling the FPGA again, if errors on the design are found, modifying the DUT design file, returning to the software simulation verification of the chip design again, and if the verification result of the FPGA passes, ending the verification.
6. The multi-mode authentication method according to claim 2, wherein the step 4 further comprises:
performing manual sub-step compiling of the FPGA:
Step 4.2.1, analyzing the input instruction by the multi-mode verification platform, wherein the analysis comprises the steps of setting relevant variable values in the full compiling process of the FPGA, judging an operation mode and executing a setting script before compiling the FPGA;
Step 4.2.2, starting Vivado software, automatically establishing the FPGA project if no FPGA project is established currently, otherwise, automatically loading the FPGA project;
Step 4.2.3, executing an FPGA compiling step analyzed by the instruction;
Step 4.2.4, outputting a result and a report after the current compiling step of the FPGA is finished, and storing the output result and report by taking the date of the day as a version number;
step 4.2.5, the results and reports are analyzed.
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