CN115145642B

CN115145642B - Software starting method and system

Info

Publication number: CN115145642B
Application number: CN202210669245.8A
Authority: CN
Inventors: 叶乐; 李辉; 程婷; 谢实海
Original assignee: Advanced Institute of Information Technology AIIT of Peking University; Hangzhou Weiming Information Technology Co Ltd
Current assignee: Advanced Institute of Information Technology AIIT of Peking University; Hangzhou Weiming Information Technology Co Ltd
Priority date: 2022-06-14
Filing date: 2022-06-14
Publication date: 2024-05-17
Anticipated expiration: 2042-06-14
Also published as: CN115145642A

Abstract

The embodiment of the application discloses a software starting method and a system, wherein the method comprises the following steps: cross compiling is carried out on the software started by the target to obtain an algorithm program running on the logic gate array FPGA; loading an algorithm program running on the FPGA into a memory with a fixed address through a CPU; configuring a wake-up register on the FPGA so that the FPGA enters an operating state after the algorithm program is loaded; a program entry register is configured on the FPGA so that the FPGA obtains an operation instruction according to the obtained fixed address in the memory; and configuring a calculation result register on the FPGA so that a result is sent to a CPU after the running of the FPGA is finished. The FPGA is more convenient to debug, and the system power consumption can be reduced by configuring the running state of the FPGA.

Description

Software starting method and system

Technical Field

The embodiment of the application relates to the technical field of computers, in particular to a software starting method and system.

Background

In recent years, the performance of general-purpose processors such as CPUs has been improved at a slow speed, and in order to continue to meet the increasing demands for energy-efficient computation in various industries, heterogeneous computing examples represented by FPGA, GPU, DSP, NPU and the like are increasingly used. Under the heterogeneous scene, the general CPU is often responsible for processing such as control and interaction of a user interface, and the deep learning on-line prediction is completed by hardware such as an FPGA, and the FPGA needs to load different algorithm programs on line for debugging. Currently, FGPA programs are loaded online, and the algorithm programs to be debugged are loaded onto the FPGA through hardware generally through connecting with a JTAG simulator.

In the heterogeneous scenario of a CPU and an FPGA, in the debugging stage of the system, an algorithm program to be run on the FPGA is generally loaded onto the FPGA through a JTAG emulator, which increases the cost for system debugging.

Disclosure of Invention

Therefore, the embodiment of the application provides a software starting method and a system, which enable the debugging of the FPGA to be more convenient, and can reduce the system power consumption by configuring the running state of the FPGA.

In order to achieve the above object, the embodiment of the present application provides the following technical solutions:

According to a first aspect of an embodiment of the present application, there is provided a software start-up method, the method including:

cross compiling is carried out on the software started by the target to obtain an algorithm program running on the logic gate array FPGA;

loading an algorithm program running on the FPGA into a memory with a fixed address through a CPU;

Configuring a wake-up register on the FPGA so that the FPGA enters an operating state after the algorithm program is loaded;

A program entry register is configured on the FPGA so that the FPGA obtains an operation instruction according to the obtained fixed address in the memory;

And configuring a calculation result register on the FPGA so that a result is sent to a CPU after the running of the FPGA is finished.

Optionally, the method further comprises:

and reconfiguring the wake-up register on the FPGA to enable the FPGA to enter a sleep state again.

Optionally, the method further comprises:

Cross compiling is carried out on the target upgraded software to obtain an upgrade algorithm program running on the FPGA;

loading an upgrade algorithm program running on the FPGA into a memory with a fixed address through a CPU;

a program entry register is configured on the FPGA so that the FPGA obtains an upgrading instruction according to the obtained fixed address in the memory;

and configuring a calculation result register on the FPGA so that the result is sent to the CPU after the FPGA is upgraded.

Optionally, the loading, by the CPU, the algorithm program running on the FPGA into the fixed address memory includes:

And loading a driving program on the CPU, checking a binary algorithm program running on the FPGA, and loading the binary algorithm program on a memory with a fixed address after error-free.

According to a second aspect of an embodiment of the present application, there is provided a software start-up system, the system comprising:

The cross compiling module is used for cross compiling the software started by the target to obtain an algorithm program running on the logic gate array FPGA;

The loading module is used for loading the algorithm program running on the FPGA to the memory with the fixed address through the CPU;

The first register configuration module is used for configuring a wake-up register on the FPGA so that the FPGA enters an operation state after the loading of the algorithm program is completed;

The second register configuration module is used for configuring a program entry register on the FPGA so that the FPGA obtains an operation instruction according to the obtained fixed address in the memory;

and the third register configuration module is used for configuring a calculation result register on the FPGA so that the result is sent to the CPU after the running of the FPGA is finished.

Optionally, the first register configuration module is further configured to:

Optionally, the system further comprises:

the cross compiling module is also used for cross compiling the target upgrading software to obtain an upgrading algorithm program running on the FPGA;

the loading module is also used for loading an upgrade algorithm program running on the FPGA to a memory with a fixed address through a CPU;

The second register configuration module is further configured to configure a program entry register on the FPGA, so that the FPGA obtains an upgrade instruction according to the obtained fixed address in the memory;

The third register configuration module is further configured to configure a calculation result register on the FPGA, so that after the FPGA is upgraded, a result is sent to the CPU.

Optionally, the loading module is specifically configured to:

According to a third aspect of an embodiment of the present application, there is provided an electronic apparatus including: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor executing the computer program to perform the method of the first aspect.

According to a fourth aspect of embodiments of the present application, there is provided a computer readable storage medium having stored thereon computer readable instructions executable by a processor to implement the method of the first aspect described above.

In summary, the embodiment of the application provides a software starting method and a system, which obtain an algorithm program running on a logic gate array FPGA by cross compiling target-started software; loading an algorithm program running on the FPGA into a memory with a fixed address through a CPU; configuring a wake-up register on the FPGA so that the FPGA enters an operating state after the algorithm program is loaded; a program entry register is configured on the FPGA so that the FPGA obtains an operation instruction according to the obtained fixed address in the memory; and configuring a calculation result register on the FPGA so that a result is sent to a CPU after the running of the FPGA is finished. The FPGA is more convenient to debug, and the system power consumption can be reduced by configuring the running state of the FPGA.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It will be apparent to those of ordinary skill in the art that the drawings in the following description are exemplary only and that other implementations can be obtained from the extensions of the drawings provided without inventive effort.

The structures, proportions, sizes, etc. shown in the present specification are shown only for the purposes of illustration and description, and are not intended to limit the scope of the invention, which is defined by the claims, so that any structural modifications, changes in proportions, or adjustments of sizes, which do not affect the efficacy or the achievement of the present invention, should fall within the scope of the invention.

FIG. 1 is a schematic flow chart of a software start method according to an embodiment of the present application;

FIG. 2 is a block diagram of a software start system according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 4 is a schematic diagram of a computer-readable storage medium according to an embodiment of the present application.

Detailed Description

Other advantages and advantages of the present invention will become apparent to those skilled in the art from the following detailed description, which, by way of illustration, is to be read in connection with certain specific embodiments, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Because the FPGA has the characteristics of programmability and high-performance calculation, AI calculation based on FPGA hardware is accelerated, and is widely applied to the field of computer vision processing. One of the most representative deployment modes is to use FPGA and CPU combinations to form a heterogeneous computing system.

The embodiment of the application mainly provides a new method for loading the FPGA program instead of hardware in the scene of CPU and FPGA, so that the FPGA is more convenient to debug, and the system power consumption can be reduced by configuring the running state of the FPGA. The method can upgrade the algorithm program of the FPGA under the condition of no service interruption.

Fig. 1 shows a software start method provided by an embodiment of the present application, where the method includes:

Step 101: cross compiling is carried out on the software started by the target to obtain an algorithm program running on the logic gate array FPGA;

Step 102: loading an algorithm program running on the FPGA into a memory with a fixed address through a CPU;

Step 103: configuring a wake-up register on the FPGA so that the FPGA enters an operating state after the algorithm program is loaded;

Step 104: a program entry register is configured on the FPGA so that the FPGA obtains an operation instruction according to the obtained fixed address in the memory;

Step 105: and configuring a calculation result register on the FPGA so that a result is sent to a CPU after the running of the FPGA is finished.

In one possible embodiment, the method further comprises: and reconfiguring the wake-up register on the FPGA to enable the FPGA to enter a sleep state again.

In one possible embodiment, the method further comprises: cross compiling is carried out on the target upgraded software to obtain an upgrade algorithm program running on the FPGA; loading an upgrade algorithm program running on the FPGA into a memory with a fixed address through a CPU; a program entry register is configured on the FPGA so that the FPGA obtains an upgrading instruction according to the obtained fixed address in the memory; and configuring a calculation result register on the FPGA so that the result is sent to the CPU after the FPGA is upgraded.

In one possible implementation manner, the loading, by the CPU, the algorithm program running on the FPGA into the fixed address memory includes: and loading a driving program on the CPU, checking a binary algorithm program running on the FPGA, and loading the binary algorithm program on a memory with a fixed address after error-free.

Under the heterogeneous scene of CPU+FPGA, the general CPU is often responsible for controlling the interaction and other processes of a user interface, and the hardware such as FPGA is used for completing the functions of deep learning on-line prediction, picture compression and decompression and the like which need a large amount of computation. In the development and debugging stage of the heterogeneous architecture, the FPGA needs to load different algorithm programs on line for debugging.

In summary, the embodiment of the present application proposes a new method to replace hardware to load FPGA program and start, and the specific flow is as follows:

in the first aspect, an algorithm program running on the FPGA is compiled first by cross-compiling.

In the second aspect, a binary program file running on the FPGA is loaded onto a fixed address memory by implementing a section of driver on the general CPU.

In a third aspect, a high-efficiency control protocol is implemented between the CPU and the FPGA: the CPU communicates with the FPGA through register operation. The specific implementation is as follows:

the FPGA is configured as a peripheral of the CPU, so that the control and interaction of the FPGA can be completed by the CPU through a register on the FPGA. The following functional registers are defined:

(1) FPGA wake-up register: after the FPGA is powered on, the FPGA is in a sleep state, so that the power consumption can be reduced;

(2) FPGA program entry register: after the FPGA wakes up, the starting address of the program is obtained from the register, and the instruction is executed from the starting address.

(3) FPGA calculation result register: after the FPGA completes a large number of parallel computing functions, the result is returned to the CPU through the register.

The specific implementation process is as follows:

After the program loading is completed, the CPU wakes up the FPGA by configuring an FPGA wake-up register, so that the FPGA enters a normal running state. The CPU informs the starting address of the program in the memory to the FPGA by configuring an FPGA program entry register, and the FPGA then takes out the instruction from the starting address and starts to run. Thus, the function of loading the FPGA program on line is completed. After the FPGA completes the calculation, the CPU is notified of the calculation result by configuring an FPGA calculation result register, and the CPU completes the storage and the post-processing of the calculation result. Finally, the CPU enables the FPGA to enter a sleep state again by configuring an FPGA wake-up register, so that the system power consumption is reduced.

It should be noted that, the functional registers configured in the method provided by the embodiment of the present application are not limited to the above several types, and the registers with corresponding functions are configured according to the needs during implementation.

Under the condition of no interruption of service, the algorithm program of the FPGA can be updated on line by the scheme, and the specific flow is as follows:

firstly, compiling an algorithm program running on the FPGA through cross compiling. After loading the program into the memory by the CPU, the CPU informs the FPGA of the initial address of the program in the memory by configuring an FPGA program entry register, and the FPGA then takes out the instruction from the initial address to start running. Thus, the function of online upgrading the FPGA program is completed. After the FPGA completes the calculation, the CPU is notified of the calculation result by configuring an FPGA calculation result register, and the CPU completes the storage and the post-processing of the calculation result.

It can be seen that under the heterogeneous scene of CPU+FPGA, the algorithm program on the FPGA is loaded and started by the CPU, and the FPGA is updated on line. The FPGA is more convenient to debug, and the system power consumption can be reduced by configuring the running state of the FPGA. Under the condition of no interruption of service, the algorithm program of the FPGA is upgraded.

In summary, the embodiment of the application provides a software starting method, which obtains an algorithm program running on a logic gate array FPGA by cross compiling target-started software; loading an algorithm program running on the FPGA into a memory with a fixed address through a CPU; configuring a wake-up register on the FPGA so that the FPGA enters an operating state after the algorithm program is loaded; a program entry register is configured on the FPGA so that the FPGA obtains an operation instruction according to the obtained fixed address in the memory; and configuring a calculation result register on the FPGA so that a result is sent to a CPU after the running of the FPGA is finished. The FPGA is more convenient to debug, and the system power consumption can be reduced by configuring the running state of the FPGA.

Based on the same technical concept, the embodiment of the application also provides a software starting system, as shown in fig. 2, wherein the system comprises:

The cross compiling module 201 is configured to cross compile the software started by the target to obtain an algorithm program running on the logic gate array FPGA;

The loading module 202 is configured to load, by using a CPU, an algorithm program running on the FPGA into a memory with a fixed address;

A first register configuration module 203, configured to configure a wake-up register on the FPGA, so that the FPGA enters an operation state after loading of the algorithm program is completed;

A second register configuration module 204, configured to configure a program entry register on the FPGA, so that the FPGA obtains an operation instruction according to the obtained fixed address in the memory;

and the third register configuration module 205 is configured to configure a calculation result register on the FPGA, so that after the FPGA finishes running, a result is sent to the CPU.

In a possible implementation manner, the first register configuration module 203 is further configured to:

In one possible embodiment, the system further comprises:

The cross compiling module 201 is further configured to cross compile the target upgraded software to obtain an upgrade algorithm program running on the FPGA;

The loading module 202 is further configured to load, by using a CPU, an upgrade algorithm program running on the FPGA into a memory with a fixed address;

the second register configuration module 204 is further configured to configure a program entry register on the FPGA, so that the FPGA obtains an upgrade instruction according to the obtained fixed address in the memory;

The third register configuration module 205 is further configured to configure a calculation result register on the FPGA, so that after the FPGA upgrade is finished, the result is sent to the CPU.

In one possible implementation, the loading module 202 is specifically configured to:

The embodiment of the application also provides electronic equipment corresponding to the method provided by the embodiment. Referring to fig. 3, a schematic diagram of an electronic device according to some embodiments of the present application is shown. The electronic device 20 may include: a processor 200, a memory 201, a bus 202 and a communication interface 203, the processor 200, the communication interface 203 and the memory 201 being connected by the bus 202; the memory 201 stores a computer program executable on the processor 200, and the processor 200 executes the method according to any of the foregoing embodiments of the present application when the computer program is executed.

The memory 201 may include a high-speed random access memory (RAM: random Access Memory), and may further include a non-volatile memory (non-volatile memory), such as at least one disk memory. The communication connection between the system network element and at least one other network element is implemented through at least one physical port 203 (which may be wired or wireless), the internet, a wide area network, a local network, a metropolitan area network, etc. may be used.

Bus 202 may be an ISA bus, a PCI bus, an EISA bus, or the like. The buses may be classified as address buses, data buses, control buses, etc. The memory 201 is configured to store a program, and the processor 200 executes the program after receiving an execution instruction, and the method disclosed in any of the foregoing embodiments of the present application may be applied to the processor 200 or implemented by the processor 200.

The processor 200 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 200 or by instructions in the form of software. The processor 200 may be a general-purpose processor, including a central processing unit (Central Processing Unit, abbreviated as CPU), a network processor (Network Processor, abbreviated as NP), etc.; but may also be a Digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 201, and the processor 200 reads the information in the memory 201, and in combination with its hardware, performs the steps of the above method.

The electronic device provided by the embodiment of the application and the method provided by the embodiment of the application have the same beneficial effects as the method adopted, operated or realized by the electronic device and the method provided by the embodiment of the application due to the same inventive concept.

The present application further provides a computer readable storage medium corresponding to the method provided in the foregoing embodiments, referring to fig. 4, the computer readable storage medium is shown as an optical disc 30, on which a computer program (i.e. a program product) is stored, where the computer program, when executed by a processor, performs the method provided in any of the foregoing embodiments.

It should be noted that examples of the computer readable storage medium may also include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, or other optical or magnetic storage medium, which will not be described in detail herein.

The computer-readable storage medium provided by the above-described embodiments of the present application has the same advantageous effects as the method adopted, operated or implemented by the application program stored therein, for the same inventive concept as the method provided by the embodiments of the present application.

It should be noted that:

The algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. Various general purpose devices may also be used with the teachings herein. The required structure for the construction of such devices is apparent from the description above. In addition, the present application is not directed to any particular programming language. It will be appreciated that the teachings of the present application described herein may be implemented in a variety of programming languages, and the above description of specific languages is provided for disclosure of enablement and best mode of the present application.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the above description of exemplary embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed application requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.

Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

Various component embodiments of the application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some or all of the components in the creation means of a virtual machine according to an embodiment of the present application may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present application can also be implemented as an apparatus or device program (e.g., a computer program and a computer program product) for performing a portion or all of the methods described herein. Such a program embodying the present application may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.

The present application is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of software initiation, the method comprising:

2. The method of claim 1, wherein the method further comprises:

3. The method of claim 1, wherein the method further comprises:

4. The method of claim 1, wherein loading, by the CPU, the algorithm program running on the FPGA into the fixed address memory, comprises:

5. A software start-up system, the system comprising:

6. The system of claim 5, wherein the first register configuration module is further to:

7. The system of claim 5, wherein the system further comprises:

8. The system of claim 5, wherein the loading module is specifically configured to:

9. An electronic device, comprising: memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor executes to implement the method according to any of the claims 1-4 when running the computer program.

10. A computer readable storage medium having stored thereon computer readable instructions executable by a processor to implement the method of any of claims 1-4.