CN114816273B

CN114816273B - Norflash-oriented adaptive optimal configuration method, device and medium

Info

Publication number: CN114816273B
Application number: CN202210736672.3A
Authority: CN
Inventors: 汪季英; 董宗宇
Original assignee: Hangzhou Youzhilian Technology Co ltd
Current assignee: Hangzhou Youzhilian Technology Co ltd
Priority date: 2022-06-27
Filing date: 2022-06-27
Publication date: 2023-06-09
Anticipated expiration: 2042-06-27
Also published as: CN114816273A

Abstract

The embodiment of the invention discloses a method, a device and a medium for adaptive optimal configuration for Norflash; the method may include: creating engineering for realizing the function of the Norflash carried on the system on chip SOC based on the debugging function of the SRAM so as to compile and obtain a debugging file comprising the optimal configuration parameters corresponding to the Norflash; after power-on, corresponding to entering a bootrom program execution stage, storing the debugging file in a memory and the head of a storage space of Norflash by running the bootrom program; after the power-on is started, the debug file stored in the head of the storage space of the Norflash is written into the memory corresponding to the entering of the execution stage of the application program, so that the Norflash and the corresponding QSPI bus are configured according to the optimal configuration parameters in the debug file, and the Norflash is operated in an XIP mode based on the optimal configuration parameters when the application program is operated.

Description

Norflash-oriented adaptive optimal configuration method, device and medium

Technical Field

The embodiment of the invention relates to the technical field of chips, in particular to a method, a device and a medium for adaptive optimal configuration of a code type flash memory Norflash.

Background

The characteristic of the coded flash memory Norflash is the execution of an on-chip (XIP) i.e. the processor can directly fetch instructions from the Norflash for subsequent decoding and execution during execution of an application program without having to read the instructions or code into system RAM.

In order to enable the Norflash to be compatible with various types of Norflash in the use process, the conventional scheme defaults to set a configuration parameter to meet the requirement that the Norflash of various types can operate in an XIP mode.

However, for various types of Norflash, taking a queue serial peripheral interface (QSPI, quad SPI) in a peripheral circuit thereof as an example, default configuration parameters set by registers of the corresponding QSPI are only used to satisfy that the corresponding Norflash operates in an XIP mode, and cannot be operated in an optimal configuration. Thus, in the current conventional scheme, even though Norflash can operate in XIP mode, the operating speed is still low.

Disclosure of Invention

In view of this, the embodiments of the present invention expect to provide a method, apparatus, and medium for adaptive optimal configuration for Norflash; the Norflash can be operated in the XIP mode under the condition of optimal configuration, so that the operation speed of the Norflash in the XIP mode is improved.

The technical scheme of the embodiment of the invention is realized as follows:

in a first aspect, an embodiment of the present invention provides a method for adaptive optimal configuration of a coded flash memory Norflash, where the method includes:

creating engineering for realizing the function of the Norflash carried on the system on chip SOC based on the debugging function of the SRAM so as to compile and obtain a debugging file comprising the optimal configuration parameters corresponding to the Norflash;

after power-on, corresponding to entering a bootrom program execution stage, storing the debug file in a memory and the head of the Norflash storage space by running the bootrom program;

after the power-on is started, the debug file stored in the head of the storage space of the Norflash is written into a memory corresponding to entering an application program execution stage, so that the Norflash and a corresponding QSPI bus are configured according to the optimal configuration parameters in the debug file, and the Norflash operates in an XIP mode based on the optimal configuration parameters when the application program operates.

In a second aspect, an embodiment of the present invention provides an apparatus for adaptive optimal configuration for Norflash, where the apparatus includes: a creation section, a bootrom program execution section, and an application program execution section; wherein, the liquid crystal display device comprises a liquid crystal display device,

the creating part is configured to create engineering for realizing the function of the Norflash carried on the system on chip SOC based on the debugging function of the SRAM so as to compile and obtain a debugging file comprising the optimal configuration parameters corresponding to the Norflash;

the bootrom program execution part is configured to store the debug file in the memory and the head of the storage space of the Norflash by running the bootrom program corresponding to entering the bootrom program execution stage after power-on;

the application program executing part is configured to write the debug file stored in the head of the storage space of the Norflash into a memory corresponding to entering an application program executing stage after power-on start-up so as to configure the Norflash and the corresponding QSPI bus according to the optimal configuration parameters in the debug file, so that the Norflash operates in an XIP mode based on the optimal configuration parameters when the application program operates.

In a third aspect, an embodiment of the present invention provides a computer storage medium, where a program for adaptive optimal configuration for Norflash is stored, where the program for adaptive optimal configuration for Norflash implements the method steps for adaptive optimal configuration for Norflash according to the first aspect when executed by at least one processor.

The embodiment of the invention provides a method, a device and a medium for adaptive optimal configuration for Norflash; creating engineering for the Norflash carried on the SOC by utilizing the function of loading code debugging at the SRAM, so as to compile and obtain a debugging file comprising the optimal configuration parameters corresponding to the Norflash; and then, copying the debug file to the head of the storage space of the Norflash through a bootrom program when the power-on is started, so that when an application program is executed, the debug file stored in the head of the storage space of the Norflash is written into a memory to perform optimal configuration on the Norflash and a corresponding QSPI bus, and the Norflash operates in an XIP mode under the condition of optimal configuration when the application program is operated, and the operating speed of the Norflash in the XIP mode is further improved.

Drawings

Fig. 1 is a schematic diagram of a system-on-chip that can be adapted to the technical solution set forth in the embodiments of the present invention.

Fig. 2 is a schematic flow chart of a method for adaptive optimal configuration for Norflash according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a memory address of Norflash according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a device with an adaptive optimal configuration for Norflash according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

Referring to fig. 1, there is shown the composition of an exemplary (and simplified) System On Chip (SOC) 100 that can be adapted to the teachings of embodiments of the present invention. It is noted that the composition shown in fig. 1 is just one example of a possible SOC composition, and that embodiments of the present disclosure may be implemented in any of a variety of SOC compositions as desired.

As shown in fig. 1, SOC 100 includes: of course, in the specific implementation process, those skilled in the art may add an adaptable component based on the structure shown in fig. 1 according to the actual scene, which is not described in detail in the embodiment of the present invention.

In some examples, the processor 110 may be a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The disclosure in connection with the embodiments of the present invention may be directly embodied as a hardware decoding processor executing or may be executed by a combination of hardware and software modules in the decoding processor.

In some examples, the on-chip Memory 120 may include Read-Only Memory (ROM) 121 and random access Memory (Random Access Memory, RAM) 122; the processor 110 may be connected to the on-chip memory 120 through an on-chip bus 140. It should be noted that, in general, the processor 110, the on-chip memory 120, and the on-chip bus 140 may be referred to as an SOC chip in some implementations, as shown in fig. 1.

In some examples, off-chip memory 130 may include coded Flash memory (Norflash) 131, and may also include storage Flash memory (NAND Flash) 132 in other examples; the processor 110 may be coupled to the off-chip memory 130 via an off-chip bus 150, for example, a Norflash 131 via a QSPI bus 151.

In some examples, processor 110 may include a QSPI controller 111 capable of performing read and write operations with Norflash 131, and may also include bootrom program 112 for booting up and upgrading SOC 100.

For SOC 100 shown in fig. 1, processor 110 enables Norflash 131 to implement an XIP mode of operation via QSPI bus 151 by way of QSPI controller 111. However, at present, each vendor is not compatible with each type of Norflash 131 of each vendor, and therefore, in the conventional chip design process, a default configuration parameter is set in the QSPI register that can be called by the QSPI controller 111, so that the finally designed SOC 100 can meet that all types of Norflash operate in XIP mode.

On the other hand, the various types of Norflash correspond to optimal configuration parameters, such as a maximum clock of a QSPI bus, a fast read command word, a fast write command word, and the like, and the optimal configuration parameters can enable the various types of Norflash to achieve an optimal operation effect, and the optimal configuration parameters corresponding to the various types of Norflash are different. Therefore, default configuration parameters adopted in the conventional scheme at present can only meet that various types of Norflash can be operated in an XIP mode, but cannot enable the various types of Norflash to be operated in the XIP mode under the optimal configuration. For example, the default configuration parameters adopted in the conventional scheme, the QSPI register will not normally set the maximum frequency division that the corresponding QSPI bus can actually reach, and the read-write command word is also a basic read-write command word instead of a fast read-write command word, which results in the situation that the optimal performance of Norflash is sacrificed for compatibility. Therefore, the embodiment of the invention expects to provide a scheme of adaptive optimal configuration for Norflash, which can enable the Norflash to operate in an XIP mode under the condition of optimal configuration compared with the conventional scheme, thereby improving the operating speed of the Norflash in the XIP mode. Based on this, referring to fig. 2 in conjunction with SOC 100 shown in fig. 1, a method for adaptive optimal configuration for Norflash according to an embodiment of the present invention is shown, where the method may be applicable to the exemplary SOC 100 shown in fig. 1, and the method may include:

s201: creating an engineering for realizing the function of the Norflash carried on the SOC 100 based on the debug function of a Static Random-Access Memory (SRAM) to compile and obtain a debug file comprising the optimal configuration parameters corresponding to the Norflash;

s202: after power-on, corresponding to entering a bootrom program execution stage, storing the debug file in a memory and the head of the Norflash storage space by running the bootrom program;

s203: after the power-on is started, the debug file stored in the head of the storage space of the Norflash is written into a memory corresponding to entering an application program execution stage, so that the Norflash and a corresponding QSPI bus are configured according to the optimal configuration parameters in the debug file, and the Norflash operates in an XIP mode based on the optimal configuration parameters when the application program operates.

For the technical scheme shown in fig. 2, using the function of code debugging loaded at the SRAM, creating engineering for the Norflash carried on the SOC, so as to compile and obtain a debug file including the optimal configuration parameters corresponding to the Norflash; and then, copying the debug file to the head of the storage space of the Norflash through a bootrom program when the power-on is started, so that when an application program is executed, the debug file stored in the head of the storage space of the Norflash is written into a memory to perform optimal configuration on the Norflash and a corresponding QSPI bus, and the Norflash operates in an XIP mode under the condition of optimal configuration when the application program is operated, and the operating speed of the Norflash in the XIP mode is further improved.

For the technical solution shown in fig. 2, in some possible implementations, the SRAM-based debug function creates an engineering for implementing the function of the Norflash carried on the SOC 100, so as to compile and obtain a debug file including the optimal configuration parameters corresponding to the Norflash, including:

determining optimal configuration parameters of Norflash loaded on the SOC, wherein the optimal configuration parameters at least comprise: the optimal clock frequency of the QSPI bus of the Norflash and the fast read and write command word of the Norflash;

creating engineering about the Norflash through the SRAM so as to realize the functions of initializing, chip signals, reading, writing and erasing of the Norflash;

and debugging the engineering related to the Norflash, establishing the engineering according to the correct interface function after confirming that the interface function related to the Norflash is correct, and compiling by combining the optimal configuration parameters to obtain an axf file comprising the optimal configuration parameters corresponding to the Norflash.

For the above implementation, it should be noted that, for Norflash, the optimal configuration includes the maximum clock corresponding to QSPI and fast read and write command words. At present, the Norflash chips of various types in the market have the same basic command names, such as read device 0x9F,read data 0x03, write enable 0x06, read status and the like, but the Norflash chips have different types for fast read/write command words, such as dual read/write and quad read/write. Specifically, after the Norflash chip has been fixedly mounted on the SOC 100, the command word for fast reading and writing of the Norflash and the optimal clock frequency of the QSPI bus may be determined according to the wiring of the QSPI bus and the chip manual of the Norflash that has been mounted on the SOC 100. For example, taking a wireless W25Q64JV model norflash chip as an example, the bus is a QSPI, and the optimal configuration can be determined as follows: the QSPI bus clock is the divide by 4 of the system clock, the fastest Read command word is Fast Read Quad I/O (0 xEB), and the Fast write command word is Quad Input Page Program (0 x 32). After the optimal configuration parameters are determined, engineering can be established through the SRAM to realize functions of initializing, chip model, reading, writing, erasing and the like of the Norflash, debugging is carried out, after the fact that the interface function of the Norflash has no problem through debugging is confirmed, engineering is additionally established for the interface functions, and the axf file with redirection is recompiled. The axf file includes the optimal configuration parameters.

For the technical solution shown in fig. 2, in some possible implementation manners, after the power-on, corresponding to entering a bootrom program execution stage, storing the debug file in the memory and the header of the storage space of the Norflash by running the bootrom program includes:

after the power-on starting, determining the BOOT0 pin level, and entering a bootrom program when the BOOT0 pin level is low level;

according to the bootrom program, the function of jumping to the SRAM is provided, and the debug file is read from the SRAM;

and storing the debugging file at an address head 1M of the storage space of the Norflash.

For the above implementation, in some examples, the storing the debug file at the address header 1M of the memory and the storage space of the Norflash includes:

the debug file is stored in a memory,

loading optimal configuration parameters in a debug file in an SOC execution memory when the bootrom program is executed;

and the bootrom program writes the debugging file into the address head 1M of the storage space of the Norflash according to the quick write command word in the optimal configuration parameter.

For the above implementation manner and the examples thereof, it should be noted that, after the SOC 100 is powered on and started, the level on the BOOT0 pin is first read, and if the level is low, a bootrom program is entered; if high, the XIP mode is performed, i.e. the application in Norflash is run. The implementation manner and the example correspondingly describe that the bootrom program stage is entered, namely the BOOT0 pin is low level; at this time, the bootrom program stage is to upgrade the application program, and store the application program in the designated location of the Norflash chip memory space. For example, the Norflash chip address 00 corresponds to a mapping address in the processor of 0x09000000, the range is 64M, the XIP mode boot code is typically run from the code at 0x09100000, then 1M space before the XIP mode boot code can store the debug files obtained by executing S201 as described above.

In addition, the execution process of the bootrom program is to finally write the bin file of the application program to the corresponding Norflash address, so by the above example, after the optimal configuration parameters are loaded, the bootrom program can store the application program in the Norflash according to the optimal configuration parameters, thereby completing the execution process of the bootrom program. Specifically, except for the debug file stored in the 1M space of the address header of the Norflash memory, the XIP mode start code starts at 0x09100000, as shown in fig. 3, the address of the Norflash memory can be used to store the execution file of the application program from 2M, specifically, the bootrom program uses the loaded optimal configuration parameters to burn the bin file content of the application program to the corresponding Norflash according to the hex file information, and the address is stored at the address after 2M space.

For the above implementation manner and the examples thereof, it should be further noted that, in the specific implementation process, the bootrom program cannot determine the signal of the external Norflash chip before curing, so that the fast read/write command word cannot be determined. The implementation manner and the example thereof utilize dynamic loading of the axf file, and apply the optimal configuration parameters of the axf file to the process of programming the debug file and the application program to the Norflash, so that the writing speed of the high bootrom can be provided.

For the technical solution shown in fig. 2, in some possible implementations, after power-on, corresponding to entering an application program execution stage, writing the debug file stored in the header of the storage space of the Norflash into a memory to configure the Norflash and the corresponding QSPI bus according to the optimal configuration parameters in the debug file, so that when the application program runs, the Norflash runs in an XIP mode based on the optimal configuration parameters, including:

after the power-on starting, determining the BOOT0 pin level, and when the BOOT0 pin level is high level, representing the execution of the application program stage;

copying a debugging file stored in the head 1M of the storage space of the Norflash to a memory through sequential addressing, and configuring the Norflash and a corresponding QSPI bus according to the optimal configuration parameters by utilizing the loading function of the debugging file;

and when the positions of the application programs in the storage space of the Norflash are sequentially addressed, the Norflash operates in an XIP mode based on the optimal configuration parameters so as to execute the application programs.

For the above implementation, specifically, in the design of an application program, an axf file stored at address 00 of a norfash needs to be copied into a memory; then, the dynamic loader function of the axf file is utilized to call the interface of the QSPI, and the QSPI is optimally configured; it should be noted that when the QSPI is optimally configured, the interrupt needs to be turned off, so that the execution speed of the XIP mode can be improved.

In addition to the above, the advantages of the above technical solution and implementation manner and examples thereof may be further described by a comparison experiment in which the mapping space of the setting processor 110 for the Norflash 131 externally connected to the QSPI interface 151 starts from 0x09000000, and the range is 64M. The XIP boot code starts to run from the code at 0x09100000, and the previous 1M address (0 x09000000 to 0x090 FFFFF) is an axf file for storing the optimal configuration parameters of the Norflash, so that at least 2Mbytes and above are required for the external Norflash space suggestion to meet the execution requirement of the application program, and in the comparative experiment, the external Norflash chip model is a winbond W25Q64JV.

In conventional approaches, the default configuration of the QSPI controller 111 of the processor 110 is as follows: the QSPI clock configuration is 8 frequency division of a system clock, a Read command word of the QSPI is Read Data (03 h) of a single line, and SPI bus transmission is actually adopted; in connection with what is set forth in the foregoing examples, these configuration parameters, while not optimal configuration parameters for a winbond W25Q64JV model Norflash chip, still enable the signal Norflash chip to operate in XIP mode.

By adopting the scheme provided by the embodiment of the invention, by means of the dynamic loading function of the configuration file, namely the axf file, the optimal configuration parameters in the axf file are loaded after the code starts to be executed, so that the Read Data command word is changed into Fast Read Quad I/O (EBh), and a QUAD-SPI bus is adopted. The maximum frequency of the QSPI clock is determined by code debugging in the engineering started by the SRAM, and the maximum frequency is obtained by dividing the system clock by 4 through debugging verification. By the scheme provided by the embodiment of the invention, the execution speed of the XIP mode is 8 times that of the conventional scheme. The advantages of the foregoing solutions, and of the implementations and examples thereof, are thereby better verifiable.

Based on the same inventive concept as the foregoing technical solution, referring to fig. 4, an apparatus 40 for adaptive optimal configuration for Norflash provided by an embodiment of the present invention is shown, where the apparatus 40 may be applied to the SOC 100 shown in fig. 1, and the apparatus 40 includes: a creation section 401, a bootrom program execution section 402, and an application program execution section 403; wherein, the liquid crystal display device comprises a liquid crystal display device,

the creating part 401 is configured to create an engineering for implementing the function of the Norflash carried on the system on chip SOC based on the debug function of the SRAM, so as to compile and obtain a debug file including the optimal configuration parameters corresponding to the Norflash;

the bootrom program executing section 402 is configured to store the debug file in the memory and the header of the storage space of the Norflash by running the bootrom program in response to entering the bootrom program executing stage after power-on;

the application program executing section 403 is configured to write the debug file stored in the header of the storage space of the Norflash into the memory after the application program executing section 403 is powered on, so as to configure the Norflash and the corresponding QSPI bus according to the optimal configuration parameters in the debug file, so that when the application program is running, the Norflash is running in XIP mode based on the optimal configuration parameters.

In some examples, the creation portion 401 is configured to:

In some examples, the bootrom program execution portion 402 is configured to:

the debug file is stored in a memory,

In some examples, the bootrom program execution part 402 is further configured to:

the bootrom program uses the loaded optimal configuration parameters, writes the bin file content of the application program to the corresponding Norflash according to the hex file information, and stores the address to the address after the 2M space;

in some examples, the application execution portion 403 is configured to:

It will be appreciated that in this embodiment, a "part" may be a part of a circuit, a part of a processor, a part of a program or software, etc., and of course may be a unit, or a module may be non-modular.

In addition, each component in the present embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional modules.

The integrated units, if implemented in the form of software functional modules, may be stored in a computer-readable storage medium, if not sold or used as separate products, and based on such understanding, the technical solution of the present embodiment may be embodied essentially or partly in the form of a software product, which is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or processor to perform all or part of the steps of the method described in the present embodiment. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Therefore, the present embodiment provides a computer storage medium, where a program for adaptive optimal configuration of Norflash is stored, where the method steps for adaptive optimal configuration of Norflash in the above technical solution are implemented when the program for adaptive optimal configuration of Norflash is executed by at least one processor.

It should be understood that the above exemplary technical solution of the device 40 for adaptive optimal configuration for Norflash belongs to the same concept as the technical solution of the method for adaptive optimal configuration for Norflash, and therefore, for details that are not described in detail in the above technical solution of the device 40 for adaptive optimal configuration for Norflash, reference may be made to the description of the technical solution of the method for adaptive optimal configuration for Norflash. The embodiments of the present invention will not be described in detail.

It should be noted that: the technical schemes described in the embodiments of the present invention may be arbitrarily combined without any collision.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for adaptive optimal configuration of a coded flash memory Norflash, the method comprising:

creating engineering for realizing the function of the Norflash carried on the system on chip SOC based on the debugging function of the SRAM so as to compile and obtain a debugging file comprising the optimal configuration parameters corresponding to the Norflash; wherein, the optimal configuration parameters at least comprise: the optimal clock frequency of the QSPI bus of the Norflash and the fast read and write command word of the Norflash;

after power-on is started, writing the debug file stored in the head of the storage space of the Norflash into a memory corresponding to entering an application program execution stage so as to configure the Norflash and a corresponding QSPI bus according to the optimal configuration parameters in the debug file, so that when the application program runs, the Norflash runs in an on-chip execution XIP mode based on the optimal configuration parameters;

after the power-on is started, the debug file stored in the header of the storage space of the Norflash is written into a memory corresponding to entering an execution stage of an application program, so that the Norflash and a corresponding QSPI bus are configured according to the optimal configuration parameters in the debug file, so that when the application program runs, the Norflash runs in an XIP mode based on the optimal configuration parameters, and the method comprises the following steps:

2. The method according to claim 1, wherein the debugging function based on the SRAM creates an engineering for implementing the function of the Norflash carried on the SOC to compile a debug file including the optimal configuration parameters corresponding to the Norflash, including:

determining optimal configuration parameters of Norflash carried on the SOC;

3. The method of claim 1, wherein storing the debug file in the memory and in the header of the Norflash memory space by running the bootrom program after the power-up corresponds to entering a bootrom program execution phase, comprising:

4. The method of claim 3, wherein storing the debug file at an address header 1M of a memory and a storage space of the Norflash comprises:

the debug file is stored in a memory,

5. A method according to claim 3, characterized in that the method further comprises:

and the bootrom program uses the loaded optimal configuration parameters, writes the bin file content of the application program to the corresponding Norflash according to the hex file information, and stores the address to the address after the 2M space.

6. An apparatus for adaptive optimal configuration for Norflash, the apparatus comprising: a creation section, a bootrom program execution section, and an application program execution section; wherein, the liquid crystal display device comprises a liquid crystal display device,

the creating part is configured to create engineering for realizing the function of the Norflash carried on the system on chip SOC based on the debugging function of the SRAM so as to compile and obtain a debugging file comprising the optimal configuration parameters corresponding to the Norflash; wherein, the optimal configuration parameters at least comprise: the optimal clock frequency of the QSPI bus of the Norflash and the fast read and write command word of the Norflash;

the application program executing part is configured to write the debug file stored in the head part of the storage space of the Norflash into a memory corresponding to entering an application program executing stage after power-on start-up so as to configure the Norflash and a corresponding QSPI bus according to the optimal configuration parameters in the debug file, so that when the application program is running, the Norflash runs in an on-chip execution XIP mode based on the optimal configuration parameters;

wherein the application program execution section is configured to:

7. The apparatus of claim 6, wherein the creation section is configured to:

determining optimal configuration parameters of Norflash carried on the SOC;

8. The apparatus of claim 6, wherein the bootrom program execution part is configured to:

9. A computer storage medium, characterized in that it stores a program for adaptive optimal configuration for Norflash, which when executed by at least one processor implements the method steps for adaptive optimal configuration for Norflash according to any of claims 1 to 5.