CN116185299A - Flash memory controller and related device and method - Google Patents
Flash memory controller and related device and method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present disclosure provides a flash memory controller and related apparatus and methods, the flash memory controller comprising: a register for storing configuration information including the number of blocks in the serial flash memory, the number of pages within a block, and the capacity of a page; the driving engine module is used for determining address information of a code storage area according to the configuration information and generating a second page reading command carrying the address information, and the code storage area has preset capacity and is the initial part of a data storage area in the serial flash memory; a command processing unit for reading the start code stored in the code storage area based on the second page read command; and the starting code storage unit is used for storing the starting code read by the command processing unit so that the processor can fetch the instruction from the starting code storage unit to execute the starting code. The method and the device effectively improve the starting speed of the chip by realizing the starting of the chip from the serial flash memory.
Description
Technical Field
The present disclosure relates to the field of chip technologies, and in particular, to a flash memory controller, and related devices and methods.
Background
In an embedded environment, the start-up speed of a System On Chip (SOC) is important for a user. The faster the system-on-chip is started, the faster the system can enter normal operation. The Nand Flash is widely applied to the system-level chip start of an embedded environment due to the characteristics of low cost and no data loss caused by power failure.
At present, a starting method of a system-level chip based on Nand Flash is generally as follows: after power-up, the processor of the system-level chip runs a boot loader (ROM) in the Read-Only Memory, the boot loader loads a boot code (i.e. Bootloader software) from Nand Flash to an on-chip Static Random-Access Memory (SRAM) or a double-rate synchronous dynamic Random Access Memory (DDR SDRAM), if the loading is successful, the processor of the system-level chip then runs the loaded boot code, the running of the boot code is used for loading an application program, and after the loaded application program is run, the starting of the chip is completed.
However, starting the execution of the boot program requires the processor to perform by fetching instructions, decoding, and executing, which consumes a portion of time; in addition, since the memory space of the on-chip rom is small, the boot code is usually divided into a plurality of stages, so that the processor is required to perform a plurality of loading operations on the boot code, and thus the whole boot process is long, and a long time is required for booting.
Disclosure of Invention
In order to solve the technical problems, the present disclosure provides a flash memory controller, and related devices and methods, which can effectively increase the chip start-up speed.
A first aspect of the present disclosure provides a flash memory controller, comprising:
a register for storing configuration information including the number of blocks in the serial flash memory, the number of pages within a block, and the capacity of a page;
the driving engine module is used for determining address information of a code storage area according to the configuration information and generating a second page reading command carrying the address information, and the code storage area has preset capacity and is the initial part of a data storage area in the serial flash memory;
a command processing unit for reading the start code stored in the code storage area based on the second page read command;
and the starting code storage unit is used for storing the starting code read by the command processing unit so that the processor can fetch the instruction from the starting code storage unit to execute the starting code.
Optionally, the driving engine module is further configured to generate a first page read command, where the first page read command carries address information of a set area in the serial flash memory;
the command processing unit is further configured to read initial setting information from the setting area based on the first page read command;
the initial setting information comprises the configuration information, a starting address and a length of a register to be configured, wherein the register stores the configuration information and is configured by the driving engine module according to the initial configuration information.
Optionally, the initial setting information further includes a start flag located at a start position thereof;
the driving engine module is also used for checking the initial mark, and analyzing the configuration information, the initial address and the length of the register to be configured from the initial setting information after the initial mark passes the check.
Optionally, the initial setting information further includes a cyclic redundancy check code;
the driving engine module is also used for calculating the cyclic redundancy check code of the initial setting information, comparing the calculated cyclic redundancy check code with the cyclic redundancy check code included in the initial setting information, and checking the initial mark if the calculated cyclic redundancy check code and the cyclic redundancy check code are the same.
Optionally, the initial setting information further includes an end flag, and the cyclic redundancy check code included in the initial setting information is located immediately before the end flag in the initial setting information.
Optionally, the driving engine module generates the first page read command if the processor recognizes that the boot mode is a boot from the serial flash memory.
Optionally, the set area is a first page of a first block of the serial flash memory, and the data storage area is located immediately after the set area in the serial flash memory.
Optionally, the flash memory controller is provided with a completion flag bit, and the register stores the completion flag bit after the configuration of the configuration information is completed;
and the driving engine module determines the address information of the code storage area according to the configuration information after detecting the completion flag bit and generates a second page reading command carrying the address information.
Optionally, the command processing unit reads the start code stored in the code storage area in a block-by-block manner, and reads a bad block flag field in a oob area of the read block, wherein if the read bad block flag field is different from a non-bad block flag, the command processing unit skips the block to continue reading the next block.
A second aspect of the present disclosure provides a method of chip booting from a serial flash memory, the method being performed by any one of the flash controllers of the first aspect.
A third aspect of the present disclosure provides a storage device comprising: a serial flash memory and any of the flash memory controllers described in the first aspect.
A fourth aspect of the present disclosure provides a system-on-chip comprising: a processor and a storage device as described in the third aspect.
The beneficial effects of the present disclosure are:
in the flash memory controller provided by the disclosure, a register is used for storing configuration information, wherein the configuration information comprises the number of blocks in a serial flash memory, the number of pages in the blocks and the capacity of the pages; the driving engine module is used for determining address information of a code storage area according to the configuration information and generating a second page reading command carrying the address information, and the code storage area has preset capacity and is the initial part of a data storage area in the serial flash memory; the command processing unit is used for reading the starting codes stored in the code storage area based on the second page reading command; the starting code storage unit is used for storing the starting code read by the command processing unit, so that the processor connected to the flash memory controller can directly fetch the command from the starting code storage unit to execute the starting code, the processor is not required to run a starting guide program, and the processor is not required to copy the starting code, thereby realizing the quick starting of the chip from the serial flash memory and effectively shortening the time consumption of the chip when the chip is started from the serial flash memory.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a system-on-chip according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of a flash memory controller according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram illustrating control of an exemplary dial switch provided by an embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating a format of initial setting information according to an embodiment of the disclosure;
FIG. 5 is a flow chart of a method for starting a chip from a serial flash memory according to an embodiment of the present disclosure;
fig. 6 is a flowchart illustrating an initialization process in a method for starting a chip from a serial flash memory according to an embodiment of the present disclosure.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
Flash memory is a non-volatile, writable memory that allows recorded data to be saved even when power is turned off, like read-only memory. According to the manufacturing method of flash memory, flash memory is mainly divided into two major types, namely parallel flash memory (parallel flash) and serial flash memory (serial flash).
In the parallel flash memory, basic memory cells (cells) are arranged in parallel between a bit line and a ground line. Typical parallel flash memories include charged erasable programmable read-Only Memory (EEPROM) and the like. A parallel flash memory is a memory device that allows access based on addresses in bytes, i.e., allows read and write operations to be performed on arbitrary addresses regardless of the order of the basic memory cells, that is, can be accessed randomly.
In a serial flash memory, basic memory cells are arranged in series between a bit line and a ground line. Typical serial Flash memories are NAND type Flash memory (i.e., NAND Flash), spi Nor type Flash memory, and the like. In general, a serial Flash memory is a memory device that allows access based on addresses in units of pages in such a manner that pages are first selected and then individual basic memory cells connected to each other in the pages are read, such as Nand Flash described above. However, the Spi Nor Flash physical structure described above has little bad blocks and bit reversal, thus supporting XIP (eXecute In Place) startup.
Specifically, the storage structure of the Nand Flash of the serial Flash memory is as follows: one memory includes a plurality of blocks (blocks), which are the minimum unit of erase operation; one block includes a plurality of pages (pages), which are the minimum unit of write operation. The page is in turn composed of an active data area and a spare area (spare area), also called oob (out of band) area, for hardware error correction and bad block management. The bad block is a unit area where the erasing operation cannot be performed, and is a block where the erasing operation must be performed before the writing operation. The 6 th byte of the oob area of the first page in the block is a bad block mark field, and if the field is the same as a non-bad block mark, the field indicates that the block is not a bad block and can be normally used; if the non-bad block flag is different, it indicates that the block is a bad block and cannot be used normally. The non-bad block flag is typically 0xff.
Serial flash memory has lower cost and better compatibility than parallel flash memory, and thus is widely used to store large data. However, serial Flash Nand Flash cannot implement XIP functions due to bad blocks and bit inversion problems, and is typically used as a device for auxiliary data storage. For the application of system-in-chip starting, the serial Flash memory Nand Flash stores the starting code, the starting code stored in the serial Flash memory Nand Flash needs to be copied to the on-chip static random access memory or the double-rate synchronous dynamic random access memory by the starting bootstrap program stored in the on-chip read-only memory running by the on-chip processor, and the starting code copied to the on-chip static random access memory or the double-rate synchronous dynamic random access memory can be directly run by the on-chip processor, so that the whole process involves more operations, and the starting of the system-in-chip consumes longer time.
In view of this, embodiments of the present disclosure provide a Flash memory controller (Flash memory controller, abbreviated as FMC) that enables a chip to be quickly booted from serial Flash memory Nand Flash. In the following description, serial Flash memory refers to a type of serial Flash memory that supports write access in units of pages and does not support XIP functions, including Spi Nand Flash, unless otherwise specified.
The flash controller and the serial flash memory provided by the embodiment of the disclosure can be used as a storage device as a whole, so that the storage device supports an XIP function. Fig. 1 illustrates a system-on-chip using a memory device 100, where the memory device 100 includes a flash controller 110 and a serial flash memory 120 provided in an embodiment of the disclosure, so that the memory device 100 supports XIP functions, and the system-on-chip includes a processor 200 capable of directly fetching instructions from the memory device 100 for a boot code to execute, thereby effectively reducing the time consumed when the system-on-chip is started.
Fig. 2 is a schematic structural diagram of a flash memory controller according to an embodiment of the disclosure. Referring to fig. 1 and 2, the flash controller 110 includes a register 111, a driving engine module 112, a command processing unit 113, and a start code storage unit 114.
The register 111 is used to store configuration information including the number of blocks in the serial flash memory 120, the number of pages within a block, and the capacity of a page. The capacity of a page refers to the capacity of valid data in the page. For example, the serial flash memory 120 has 1024 blocks, one block has 64 pages, one page has 2K bytes of valid data and 64 bytes of oob area, and then for the serial flash memory 120, the configuration information is: the number of blocks in the serial flash memory 120 is 1024, there are 64 pages in a block, and the capacity of a page is 2 kbytes.
The driving engine module 112 is connected to the register 111, and is configured to determine address information of the code storage area according to configuration information stored in the register 111 and generate a second page read command carrying the address information. Specifically, the code storage area has a predetermined capacity and is the beginning of the data storage area in the serial flash memory 120. The format of the second page read command may be: block address + page address, block address and page address combine form the address information of the code storage area, wherein, the block address represents which block the code storage area occupies, the length is decided by the quantity of the block included in the configuration information; the page address indicates which page is occupied in the last block of the blocks occupied by the code storage area, and the length is determined by the number of pages in the block included in the configuration information. For example, the block address in the serial flash memory 120 of 1024 blocks of the above example requires a length of 10 bits (since the 10 th power of 2 is just 1024), while the page address corresponding to 64 pages within a block requires a length of 6 bits (since the 6 th power of 2 is just 64). Further, the driving engine module 112 determines how many blocks the code storage area occupies and how many pages are occupied in the last block of the blocks occupied by the code storage area according to the number of pages in the block and the capacity of the pages, that is, assigns the block address and the page address with determined lengths. For example, the preset capacity is 1M, the serial flash memory 120 has 1024 blocks, one block has 64 pages, and one page has valid data of 2K bytes, and then the number of blocks occupied by the code storage area is 8, so that the code storage area is the first 8 blocks of the data storage area and the pages of the last block in the occupied blocks are all occupied, so that the block addresses are from 0000000000 to 0000000111, that is, the code storage area occupies the 0 th to 7 th blocks; the page addresses are from 000000 to 111111, that is, the 0 th to 63 th pages of the last block in the blocks occupied by the code storage area are occupied; the second page read command carries any one address of 0000000000 to 0000000111 and any one address of 000000 to 111111, eventually requiring traversing all blocks and all pages occupied by the code storage area. Here the ordering sequence number of the blocks and pages starts from 0. The preset capacity is the size of the starting code, and the code storage area is the area for storing the starting code.
The command processing unit 113 is connected to the drive engine module 112 and also to the serial flash memory 120. The driving engine module 112 generates a second page read command and then transmits the generated second page read command to the command processing unit 113, and the command processing unit 113 is configured to read the code storage area of the serial flash memory 120 based on the received second page read command. The code storage area stores the start code in advance, and thus the command processing unit 113 reads the start code from the code storage area.
The start code storage unit 114 is used for storing the start code read by the command processing unit 113. Boot code storage unit 114 is a memory space having a predetermined capacity and is coupled to processor 200. After the boot code is stored in the boot code storage unit 114, the processor 200 fetches an instruction from the boot code storage unit 114 to execute the boot code for such a boot mode as booting from the serial flash memory 120.
Specifically, the command processing unit 113 may be connected to the serial flash memory 120 through a serial peripheral interface (Serial Peripheral interface, abbreviated as SPI) bus, and the command processing unit 113 accesses a code storage area of the serial flash memory 120 as a master device on the serial peripheral interface bus. In some examples, the flash memory controller 110 further includes a data receiving controller 115 connected to the command processing unit 113 and a data buffering unit 116 connected to the data receiving controller 115 as shown in fig. 2. The command processing unit 113 may also transmit the data replied to the serial flash memory 120 to the data receiving controller 115 through the serial peripheral interface, and the data receiving controller 115 transmits the received data to the data buffering unit 116, in such a manner that the start codes can be all buffered into the data buffering unit 116 in the order of storage in the code storage area (i.e., the order of storage in the data buffering unit 116 after the start codes are buffered, and the order of storage in the code storage area are identical). After that, the boot codes buffered by the data buffer unit 116 are carried to the boot code storage unit 114 as indicated by dotted arrows in fig. 2, and the boot codes are stored in the boot code storage unit 114 in the order of storage in the code storage area. The handling process shown by the dotted arrow in fig. 2 may be performed by the data receiving controller 115 or may be performed by the driving engine module 112 controlling the command processing unit 113, which is not limited in the embodiment of the present disclosure.
In an alternative embodiment, the driving engine module 112 is further configured to generate a first page read command, where the first page read command carries address information of a set area in the serial flash memory 120; the command processing unit 113 is also configured to read initial setting information pageinfo from the setting area based on the first page read command; the initial setting information pageinfo includes configuration information, a start address and a length of a register to be configured, and the register 111 stores the configuration information configured by the driving engine module 112 according to the initial setting information.
Specifically, the driving engine module 112 determines the register 111 according to the start address and the length of the register to be configured, and the register 111 is a memory space with the length from the start address. The driving engine module 112 configures the configuration information into the register 111 starting from the start address, after which the driving engine module 112 automatically calculates the address to be configured next in the register 111 and configures the information at the address until the configuration information included in the initial setting information pageinfo is configured into the register 111 in its entirety.
The set area and the data storage area are predetermined areas in the serial flash memory 120. It may be that the storage space of the serial flash memory 120 is divided into a set area and a data storage area, i.e., the storage space of the serial flash memory 120 is constituted by the set area and the data storage area, and the set area is predetermined to precede the data storage area. For example, the set area is the first page of the first block of serial flash memory 120, and the data storage area is located immediately after the set area in serial flash memory 120, which facilitates flash controller 110 to quickly locate the set area and the data storage area. If the sequence number of the blocks in the serial flash memory 120 starts from 0 and the sequence number of the pages starts from 0, the setting area is page0 of block0 of the serial flash memory 120, and the initial setting information pageinfo can be pre-programmed into page0 of block0 of the serial flash memory 120; the data storage area is a page following page0 of block0 and a block following block0 of the serial flash memory 120.
In some examples, after the system on chip is powered on, the processor 200 first identifies a start-up mode, and the driving engine module 112 performs the above operation of generating the first page read command if the processor 200 identifies that the start-up mode is to start from the serial flash memory. If the processor 200 recognizes that the boot mode is not being booted from the serial flash memory, the driving engine module 112 does not perform the operation of generating the first page read command. The driving engine module 112 may be directly connected to the processor 200, and the processor 200 transmits information notifying the driving engine module 112 of the start mode after recognizing the start mode, so that the driving engine module 112 determines whether to perform the above-described operation of generating the above-described first page read command based on the information.
The processor 200 may identify the activation pattern by an input signal of the dip switch. The user can confirm the input signal of dial switch according to the demand before the chip is electrified, and power is supplied to the chip after the dial is completed, so that the processor 200 can identify the starting mode through the input signal of the dial switch after the chip is electrified. Fig. 3 is a schematic control diagram of an exemplary dial switch, where the dial switch involves 3 general purpose input/output interfaces (General Purpose Input Output, gpio for short), and the value of the input signal of each input/output interface may be 0 or 1, and the input signal of the dial switch is the combined value of the signals of the 3 general purpose input/output interfaces, that is, the gpio combined value illustrated in fig. 3. In fig. 3, if the gpio combination value is 100, the starting mode is to start from the rom, that is, the chip is started by executing the boot loader in the rom; if the gpio combination value is 010, the starting mode is to start from the random access memory, namely, the starting code in the random access memory is executed to realize the chip starting; if gpio is combined to be 001, the boot mode is to boot from serial flash memory, i.e. the chip is started by executing the boot code in the boot code storage unit 114. Under the condition, the chip supports three starting modes, and the starting is flexible.
The flash controller 110 may also set a completion flag bit. The configuration register 111 stores configuration information, which is a process of initializing the flash controller 110 in preparation for subsequent reading of the boot code from the serial flash memory 120. After the configuration of the configuration information stored in the register 111 is completed, the completion flag is set, which indicates that the initialization process of the flash controller 110 is completed. The driving engine module 112 performs the above-described operation of determining address information of the code storage area according to the configuration information and generating a second page read command carrying the address information after detecting the completion flag bit. If the drive engine module 112 does not detect the completion flag bit set, the above-described operation of determining the address information of the code storage area according to the configuration information and generating the second page read command carrying the address information is not performed. The completion flag bit plays a role in controlling the start of the start code reading start.
In the embodiment of the present disclosure, since the configuration information is included in the initial setting information pageinfo and is programmed in the serial flash memory 120 together, the flash controller 110 is compatible with the serial flash memory 120 having different block sizes and different page sizes, i.e., the flash controller 110 can determine the code storage area for the serial flash memory 120 having different block sizes and different page sizes, thereby allowing the chip to be quickly started up from the different serial flash memories 120.
In an alternative embodiment, the initial setting information pageinfo read by the command processing unit 113 further includes a start flag located at a start position of the initial setting information pageinfo, and the driving engine module 112 is further configured to check the start flag, that is, compare whether the start flag is a preset start flag, if the start flag is the preset start flag, the start flag is checked to be passed, otherwise, the start flag is checked to be failed. The driving engine module 112 analyzes the configuration information and the start address and length of the register to be configured from the initial setting information pageinfo after the start flag is checked. It should be understood that, in the case where the start flag is not checked, the initial setting information pageinfo is highly likely to be erroneous information, and thus the driving engine module 112 does not perform an operation of parsing the initial setting information pageinfo.
Further, the initial setting information pageinfo read by the command processing unit 113 further includes a cyclic redundancy check (Cyclic Redundancy Check, abbreviated as CRC) code, and the driving engine module 112 is further configured to calculate the cyclic redundancy check code of the initial setting information pageinfo, compare the calculated cyclic redundancy check code with the cyclic redundancy check code included in the initial setting information pageinfo, and perform the start flag checking operation if the calculated cyclic redundancy check code and the cyclic redundancy check code are the same. It should be understood that if the calculated crc code and the initial setting information pageinfo include crc codes different, it indicates that the initial setting information pageinfo read by the command processing unit 113 is erroneous, and thus the driving engine module 112 does not perform the above-described start flag checking operation.
It should be noted that, the cyclic redundancy check can reliably check the integrity of the initial setting information pageinfo to a large extent, but cannot reliably check the integrity of the initial setting information pageinfo. That is, the cyclic redundancy check code calculated above is the same as the cyclic redundancy check code included in the initial setting information pageinfo, and it is not possible to completely and reliably determine that no change has occurred in the initial setting information pageinfo because the polynomial used for the cyclic redundancy check is a linear structure, and it is very easy to intentionally change a plurality of data of the initial setting information pageinfo so that the changed initial setting information pageinfo and the initial setting information pageinfo before the change have the same cyclic redundancy check code.
Thus, the above cyclic redundancy check and start flag check are both to check whether the initial setting information pageinfo read by the command processing unit 113 is erroneous, and combining the cyclic redundancy check and start flag check improves the reliability of the accuracy check of the initial setting information pageinfo.
Further, the initial setting information pageinfo read by the command processing unit 113 further includes an end flag, and the cyclic redundancy check code included in the initial setting information pageinfo is located immediately before the end flag in the initial setting information pageinfo, so that the cyclic redundancy check code included in the initial setting information pageinfo can be accurately located when the cyclic redundancy check is performed.
Fig. 4 is a schematic diagram illustrating a format of initial setting information pageinfo according to an embodiment of the present disclosure. As shown in fig. 4, the initial setting information pageinfo includes, in order from front to back, a start flag, a start address and length of a register to be configured, configuration information, a cyclic redundancy check code, and an end flag.
As described above, the command processing unit 113 may be connected to the serial flash memory 120 through the serial peripheral interface bus, in which case the command processing unit 113 transmits a first page read command to the serial flash memory 120 through the serial peripheral interface to read the initial setting information pageinfo stored in the setting area of the serial flash memory 120. The initial setting information pageinfo read by the command processing unit 113 may be stored in the data buffer unit 116 via the data reception controller 115 shown in fig. 2, and this process is buffered in the data buffer unit 116 as the start code described above, which will not be described in detail. After all the data of the initial setting information pageinfo is buffered in the data buffer unit 116, the driving engine module 112 performs the above-mentioned cyclic redundancy check and even the start flag check on the initial setting information pageinfo buffered in the data buffer unit 116. After the start flag passes the verification, the driving engine module 112 parses the initial setting information pageinfo buffered in the data buffer unit 116 to obtain the start address and length of the register to be configured and the configuration information required by the configuration register 111.
In some examples, to ensure data security, the setup area of the serial flash memory 120 stores the initial setup information pageinfo in a specific ECC (Error checking and Correcting) format, and the command processing unit 113 correspondingly reads the initial setup information pageinfo stored in the setup area in this format.
In an alternative embodiment, the command processing unit 113 reads the code storage area of the serial flash memory 120 in a block-by-block manner, and reads the bad block flag field in the oob area of the block for the read block, wherein if the read bad block flag field is different from the non-bad block flag, the command processing unit 113 skips the block to continue reading the next block; if the read bad block flag field is the same as the non-bad block flag, the command processing unit 113 continues to read the block and reads the next block after the block is read, until the start code of the preset capacity is read, or until the target number of blocks is read based on the address information of the code storage area, where the target number is the number of blocks occupied by the code storage area included in the address information of the code storage area.
In the flash controller 110 provided in the embodiment of the present disclosure, in the process of implementing the quick start of the chip from the serial flash memory 120, there is no need to start the boot program, so there is no need to set a read-only memory for the system-level chip to store the boot program; in addition, the startup code does not need to be copied to the on-chip static random access memory or the double-rate synchronous dynamic random access memory, so that the system-on-chip is not required to set any one of the two memories to store the copied startup code, the on-chip static random access memory space or the double-rate synchronous dynamic random access memory space can be saved, and even the on-chip read-only memory and the random access memory can be omitted, thereby further having the advantages of reducing the area of the system-on-chip and reducing the cost of the system-on-chip.
Fig. 5 is a flowchart of a method for starting a chip from a serial flash memory according to an embodiment of the disclosure. Referring to fig. 5, a method for starting a chip from a serial flash memory includes:
step S110, determining address information of a code storage area according to configuration information stored in a register 111, wherein the configuration information comprises the number of blocks, the number of pages in the blocks and the capacity of the pages in the serial flash memory 120, and the code storage area has a preset capacity and is a starting part of the data storage area;
step S120, generating a second page read command carrying address information;
step S130 reads the boot code stored in the code storage area based on the second page read command and stores the read boot code in the boot code storage unit 140, so that the processor 200 connected to the flash controller 120 fetches an instruction from the boot code storage unit 140 to execute the boot code.
Further, the method for starting the chip from the serial flash memory further includes performing the initialization process shown in fig. 6 before step S110. As shown in fig. 6, the initialization process includes:
step S101, a first page read command is generated, wherein the first page read command carries address information of a set area in the serial flash memory 120;
step S102, reading initial setting information pageinfo from a setting area based on a first page reading command, wherein the initial setting information pageinfo comprises configuration information, a starting address of a register to be configured and a length;
step S103, determining the register 111 according to the start address and length of the register to be configured and configuring the configuration information included in the initial setting information pageinfo into the determined register 111.
The method of the disclosed embodiments is performed by any of the flash controllers 110 described above. By executing the method, the flash memory controller 110 reads the boot code stored in the code storage area of the serial flash memory 120 to the boot code storage unit 140, so that the processor 200 can fetch the instruction from the boot code storage unit 140 to directly execute the boot code, and therefore, the processor 200 is not required to run a boot program and the processor 200 is not required to copy the boot code, thereby realizing the quick start of the chip from the serial flash memory 120 and effectively shortening the time consumption when the chip is started from the serial flash memory 120.
The implementation details of the foregoing method embodiments are described in the foregoing apparatus embodiment section in detail, and reference may be made to the foregoing apparatus embodiment section, so that details are not repeated.
Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it is apparent that the above examples are merely illustrative of the present disclosure and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present disclosure.
Claims (12)
1. A flash memory controller, comprising:
a register for storing configuration information including the number of blocks in the serial flash memory, the number of pages within a block, and the capacity of a page;
the driving engine module is used for determining address information of a code storage area according to the configuration information and generating a second page reading command carrying the address information, and the code storage area has preset capacity and is the initial part of a data storage area in the serial flash memory;
a command processing unit for reading the start code stored in the code storage area based on the second page read command;
and the starting code storage unit is used for storing the starting code read by the command processing unit so that the processor can fetch the instruction from the starting code storage unit to execute the starting code.
2. The flash memory controller of claim 1, wherein,
the driving engine module is further configured to generate a first page read command, where the first page read command carries address information of a set area in the serial flash memory;
the command processing unit is further configured to read initial setting information from the setting area based on the first page read command;
the initial setting information comprises the configuration information, a starting address and a length of a register to be configured, and the register stores the configuration information and is configured by the driving engine module according to the initial setting information.
3. The flash memory controller of claim 2, wherein,
the initial setting information also comprises a starting mark positioned at the starting position of the initial setting information;
the driving engine module is also used for checking the initial mark, and analyzing the configuration information, the initial address and the length of the register to be configured from the initial setting information after the initial mark passes the check.
4. The flash memory controller of claim 3, wherein,
the initial setting information also comprises a cyclic redundancy check code;
the driving engine module is also used for calculating the cyclic redundancy check code of the initial setting information, comparing the calculated cyclic redundancy check code with the cyclic redundancy check code included in the initial setting information, and checking the initial mark if the calculated cyclic redundancy check code and the cyclic redundancy check code are the same.
5. The flash controller of claim 4, wherein the initial setting information further comprises an end flag, the initial setting information comprising a cyclic redundancy check code immediately preceding the end flag in the initial setting information.
6. The flash controller of claim 2, wherein the drive engine module generates the first page read command if the processor identifies that a boot mode is to be initiated from the serial flash memory.
7. The flash controller of claim 2, wherein the set area is a first page of a first block of the serial flash memory, the data storage area being located immediately after the set area in the serial flash memory.
8. The flash memory controller of claim 2, wherein,
the flash memory controller is provided with a completion zone bit, and the register stores the completion zone bit after the configuration of the configuration information is completed;
and the driving engine module determines the address information of the code storage area according to the configuration information after detecting the completion flag bit and generates a second page reading command carrying the address information.
9. The flash memory controller according to claim 1, wherein the command processing unit reads the boot code stored in the code storage area on a block-by-block basis and reads a bad block flag field in a oob area thereof for the read block, wherein the command processing unit skips the block to continue reading the next block if the read bad block flag field is different from a non-bad block flag.
10. A method of starting up a chip from a serial flash memory, characterized in that the method is performed by a flash memory controller according to any of claims 1-9.
11. A memory device, comprising: a serial flash memory and a flash memory controller as claimed in any one of claims 1 to 9.
12. A system-on-chip, comprising: a processor and a storage device as claimed in claim 11.
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| CN116578352A (en) * | 2023-07-11 | 2023-08-11 | 沐曦集成电路(上海)有限公司 | Chip initializing system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116578352A (en) * | 2023-07-11 | 2023-08-11 | 沐曦集成电路(上海)有限公司 | Chip initializing system |
| CN116578352B (en) * | 2023-07-11 | 2023-09-22 | 沐曦集成电路(上海)有限公司 | Chip initializing system |
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