KR101146059B1 - Nonvolatile memory system, and data read/write method for nonvolatile memory system - Google Patents

Abstract

A nonvolatile memory system includes a nonvolatile memory having a plurality of data areas; And a memory controller operative to control read and write operations to this nonvolatile memory. The memory controller continuously executes read / write operations for a plurality of sectors in the selected data area of the nonvolatile memory in accordance with the command input from the host device and the sector count and sector address.

Nonvolatile Memory, Read, Write, Memory Controller, Host, Sector

Description

NONVOLATILE MEMORY SYSTEM, AND DATA READ / WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM}

The present invention relates to a nonvolatile memory system comprising a nonvolatile memory and a memory controller operative to perform read / write control for the memory, and a method of reading / writing data in a nonvolatile memory system.

NAND type flash memory is known as one of the EEPROM (eletrically erasable programmable nonvolatile semiconductor memory). NAND-type flash memory has a smaller unit cell area than NOR-type and is easy to mass store. The read / write speed per cell is slower than the NOR type, but the effective cell range (physical page length) for executing read / write operations simultaneously between the cell array and the page buffer can be extended to substantially achieve fast read / write operations. Can be.

Through the effective use of this feature, NAND type flash memory has been used in various recording media including file memory and memory cards.

In a memory card or the like, the nonvolatile memory and the memory controller are packaged together to execute read / write control for the nonvolatile memory in accordance with commands and logical addresses input from the host. For example, logical addresses and sector counts are input from the host to read data from a plurality of sectors as proposed (JP 2006/155335 A).

In one aspect, the present invention provides a nonvolatile memory system connectable to a host device. The system includes a nonvolatile memory having a plurality of data areas; And a memory controller operative to control read and write operations to this nonvolatile memory. The memory controller continuously executes read / write operations for a plurality of sectors in the selected data area of the nonvolatile memory in accordance with the command, sector count, and sector address input from the host device.

In one aspect, the present invention provides a data read / write method for a nonvolatile memory system connectable to a host device. The system includes a nonvolatile memory having a plurality of data regions and a memory controller operative to control read and write operations to the nonvolatile memory. The method includes providing a command, sector count and sector address from a host device; And continuously executing a read / write operation on a plurality of sectors in the selected data area of the nonvolatile memory according to the command, sector count, and sector address under the control of the memory controller.

1 is a diagram illustrating an LBA-NAND memory system configuration according to an embodiment of the present invention.

2 is a diagram illustrating a functional block of an LBA-NAND memory.

3 is a diagram illustrating a memory cell array configuration in an LBA-NAND memory.

4 is a diagram illustrating a pin configuration in the LBA-NAND memory.

5 is a diagram illustrating pin names and functions of the LBA-NAND memory.

6 is a diagram illustrating system data written in an LBA-NAND memory.

7 is a diagram illustrating an operation mode of an LBA-NAND memory with instructions.

8 is a diagram illustrating an example of switching between operating modes of an LBA-NAND memory.

9 is a diagram illustrating another example of switching between operating modes of an LBA-NAND memory.

10 is a diagram illustrating a data structure in an LBA-NAND memory.

11A is a diagram illustrating an instruction configuration for an LBA-NAND memory (part 1).

11B is a diagram illustrating an instruction configuration for an LBA-NAND memory (part 2).

11C is a diagram illustrating an instruction configuration for an LBA-NAND memory (part 3).

11D is a diagram illustrating an instruction configuration for an LBA-NAND memory (part 4).

11E is a diagram illustrating an instruction configuration for an LBA-NAND memory (part 5).

11F is a diagram illustrating an instruction configuration for an LBA-NAND memory (part 6).

11G is a diagram illustrating an instruction configuration for an LBA-NAND memory (part 7).

11H is a diagram illustrating an instruction configuration for an LBA-NAND memory (part 8).

11I is a diagram illustrating an instruction configuration for an LBA-NAND memory (part 9).

11J is a diagram illustrating an instruction configuration for an LBA-NAND memory (part 10).

12 is a list of instructions for an LBA-NAND memory.

13 is a diagram illustrating latch timing of various signals for an LBA-NAND memory.

14 is a diagram illustrating command input period timing in the same manner.

15 is a diagram illustrating command input period timing for a power saving mode in the same manner.

16 is a diagram illustrating command input timing after data reading in the same manner.

17 is a diagram illustrating the address input period timing in the same manner.

18 is a diagram illustrating the address input period timing for the peak current reduction mode in the same manner.

19 is a diagram illustrating data input timing in the same manner.

20 is a diagram illustrating serial read timing in the same manner.

21 is a diagram illustrating state read timing in the same manner.

22 is a diagram illustrating read cycle timing in the same manner.

23 is a diagram illustrating the serial EEP mode setting timing in the same manner.

24 is a diagram illustrating an example of selection from a PNR mode and a serial EEP mode using a common pin.

25 is a timing diagram in PNR mode with error checking (1-1).

Fig. 26 is a timing diagram in PNR mode with error checking (1-2).

27 is a timing diagram in PNR mode with error checking (1-3).

28 is a timing diagram in PNR mode with error checking (1-4).

29 is a timing diagram in PNR mode with error checking (1-5).

30 is a flowchart of the PNR mode.

31 is a timing diagram of read access in the basic MDA mode (one sector).

32 is a timing diagram of read access in the basic MDA mode (for 256 sectors).

33 is a timing diagram of read access in the basic MDA mode (for 64K sectors).

34 is a timing diagram of reading in the MDA mode interrupted using the end command.

35 is a timing diagram of a read in MDA mode with a retransmission request.

36 is a timing diagram when a new sequence is restarted after input of an end command.

37 is a timing diagram of read access in the MDA mode of optional read type B (1).

38 is a timing diagram of read access in the MDA mode of optional read type B (2).

39 is a timing diagram of read access in the MDA mode of optional read type B (3).

40 is a timing diagram of read access in MDA mode of optional read type B (4).

Fig. 41 is a timing diagram of read access in MDA mode of selective read type C (1).

42 is a timing diagram of read access in MDA mode of optional read type C (2).

43 is a timing diagram of read access in MDA mode of optional read type C (3).

44 is a timing diagram of read access in MDA mode of optional read type C (4).

45 is a timing diagram of readings in the MDA mode when illegal access occurs (case 1).

46 is a timing diagram of readings in the MDA mode when illegal access occurs (case 2).

47 is a timing diagram of write access in the MDA mode (one sector).

48 is a timing diagram of write access in the MDA mode (for 256 sectors).

49 is a timing diagram of write access in the MDA mode (for 64K sectors).

50 is a timing diagram of write access in the MDA mode interrupted using an end command.

51 is a timing diagram of write access in MDA mode with data retransmission.

Fig. 52 is a diagram illustrating the types of write errors when writing MDA mode.

53 is a timing diagram of MDA mode write of selective write type.

54 is a timing diagram of MDA mode write when illegal access occurs (case 1).

55 is a timing diagram of MDA mode write when illegal access occurs (case 2).

56 is a timing diagram of read access in the basic PNA mode.

57 is a timing diagram of a read access in a PNA mode interrupted using an end command.

58 is a timing diagram of read access in PNA mode with reread.

59 is a timing diagram of read access in the PNA mode of the optional read type B (1).

60 is a timing diagram of a read access in PNA mode of optional read type B (2).

Fig. 61 is a timing diagram of read access in the PNA mode of the optional read type B (3).

62 is a timing diagram of read access in PNA mode of optional read type B (4).

63 is a timing diagram of read access in PNA mode of optional read type C (1).

64 is a timing diagram of read access in PNA mode of optional read type C (2).

65 is a timing diagram of read access in the PNA mode of optional read type C (3).

66 is a timing diagram of read access in the PNA mode.

67 is a timing diagram of write access in the PNA mode interrupted using the end instruction.

68 is a timing diagram of write access in PNA mode upon data retransmission associated with a transmission error.

69 is a timing diagram of write access in the PNA mode of the optional write type.

70 is a timing diagram of write access in the VFA mode of a basic write type.

71 is a timing diagram of reading in the VFA mode interrupted using the end command.

72 is a timing diagram of read access in the VFA mode for rereading.

73 is a timing diagram of read access in the VFA mode of optional read type B (1).

74 is a timing diagram of read access in the VFA mode of optional read type B (2).

75 is a timing diagram of read access in the VFA mode of optional read type B (3).

76 is a timing diagram of read access in the VFA mode of optional read type B (4).

77 is a timing diagram of read access in the VFA mode of optional read type C (1).

78 is a timing diagram of read access in the VFA mode of optional read type C (2).

79 is a timing diagram of read access in the VFA mode of optional read type C (3).

80 is a timing diagram of write access in the VFA mode (one sector).

81 is a timing diagram of write access in the VFA mode (256 sectors).

82 is a timing diagram of write access in a VFA mode interrupted using an end instruction.

83 is a timing diagram of write access in VFA mode with error recovery.

84 is a timing diagram of write access in the VFA mode of selective write type.

85 is a diagram illustrating a flow in a PNR mode including error processing.

86 is a diagram illustrating a flow in PNR, VFA, MDA modes including error processing in read access.

87 is a diagram illustrating a flow in PNR, VFA, and MDA modes including error processing in write access.

88 is a timing diagram of execution of a change command for changing an arbitrary mode to an MDA mode.

89 is a timing diagram of execution of a change command for changing an arbitrary mode to the PNA mode.

90 is a timing diagram of execution of a change instruction for changing any mode to the VFA mode.

91 is a timing diagram of registration of a NOP instruction.

92 is a timing diagram of registration of another NOP instruction.

93 is a timing diagram of an operation associated with a firmware reload command.

94 is a timing diagram of a busy / ready change command.

95 is a timing diagram of an ID read command.

96 is a timing diagram of a status read command.

97 is a timing diagram of a password setting command.

98 is a timing diagram of a VFA device setting command.

99 is a timing diagram of a firmware update execution command.

100 is a timing diagram of an address reset command.

101 is a timing diagram of a firmware reload command.

102 is a timing diagram of a read / write end command.

103 is a timing diagram of a firmware updater transfer command.

104 is a diagram illustrating the relationship between host I / O and LBA-NAND memory internal operations.

105 is a diagram illustrating a flow of error processing at firmware update.

106 is a timing diagram of a data refresh execution command.

107 is a timing diagram of an MDA area erase command.

108 is a timing diagram of a flash cache execution command.

109 is a timing diagram of a transport protocol setting command.

110 is a timing diagram of a minimum busy time setting command.

111 is a timing diagram of a power saving mode setting command.

112 is a timing diagram of a read to which a power saving mode setting command is applied.

113 is a timing diagram of an instruction latch to which a power saving mode setting command is applied.

114 is a timing diagram of a power saving mode end command.

115 is a timing diagram of an address information acquisition command.

116 is a timing diagram of a maximum capacity information acquisition command.

117 is a timing diagram of a pin information acquisition command.

118 is a timing diagram of a read associated with a read retry command.

119 is a timing diagram of sector read type A with status information read.

120 is a timing diagram of sector read type B with status information read.

121 is a timing diagram of sector read type C with status information read.

122 is a timing diagram of sector write type A with state information reading.

123 is a timing diagram of sector write type B with state information reading.

124 is a diagram for explaining the operation of status information reading in the PNR mode.

125 is a view for explaining the operation of status information reading in the VFA / MDA mode.

126 is a view for explaining operation of status information reading in the boot code holding mode.

FIG. 127 is a diagram collectively showing each operation mode and wave mode switching of the LBA-NAND memory.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

[Memory System Overview]

The nonvolatile memory system of this embodiment is configured in a memory module including a single or a plurality of NAND type flash memory and a memory controller operative to execute read / write control on the memory. All mounted flash memories can be controlled from a single memory controller as logical memory referred to as Logical Block Address NAND flash memory (hereinafter abbreviated as LBA-NAND memory).

The LBA-NAND memory has a plurality of data areas (logical block access areas) that can be changed in accordance with instructions. Specifically, the present embodiment includes the following three data areas, which are divided based on the purpose and reliability of the data.

(1) A program area for a vendor application, that is, a "vendor application firmware area", hereinafter referred to as a "VFA" area.

(2) A program area for an end user application, that is, a "music data area", hereinafter referred to as an "MDA" area.

(3) A system data recording area for recording boot data of the host system, that is, a "pure NAND area" excluding the VFA and MDA areas, hereinafter referred to as "PNA" area.

The PNA area is given a normal access mode (hereinafter referred to as "PNA" mode) for execution of a read / write operation depending on input commands and addresses, and additionally two read only modes to be set at power up.

One is a read mode that is set to the input of a first PNA read mode command after power up. This is hereinafter referred to as "PNR (Pure NAND Read) mode".

The other is set as input of a second PNA read mode command after power up for serial read in SPI (Serial Peripheral Interface) mode in synchronization with an external clock. This is hereinafter referred to as "serial EEP" mode.

These two read modes are identical for reading the boot data of the host itself from the LBA-NAND memory and the system data needed for the read / write operation to the LBA-NAND memory. Thus, the PNR mode can be interpreted as including both in a broad sense and the serial EEP mode can be considered a special mode among the PNR modes.

The system data (firmware FW) and boot data required for the memory controller are automatically read from the flash memory and transferred to the data register (buffer RAM) in an initialization operation (power input initial setting operation) which is executed automatically after the power is applied. This read control is executed in, for example, a hardware sequencer prepared in a memory controller.

When the host enters a command at any time after power-up, the PNR mode or serial EEP mode is set to read the system data set in the data register of the LBA-NAND memory. The memory controller may boot after the data has been read and entered into the PNR area at the host (or in parallel).

Apart from the read mode for the PNR region at power up, the mode for read and write access to the PNA, MDA and VFA regions can be set according to the command. These are hereinafter referred to as PNA access mode, MDA access mode, and VFA access mode.

In the application program area or the VFA and MDA areas, the data transfer unit of read / write access is one sector (512 bytes or 528 bytes), and the data transfer format is SSFDC (Solid State Floppy Disk Card) format. LBA-NAND memory uses sector multiples to select the number of sectors accessible at one time using an access command. The user can, for example, choose among sector multiples of 1, 4 and 8.

The use of sector counts allows many consecutive sectors to be accessed per command. That is, with this command, the host device provides a sector count and sector address (logical address) initial value indicating the amount of data so that data can be read continuously from or written to a plurality of sectors sequentially from the plurality of sectors defined by it. To be possible.

Specifically, one address input consists of 5 bytes, of which the first half of two bytes are allocated to the sector count and the second half of three bytes are allocated to the sector address. This access mode allows the sector count and sector address to be identified using the address condition ID command. The byte count of this address input is scalable.

A mode change command is input to change the mode of the LBA-NAND memory. That is, at power up, the PNR mode or serial EEP mode is changed to the MDA access mode with the input of a special command. In addition, the input of the special change command is changed between the PNR mode, the VFA access mode, and the MDA access mode.

The internal chip enable signal / CE is generated at the memory controller. Each flash memory test is controlled using this signal.

The erase and reset commands for the LBA-NAND memory are NOP. Upon issuing this command, control does nothing and returns Ready to the host.

LBA-NAND Memory Configuration

1 illustrates a configuration of an LBA-NAND memory 20 that is a nonvolatile memory system according to an exemplary embodiment. This memory 20 includes a NAND-type flash memory chip 21 and a memory controller 22 that serves to execute read / write control for the memory, both of which are packaged in one piece.

The flash memory chip 21 may include a plurality of memory chips. 1 shows two memory chips, chip 1 and chip 2, which in this case can be controlled from a single memory controller 22. The maximum number of mountable memory chips can be determined from the regulator's current capability and other factors, for example four chips.

The memory controller 22 is a one-chip controller, comprising: a NAND flash interface 23 for processing data transfer to / from the flash memory chip 21; A host interface 25 for handling data transmission to / from the host device; A buffer RAM 26 serving to temporarily hold read / write data and the like; An MPU 24 operative to execute data transfer control; And a hardware sequencer 27 for use in read / write sequence control for the firmware FW in the NAND type flash memory 21, and the like.

It is not essential for this LBA-NAND memory system that the memory chip 21 and the memory controller 22 consist of different chips. FIG. 2 shows the functional block configuration of the LBA-NAND memory 20 of FIG. 1, where the logic control of the memory chip 21 and the memory controller 22 are shown together. 3 shows a cell array configuration of the memory core.

The memory cell array 1 includes a plurality of electrically erasable programmable nonvolatile semiconductor memory cells M0 connected in series to form one of the arrayed NAND cell units (NAND string) NU as shown in FIG. 3. -M31) (32 memory cells in the example shown).

One end of the NAND cell unit NU is connected to the bit lines BLO and BLe through the selection gate transistor S1, and the other end thereof is connected to the common source line CELSRC through the selection gate transistor S2. The memory cells M0-M31 each have a control gate connected to the word lines WL0-WL31. The selection gate transistors S1 and S2 have gates connected to the selection gate lines SGD and SGS.

A group of NAND cell units arrayed along a word line constitutes one block, which is a data erasing minimum unit, and a plurality of such blocks BLK0-BLKn-1 are aligned along bit lines as shown.

The sense amplifier circuit 3 is aligned at one end of the bit lines BLO and BLe for cell data read and write operations. The row decoder 2 is aligned at one end of the word line to selectively drive the word line and the selection gate line. In the case shown, the even bit line BLe and the adjacent odd bit line BLO are selectively connected to each sense amplifier SA in the sense amplifier circuit 3 via a bit line selector.

Commands, addresses and data are input via the input controller 13. The chip enable signal / CE, the write enable signal / WE, the read enable signal / RE, and other external control signals are input to the logic circuit 14 for use in timing control. This command is decoded in the command decoder 8.

The controller 6 serves to perform control of data transfer and sequence control of write / erase / read. The status register 11 serves to provide a ready / busy state of the LBA-NAND memory 20 to a Ready / Busy terminal. Apart from this, the status register 12 is prepared to notify the host through the I / O port of the status of the memory 20 (pass / fail, ready / busy, etc.).

This address is passed to the row decoder 2 (including the pre-row decoder 2a and the main row decoder 2b) and the column decoder 4 via the address register 5. The write data is loaded into the sense amplifier circuit 3 (including the sense amplifier 3a and the data register 3b) through the I / O control circuit 7 and the control circuit 6. Read data is provided externally through the control circuit 6 and the I / O control circuit 7.

The high voltage generator 10 is provided to generate the required high voltage according to different operating modes. The high voltage generator 10 generates any high voltage based on a command given from the control circuit 6.

Fig. 4 shows a package pin configuration in the LBA-NAND memory of this embodiment, and Fig. 5 summarizes the pin names and functions. These figures together show the package pin configuration in a conventional NAND type flash memory (4Gbit SLC Large Block) for comparison.

Input / output ports (I / O1-I / O8) are used for input / output of commands, addresses and data on a byte basis. The external control signal terminal includes a chip enable signal (/ CE), a write enable signal (/ WE), a read enable signal (/ RE), an instruction latch enable signal (CLE), and an address latch enable signal (ALE). It may include terminals for.

I / O signals are address, data or command signals. The instruction latch enable (CLE) signal is a signal that controls the operation command in the LBA-NAND memory. When this signal is set to the "H" level in response to the rising or falling of the write enable (/ WE) signal, the data at the input / output port (I / O0-I / O7) is LBA-NAND as command data. Can be taken from memory.

The address latch enable (ALE) signal is a signal that controls taking address data from the LBA-NAND memory. When this signal is set to the "H" level in response to the rising or falling of the write enable (/ WE) signal, the data at the input / output port (I / O0-I / O7) is LBA-NAND as address data. Can be taken from memory.

The chip enable (/ CE) signal is a device select signal that sets the low power standby mode when set to the "H" level in the ready state.

The write enable (/ WE) signal is a signal that takes data from an input / output port (I / O0-I / O7) and inputs it to the device.

The read enable (/ RE) signal is a signal that allows input / output ports (I / O0-I / O7) to provide data externally in series.

The memory of this embodiment has the same signal terminal alignment as that of the conventional NAND flash memory seen in the host device, and can be treated as a conventional NAND flash memory as one feature. That is, the host interface 25 shown in FIG. 1 has the same electrical configuration as the NAND flash interface 23.

Thus, it can be treated like a conventional NAND flash memory, except that the address supplied from the host is a logical address rather than a physical address on the NAND flash memory 21. The logical address supplied from the host performs address translation in the MPU 24 to access the NAND type flash memory 21.

"DATA" and "CLK" are data and clock terminals for use in the operation of the LBA-NAND memory 20 in the serial EEP mode, and "/ HOLD" is its pause terminal.

The custom control pins "COM0", "COM1" and "COME" are prepared for use in requesting current information and special data input / output for the device.

Fig. 6 shows a recording state of system data (including boot data) of the host system to be recorded in the PNA area. This system data is written in the preceding block BLK0 in the flash memory chip 21. The system data is required to have high reliability, and therefore the following is particularly considered.

Of the word lines WL0-WL31 in one block, at least the word lines WL0 and WL31 at both ends are not used because the cell adjacent to the selection gate transistor has a larger write disturbance than the other cells. Alternatively, much higher data reliability can be ensured through the use of word lines every two lines or every few lines.

The cell array has the same read / write range as the even page selected using the even bit line BLe and one word line and the odd page selected using the odd bit line BLO and one word line. System data is written to only one of these pages (even pages in this example). The use of bit lines every few lines is also effective for higher reliability.

As the minimum process specification (design rule) becomes smaller, the interference between adjacent cells causes greater data variation. Thus, this embodiment guarantees the reliability of system data through the use of even or odd pages only.

For example, if the LBA-NAND memory is a multivalue memory capable of storing two bits (four values) of data in one memory cell, two page addresses, i.e., upper page and lower page, are allocated with two bits. Even when LBA-NAND memory is used to store multiple values in this way, a binary storage scheme using only lower pages is preferably applied to the portion of the system data that needs to have higher reliability.

As shown in Figure 6, only the lower pages of even pages are used for the system data portion.

In serial EEP mode, the output of system data is performed in the form of data including redundant areas. If a data error of any symbol occurs at the time of reading, this data is replaced with a spare block. If a data error of eight or more symbols occurs, the uncorrected data is output as is and the read error is displayed in the state.

[System overview and mode change]

7 summarizes the system overview of the LBA-NAND memory. As described above, this memory has three data areas, namely PNA, VFA and MDA areas, and additionally has a controller system area. This controller system area is the area where the firmware (FW) of the memory controller in the LBA-NAND memory is stored.

As the " pure NAND " mode, there is a PNR mode, which is a read mode for the PNA area set at power on. The PNR mode is set using the commands <00h>-<Add>-<30h>. In this case, the address <Add> is a dummy address.

In this example, <h> in the command represents a hexadecimal number. In practice, an 8-bit signal of "00000000" is given in parallel to eight input / output ports (I / O0-I / O7).

Examples of "LBA-NAND" modes are PNA access mode, VFA access mode, and MDA access mode for use in read / write access to the PNA, VFA, and MDA regions, respectively.

Changing between the PNR mode, PNA access mode, VFA access mode, and MDA access mode is performed using instructions. 8 and 9 show two mode change diagrams.

As shown in FIG. 8, using COME = "L" (or COME = "H") and PNR mode commands <00h>-<Add>-<30h>, the PNR mode is set after power-up. After completion of work in PNR mode, the input of command <FCh> causes a transition to MDA access mode.

The input of the change command then makes it possible to change between the access modes PNA-MDA-VFA.

As shown in FIG. 9, using COME = "H", COM0 = "H", and COM1 = "L", the serial EEP mode is set after power-up. Serial EEP mode is a mode in which data readable in the PNR is provided externally through the serial EEP interface. As a serial EEP interface, an SPI interface can be adopted.

Even in this case, after completion of the operation, the input of the command <FCh> causes a transition to the MDA access mode. The input of the change command then makes it possible to change between the access modes PNA-MDA-VFA.

[Data structure]

10 shows data structures in different data areas.

Data in the PNA area is given a transmission unit of 2112 bytes (2048 bytes + 64 bytes) for reading and writing. When all data is output serially, they are provided sequentially from the first sector to the 256th sector on a sector basis (= 2112 bytes), resulting in a total of 512 KB (= 540,6278 bytes).

For sector multiple 1 (SM = 1), the VFA and MDA areas are given a total of 528 bytes of transmission in the data format shown, including 512 bytes (data body) and 16 bytes for read and write (surplus data). . CRC data and ECC data are generated at the host device at the time of writing and at the memory controller of the LBA-NAND memory at the time of reading.

Part of the 512 bytes is stored in NAND flash memory. Of the transmitted data, only the data body is written. In practice, the extended 16 bytes are deleted from the flash memory, and the ECC code is generated in accordance with the write data and stored with this write data.

The accuracy of the transmitted data is checked with 6 bytes of ECC data at the memory controller of the LBA-NAND memory at the time of writing and at the host system at the time of reading.

It is possible to execute read / write operations in units of 512 bytes of transmission except for 16 bytes of excess data. This can be changed and set using configuration commands that instruct to modify or change the data configuration.

The sector multiple of SM = 4 or 8 is a data transfer unit of 2 KB or 4 KB. These are done through four or eight iterations of the SM = 1 data format.

In the mode of updating the firmware (FW) of the controller from the host, the write data transfer is executed in units of 528 bytes as shown. The VFA area has a basic data size of 8 MB, can be modified using a resize command, and has a selectable capacity of up to 32 MB in a capacity modification unit of 256 KB. The data to be stored includes only the data body and no redundant area data is stored. The ECC code input at the time of data writing is used only for confirmation of transmission data and is corrected when a 1 bit error occurs.

The resize / password is set in the next command sequence.

Resize: <00h>-<Config: A5>-<New value: 1 byte>-<Dummy: 3 bytes>-<57h>

Change Password: <00h>-<Config: 11>-<Last PW (Password): 2 bytes>-<New PW: 2 bytes>-<57h>

As the capacity of the VFA region increases or decreases, the capacity of the MDA region decreases or increases accordingly. The output format in MDA access mode is SSFDC mode of +16 bytes. Of the 16 bytes extended, valid data is only 6 bytes of ECC data and other data is ignored / invalidated.

Command structure

11A-11J illustrate instruction structures in different modes of operation. In these figures, <> represents an input to the LBA-NAND memory, and [] represents an output from the LBA-NAND memory. Further, (B2R) indicates that the busy / ready signal RY / BY transitions to busy and then returns to ready.

The PNR mode is a read mode that does not require address input and the address is input as a dummy (command number 1 in Fig. 11A). In this PNR mode, data is read sequentially from logical address LBA = 0 in units of 2112 bytes.

In the MDA access mode, read / write is executed successively for a plurality of sectors in the next command sequence, where after one command, sector count <SC> and sector address (initial value) <SA> are input (FIG. 11A). Command number 2).

Readout:

(1) <00h>-(SC: 2Byte)-(SA: 3Byte)-<30h>-(B2R)-[Data] -... <00h>-(DummyAdd)-<30h>-[Data]. ..; or

(2) <00h>-(SC: 2Byte)-(SA: 3Byte)-<30h>-(B2R)-[Data]-<F8h>-(B2R)-[Data] ...; or

(3) <00h>-(SC: 2Byte)-(SA: 3Byte)-<30h>-(B2R)-[Data]-(B2R)-[Data]-(B2R)-[Data] ...

entry:

(1) <80h>-(SC: 2Byte)-(SA: 3Byte)-<data>-<10h>-(B2R) -... <80h>-(DummyAdd)-<data>-<10h>- (B2R) ...; or

(2) <80h>-(SC: 2Byte)-(SA: 3Byte)-<data>-<15h>-(B2R)-<F2h>-<data>-<10h>-(B2R)-<F2h> -<data>-<10h>-(B2R) ...

PNA access mode is performed similarly to MDA access mode (command number 3 in FIG. 11A). At the time of writing, write data of 2112 bytes / instruction is written using an area of 4224 bytes. At the time of writing, all data is stored with the ECC.

The VFA access mode is also similar to the MDA access mode (command number 4 in FIG. 11A).

The mode change command code is prepared for the change from the PNR mode to the MDA access mode, the change from the serial EEP mode to the MDA access mode, and the change between the MDA access mode-PNA access mode-VFA access mode, respectively (FIG. 11A). Command number 5).

In command number 7 of FIG. 11A, the firmware (FW) reload command “command-911” is used to reread the FW of the controller stored in the flash memory chip. When the operation of the memory controller becomes a problem, a reconfiguration of the buffer RAM is required and this command is executed accordingly. Using this command, the data in the buffer RAM is backed up, and after executing the system boot, the system returns to the MDA access mode. The minimum busy time is 1 second.

Execution of the IF read command makes it possible to read the ID code assigned to each I / O port as shown in command number 9 of FIG. 11B. Specifically, ID data (with erase block size of 128K bytes and page length of 2K bytes) and ID data for actual LBA-NAND memory are emulated according to the ID code for emulation of 4Gbit NAND flash memory of binary storage type. Can be read separately using.

As shown in FIG. 11C, status information may be output to the host using a status read command. Specifically, as shown in FIG. 11C, information such as general pass / fail, transmission error pass / fail, ready / busy, and special information unique to the LBA-NAND, such as power save mode, operation mode, and other modes, may be issued a command. Can be selected. Apart from the ready / busy terminals, this status information is provided to the input / output port (I / O).

For the pass / fail associated with I / O1 and I / O2, the former represents the summary of the command in summary bits when a large number of sectors are sent using one command. In contrast, the latter shows the result of a pass / fail for which data transfer is intended just before the implementation of the health check. Both of these include transmission error pass / fail.

Password setting and modification are executed using a user-specified command (command number 11 in FIG. 11D).

The VFA unit setting command is used to set the capacity size of the VFA area up to 32 MB in 256 KB units (command number 12 in Fig. 11D). The input value is an integer multiple of 256 KB ("04h 00h" through "00h 00h"). This command is used to erase old VFA data and MDA data.

The FW update execution command is used to validate the updated FW data at the host to the buffer RAM of the memory controller and to transfer and write it to the NAND flash memory (command number 13.1 in FIG. 11D).

The address reset command is used to clear the sector count and the sector address (command number 13.2 in Fig. 11D). After completion of the command, the system can return to PNR mode and resume PNR mode from address 00h. This command is valid in the PNR.

The FW reload command is applied to reread the FW from flash memory and is used when the FW update from the host fails (command number 13.3 in FIG. 11D).

The end command is used to force the end of the read / write. Once this command is entered, new data is no longer allowed and all remaining data in the buffer RAM is written to the flash memory (command number 14 in Fig. 11D). After writing is complete, the system returns Ready to the host. Writing is performed until it passes. If the write cannot be completed at the write time tPROG, control proceeds to error termination.

The Send FW Update command (command number 15 in FIG. 11D) is used to update the FW when a bug caused by the FW is found after sending it to the user. The FW rewrite command is prepared during setup by the user to provide an environment that allows for easy execution of FW updates in the market.

In the operational sequence of instructions, data is updated in the buffer RAM and then validated. This data is given additional CRC16 data at intervals of 512 bytes. The memory controller performs a data comparison and, in the event of a failure, returns a transmission error to the host. Data correction of the SSFDC is not performed.

The data refresh command (command number 16 in FIG. 11D) is presented to the user as the recommended command. In this case, the detrimental effects (for example, the possibility of power interference and the problem of power consumption) are clearly expressed.

The secure erase command (command number 17 in Fig. 11D) is a command used to erase the entire data in the MDA area from the flash memory.

The flush cache (flash-cache) command (command number 18 in FIG. 11D) is a command for which issuance from the host is recommended before powering down. This allows the system to terminate all of the incomplete processing at the controller and return the ready to the host.

The transport protocol setting command (command number 19 in Fig. 11E) is used to correct the condition used in the system. Modifiable conditions are given in the table.

The first byte is used to set the ECC / CRC16 check / correction condition and the transmission sector size (ie, sector multiple). When an error bit is detected with the ECC check enable, the transfer result is notified to the status register. By retransmission of the data at this stage, non-error correction data can be written.

The second byte in the table of FIG. 11E is used to set the optional read / write style. Specifically, as the reading mode, it is possible to set type B for continuing the reading operation with the use of the continuation command <48h / F8h>, in contrast to the normal reading type A. It is possible without setting the type C to continue reading by using the busy status signal B2R to repeat (B2R)-[Data]-(B2R).

As the writing style, it is possible to set the normal writing type A and the type B which continues the write operation excluding the address input.

The minimum busy time setting command (command number 20 in FIG. 11F) is applied to set the host detectable minimum busy time as shown in the table. The memory controller sets a busy time longer than the minimum busy time.

A power save mode setting and canceling command (command number 21 in FIG. 11F and command number 22 in FIG. 11G) is used to set and cancel the low power consumption mode for the LBA-NAND module.

An address information acquisition command (command number 23 in Fig. 11F) is used to provide address space information as shown in the table. The address space information includes information showing the number of bytes allocated to the sector address and the sector count, respectively.

The MDA area capacity acquisition command (command number 24 in FIG. 11G) is used to identify the allocation size of the MDA area in each product. Specifically, it is provided to the input / output port as the maximum address represented by a 5 byte logical address. For example, in the case of 4G bytes, 5 byte data is formed as indicated in the table.

The pin information acquisition command (command number 25 in Fig. 11H) is used to show the status of the user specified control pin detected by the LBA-NAND module. Specifically, the situation of COME, COM0, COM1 can be seen as in the table.

Without interpreting the meaning of the command in the controller, the mode command performs a mode change by directly informing the NAND flash memory 21 of access to the host I / F 25 in the LBA-NAND memory 20 from the host device. Passing (command number 26 in FIG. 11H); A firmware update instruction (command number 27 in FIG. 11H) for use in updating the firmware at the MPU in the memory controller; And other commands such as a read retry command (command number 28 in FIG. 11H) to direct the reread.

The VFA unit acquisition command (command number 29 in Fig. 11i) is used to identify the allocation size of the VFA area in each product.

The transfer protocol acquisition command (command number 30 in FIG. 11I) is used to identify the data transfer protocol for the LBA-NAND memory as shown in the table.

The minimum busy time acquisition command (command number 31 in FIG. 11I) allows the host to identify the operating state of the LBA-NAND memory as shown in the table.

12 summarizes the commands.

[Basic Timing Diagram]

The input / output timing of commands, addresses and data in different operation modes will be described in detail below.

FIG. 13 is a diagram of basic timing normally applied for command, address, and data input. The address latch enable ALE, the instruction latch enable CLE, and the like are enabled. Thereafter, after waiting a certain set time, the write enable / WE is set to " L " to allow input of a signal such as a command. This input signal is latched in response to the transition of / WE to "H".

14 is a timing diagram of command input. The instruction latch CLE is "H", the chip enable (/ CE) is "L", the address latch enable (ALE) is invalidated, and the write enable (/ WE) is "L". The command "CMD" is then allowed to enter in synchronization with the transition of / WE to "H".

15 is a timing diagram of command input for a power saving mode, which is basically the same as that shown in FIG.

16 is a timing diagram of the next command input after data reading. An address input between commands <00h> and <30h> allows reading of the data. Then, after any busy, the read enable / RE is input to enable the read data Dout0-DoutN to be output on a sector basis in synchronization with this.

Thereafter, when the instruction latch enable CLE goes back to " H " and the write enable / WE goes to " L ", the next command < 00h > is allowed for input after reading data.

17 is a timing diagram of an address input. During the duration of " H " after the address latch enable ALE becomes " H ", the sector counts of 2 bytes SC0, SC1 and the subsequent sector addresses of 3 bytes SA0, SA1, SA2 are write enable (/ WE). It is input in synchronization with. This enables continuous data access within the logical address range determined from the sector count and sector address (initial value).

18 is basically the same as FIG. 17 as a timing diagram of an address input in a power saving mode. It is possible to set the power saving mode through selection of the valid period tADDP of the instruction latch enable CLE and the periods tWHP and tWPP of the "H" and "L" levels of the write enable / WE.

19 is a timing diagram of data input. After command and address input, it is possible to input data in synchronization with the write enable (/ WE).

20 is a timing diagram of data read from a cell array and read out in series. Data read from the cell array may be serially transmitted and output in synchronization with the read enable (/ RE) on a byte basis. During this output operation, a write operation to the NAND flash memory can be executed so that the LBA-NAND memory outputs a ready.

21 is a read timing of status data (pass / fail, ready / busy and others). In synchronization with the write enable (/ WE), the status read command "CMD" is input. Then, in synchronization with the read enable (/ RE), the state "ST" can be read.

Fig. 22 is a timing diagram of a data read period including a command input and an address input. As described above, as located between the first command <00h> and the second command <30h>, the sector count SC and the sector address SA are input to perform a read operation on the cell array.

Then, after any busy time, using the toggle of the read enable (/ RE), the read data is output in series as shown in FIG.

23 shows setting timing of the serial EEP mode at power input. After initial setup at power up and when the LBA-NAND memory is ready, the signal level at the user-specified control pin is identified for mode setting.

Specifically, with COME = "H", COM0 = "H", and COM1 = "L", the SPI mode (ie, serial EEP mode) is set. The entry of the command <FCh> cancels this mode.

24 summarizes the conditions for PNR mode selection. Serial EEP mode is indicated as "PNR with SPI". A typical PNR mode may be set to only COME = "L", and also COME = "H" and COM0 = COM1 = "H", or COME = "H" and COM0 = COM1 = "L". Alternatively, the setting can be accomplished when one of these custom control pins is open and the other two pins are at the appropriate level.

[PNR Mode Read Timing]

25-28 are timing diagrams of a PNR mode which is a read operation when power is input in the PNR area, and shows a case of having an error check. 25 shows non-error data transmission.

As described above, using the command input and the dummy address input, reading starts after any busy time. When the state is Pass ("P"), the same read operation is repeated up to the 256th sector as well.

Fig. 26 shows a handling method for the case where a state indicating an error "E" is obtained. Upon reception of the error "E", an address removal command "FFh" is input to execute reading again from the first address.

FIG. 27 shows an example of forcing a power off, rebooting, and reading again when a state indicating an error "E" is likewise obtained.

Fig. 28 shows a handling method for the case where the host executes a data check and detects a data transmission error. In this case, upon receiving the error detection, the host inputs an address removal command " FFh " to execute reading once again from the first address.

Fig. 29 shows an example in the case where the host inputs the same sector address of this data to read the same data again after detecting the data transmission error.

30 illustrates the PNR mode operation described in FIGS. 25-28 summarized in a series of flows. The system is started (step S1), a command and an address are input (step S2) to start a read operation.

If an error is detected by status check (step S3), an error sequence is executed (step S4). In this case, the address removal command " FFh " is input to erase the address in order to restart the read operation from the beginning. Alternatively, the power supply is shut off to restart the read operation from the beginning.

If an error is detected by the transmission data check at the host (step S6), a handling method is selected (step S7) to execute the error sequence (step S7) or to retransmit data at the same address (step S5).

If there is no error in the data transmission of one transmission unit, it is determined whether all the data are read out (step S8). If not read, the same read operation is repeated while incrementing one address until all data is read (step S9).

[MDA access mode for reading]

Various access timings in the MDA access mode are described below.

31 is a timing diagram when one sector is read in the MDA area. As described above, with the command, the sector count M and the sector address N (start address LBA) are input. Thereafter, after any busy, the data can be read in synchronization with the read enable (/ RE).

32 is a timing diagram of reading in the same manner continuously from the first sector (LBA = 30h) to the 256th sector (LBA = 12Fh). After each sector is read, a command and an address are input but this is a dummy address. The actual address is sequentially incremented internally according to the first entered sector address (initial value) and sector count.

33 is a timing diagram of reading continuously from the first sector (LBA = 30h) to the 64Kth sector (LBA = 1002Fh) in the same manner.

34 illustrates a read operation interrupted using the end command <FBh> during the waiting (ready) of the host in the read sequence.

35 is a process chart when a data transfer error occurs during multi-sector read. When the host detects a data transfer error, it issues a retry command <31h> to request a retransmission to the LBA-NAND. This may cause the same data to be reread.

36 is another processing diagram when a data transmission error occurs in the same manner. In this case, the host detects a transmission error and issues an end command <FBh>. This makes it possible to end the read operation once and read back with the read command and address input.

37-40 are read timing diagrams for optional read type B. FIG.

Fig. 37 is a timing diagram when a transfer protocol setting command is used to set an optional read type B, i.e., when a continue command <F8h> is input after each sector data read to continue a read operation. When the continue command clock is input over the number of output requests (sector counts), a fixed value <FFh> is output. In short, the LBA-NAND outputs a fixed value and waits for a shutdown command sent from the host.

38 is a timing diagram when the continue command <F8h> is used to continue the read operation and the end command <FBh> is used to end the continued read operation.

39 is a timing diagram when the continue command <F8h> is used to continue the read operation as well and the retry command <31h> is used to retransmit the same sector data as in the immediately preceding read.

40 is a timing diagram when the continue command <F8h> is likewise used to continue the read operation and the same continue command <F8h> is used to execute the interruption so as to omit the data read operation. In this example, one sector contains 2112 bytes of data D0-D2112. During the second sector read, a continuation command <F8h> is input when data D0-D256 is read, thereby skipping the data read operation.

Read access using the optional read mode C in the MDA access mode is described next with reference to FIGS. 41-44.

41-44 are timing charts when a read operation is continued without finding an instruction period for each read operation on a sector basis. FIG. 41 shows an example in which data reading is executed with only read enable (/ RE) only when the / RE input exceeds the number of output requests and the fixed value <FFh> is output. The LBA-NAND memory outputs a fixed value and waits for a shutdown command sent from the host.

42 is a timing diagram when applied to end the read operation in the same read operation as in FIG. 41.

FIG. 43 is a timing diagram when the host detects a data transfer error, issues a data transfer retry command <31h>, and retransmits the same data, for example, in the same read operation as in FIG.

FIG. 44 is a timing diagram when an end command <FBh> is applied to end a read operation once and a new command is issued to execute the read operation again in the same read operation as in FIG. 41.

45 and 46 are read timing diagrams in the MDA access mode when illegal access occurs during a read operation. The VFA access mode and the PNA access mode have the same preparation for this illegal access.

45 relates to the case where a new command is input without executing this command during execution of a read command. In this example, after the sector data at LBA = 30h is read, a new command and a new address are input. In this case, the new address is treated as a dummy and the read is executed continuously according to the previous input address.

46 relates to the case where a new write command is input without terminating this command during execution of a read command. In this example, the previous read command is automatically terminated to validate the write command.

In the case of sector multiples of SM = 4 or 8, it is necessary to issue an end command in order to end the read and shift to the next stage at a stage smaller than the sector count.

[MDA access mode for writing]

An example of write timing in the MDA access mode is described next.

47 is a timing diagram of one sector write in MDA access mode. A write command and a write address (i.e., sector count = 1 and sector address) are input, and write data of one sector is input to the NAND flash memory to be written. During writing, Busy is output to the host.

After completion of writing, input of status read command <70h> allows the status data to be read.

48 is a timing diagram when the same starting logical address LBA = 30h is used for continuously writing 256 sectors set using the sector count. After the passage of each sector write is confirmed from the state data ("P"), the dummy address and write data input are repeated for successive writes to the 256th sector.

Figure 49 is a timing diagram of a similar successive write for a 64K sector with a dummy address input.

Fig. 50 relates to the case where the end command <FBh> is input in the ready state (Ready) during the write sequence started from the start address LBA = 30h, whereby the end of the write sequence is forced.

Fig. 51 is a timing diagram of a process recommended when the status of a write command indicates a write error ("E"). If the write error is ECC-uncorrectable, the same address is re-entered as shown to effect retransmission.

As shown in FIG. 52, write status information is assigned to an I / O port and classified into four cases: pass, ECC-correctable transmission error, ECC-transmit transmission error, and write failure. Thus, the determination of this makes it possible to select execution of data rewriting or termination of the writing sequence.

FIG. 53 is a timing diagram of an optional write format that allows writing to continue with command <80h> and data input and without dummy address input. FIG.

54 and 55 show cases where illegal access occurs. The handling method for this illegal access is similarly applicable to the PNA access mode and the VFA access mode.

54 relates to the case where a new write command and an address are input without ending this command during execution of the write command. In this case, the new input address is treated as a dummy address and therefore the contents of the address are ignored. Thus, writing is performed for the next sector determined from the first input sector count and the address initial value.

55 relates to the case where a read command is input during execution of a write command. In this case, the LBA-NAND memory finishes writing and executes a read command.

[PNA Access Mode for Reading]

Among the modes or PNA modes for accessing the PNA region, read access is described first. In the PNA access mode, the access unit has a sector length of 2 KB (= 2112 bytes), a maximum sector count of 256 sectors, and a maximum capacity of 512 KB (= 540,672 bytes).

Fig. 56 is a timing diagram when the preceding address LBA = 00h is input to read 256 sectors (i.e., the entire PNA area). At a two byte sector count and a three byte sector address, only the first one byte of each is valid and the others are dummy.

57 relates to the case where the end command <FBh> is input in the state of Ready to forcibly terminate the read operation.

58 relates to the case where a read retry command <31h> is input in the ready state to output the immediately preceding read data again.

59-65 illustrate optional read modes in PNA access mode. Among these, FIGS. 59-62 relate to the case where the transfer protocol setting command is applied to set the read type B, that is, the case where the continue command <F8h> is used to continue the read operation.

In FIG. 59, the continue command <F8h> is input after each sector data read in order to continue the read operation. If the continue command clock is input beyond the number of output requests (sector counts), a fixed value <FFh> is output. If the LBA-NAND memory outputs a fixed value, the host sends an end command to end the command.

Fig. 60 is a timing diagram when the continue command <F8h> is likewise used to continue the read operation and the end command <FBh> is used to end the continued read operation.

Fig. 61 is a timing diagram when a continuation command <F8h> is likewise used to continue a read operation and a retry command <31h> is input to retransmit the same sector data as in the immediately preceding read.

FIG. 62 is a timing diagram when a continue command <F8h> is likewise used to continue a read operation and the same continue command <F8h> is used to execute an interruption to omit a data read operation. In this example, one sector contains 2112 bytes of data D0-D2112. During the second sector read, a continuation command <F8h> is input when data D0-D256 is read, whereby the data read operation is omitted.

63-65 relate to the case where the transfer protocol setting command is applied to set the read type C, that is, the read operation continues without the use of the continue command <F8h>.

In Fig. 63, sector data readout is repeated continuously, and a busy state signal is inserted between them. If the sector count is exceeded, a fixed value <FFh> is output. In this case, the LBA-NAND memory outputs a fixed value, and the host sends an end command to end the command.

64 is a timing diagram when a similar read type C is applied to continue a read operation and an end command <FBh> is used to end a continued read operation.

65 is a timing diagram when a similar read type C is applied to continue a read operation and a retry command <31h> is input to retransmit the same sector data as in the last read.

[PNA Access Mode for Writing]

The write timing of the PNA access mode is described next.

Fig. 66 is a timing diagram when the preceding address LBA = 00h is input to execute writing for all sectors (256 sectors) in the PNA area. After the identification of the write confirms a pass (" P "), a dummy address is input along with the write data to perform the continuous write.

Fig. 67 is a timing chart when an end command <FBh> is inputted to forcibly end writing.

68 shows an example of retransmission of the same address and data for writing when the host detects a write error "E".

Fig. 69 is a timing diagram of writing using an optional writing format set using a transport protocol setting command. In this case, write data is continuously input without inputting a dummy address, so that write data is inserted between busy signals to perform writing to 64K sectors.

[VFA Access Mode for Reading]

The read timing in the VFA access mode is described next. The VFA area has a default data length of 512 bytes (or 528 bytes). This can be changed to 2 KB (= 2112 B: multiple = 4) or 4 KB (= 4224 B: multiple = 8) using the transport protocol change command. In this case, it is possible to determine the additional suitability of the extended 16 bytes, and the suitability of the adoption of the ECC function to identify the data transmission system upon the addition of 16 bytes.

The capacity of the VFA area can be resized using the VFA resize command.

FIG. 70 is a timing diagram when a start address LBA = 00h is input to execute reading of a basic read type for 256 sectors of the VFA.

71 relates to the case where the end command <FBh> is input in the ready state to forcibly terminate the read operation.

Fig. 72 relates to the case where a retry command <31h> is input in the ready state to output the immediately preceding read data once again.

73-79 illustrate an optional reading format in the VFA access mode. Among these, FIGS. 73-76 relate to the case where the transfer protocol setting command is applied to set the read type B, that is, the case where the continue command <F8h> is used to continue the read operation.

In Fig. 73, the continue command <F8h> is input after each sector data read to continue the read operation. If the continue command clock is input beyond the number of output requests (sector counts), a fixed value <FFh> is output. LBA-NAND memory outputs this fixed value, and the host sends an end command to end the command.

74 is a timing diagram in which the continue command <F8h> is likewise used to continue a read operation and the end command <FBh> is used to end a continued read operation.

FIG. 75 is a timing diagram when the continue command <F8h> is likewise used to continue a read operation and a retry command <31h> is input to retransmit the same sector data as in the immediately preceding read.

Fig. 76 is a timing diagram when the continue command <F8h> is likewise used to continue the read operation and the same continue command <F8h> is used to execute the interruption so as to omit the data read operation. In this example, one sector contains 528 bytes of data D0-D527. During the second sector read, the continue command <F8h> is input when data D0-D256 is read, thereby omitting the data read operation.

77-79 relate to the case where the transfer protocol setting command is applied to set the read type C, that is, the read operation continues without the use of the continue command <F8h>.

Fig. 77 relates to the case where sector data reading is repeatedly repeated, and a busy state signal is inserted therebetween.

FIG. 78 is a timing diagram when an end command <FBh> is applied to end a continued read operation of similar read type C. FIG.

79 is a timing diagram when a similar read type C is applied to continue a read operation and a retry command <31h> is input to retransmit the same sector data as in the immediately preceding read.

[VFA access mode for writing]

80 relates to the case where the start address LBA = 00h is input to execute writing to 256 sectors, and shows command, address, and one sector write data input. 81 shows write data input of up to 256 sectors upon receipt of a write confirmation pass (“P”).

82 relates to a case where the end instruction <FBh> is input in the state of a write ready state during the write sequence starting from the start address LBA = 30h, whereby the write sequence is terminated.

83 is a timing diagram of a process recommended when the status of a write command indicates a write error ("E"). If the write error is uncorrectable, the same address is input again as shown to effect retransmission.

84 is a timing diagram of an optional write format in which write data for each sector is input without input of a dummy address.

[Command Diagram Overview]

85-87 show an instruction diagram overview of the read / write access.

85 relates to the case where the PNR mode is set at power up. After the PNR mode is set, the command "CMD" and the address "ADD" are input, and after a certain busy time has elapsed, the state "ST" is checked.

Two handling methods are provided for status errors. One is to return to the initial PNR mode setting using the command <FFh> which retries the setting without shutting down the power (address reset). Another method is to turn off the power and restart the power supply.

The read data is subjected to a transmission test. When a transmission error is detected, the same data is transmitted once again.

86 relates to read access in PNA, VFA, MDA access modes. After setting the start using the initial command, the command and address are input. Then, after any busy, the state "ST" is checked.

Two handling methods are provided for status errors. One is to return to the initial setting using the command <FDh> to retry the setting (soft reset). Another way is to issue a shutdown command <FBh> and return to the initial command.

The read data is subjected to a transmission test. When a transmission error is detected, the same data is transmitted once again.

87 relates to write access in PNA, VFA, MDA access modes. After the start setting using the initial command, the command, address and write data are input. If a data transfer error is detected through checking of the state "ST", write data is input again.

The end command <FBh> may be issued during the write sequence to end the write operation and may retry it from the beginning.

[Other command sequence]

Specific timing diagrams of the other instruction sequences are described below. 88-90 illustrate command sequences for mode change.

88 shows input timing of a change command <FCh> for changing to the MDA access mode. After a certain busy period has elapsed, this mode is changed. This may include (a) a change from PNA access mode or VFA access mode to MDA access mode; And (b) termination at PNR access mode or serial EEP mode. In case of (a), it is possible to return to the original mode. However, in the case of (b), it is not possible to return to the original mode because the original mode is a read mode that can be set only when the power is applied.

89 shows a sequence of instructions for changing from MDA or VFA access mode to PNA access mode, and FIG. 90 shows changing from MDA or PNA access mode to VFA access mode.

91 and 92 illustrate commands registered as NOP commands among the commands used above. In FIG. 91, <60h>-<D0h> are past erase commands and are registered at appropriate addresses. In FIG. 91, <FFh> is a past reset command and is validated as an address reset command in the PNR mode (see FIG. 85).

93 shows a sequence of firmware (FW) reload command <CMD> required for the memory controller. When the controller receives this command, it ends the current command and executes a backup write of data from the buffer RAM to the flash memory chip (step 1). It then reads the FW from the flash memory chip and sends it for reload (step 2). After executing this command, it will boot the system and return to the Ready state.

FIG. 94 shows a timing diagram of an instruction < FEh > used to force the LBA-NAND memory to return to the ready state when it remains in the busy state.

FIG. 95 shows an ID data read command sequence, which prepares instructions for reading pseudo ID code data and reading ID code from the original LBA-NAND memory as described above (see FIG. 11B).

96 shows a state read command sequence. The LBA-NAND memory has two kinds of states, namely, a general state output using the command <70h>; And the LBA-NAND specific state output using the command <71h> as shown in FIG. 11C.

97 is a timing diagram of a password setting command. The default password is "FFhFFh" and the password authentication function is disabled during this period. After this command is used to set a user specific password, the password authentication function is enabled. When executing this command, it is desirable that a state check be performed. Fig. 97 shows the case where pass "P" is obtained using the status command <71h>.

98 is a timing diagram of a VFA unit setting command. As described above, the VFA region is expandable. It is possible to change the capacity of the VFA area using this command. If the capacity of the VFA area gains, the MDA area loses twice the capacity of that increase. When executing this command, it is also desirable that a status check be performed. FIG. 98 shows the case where pass "P" is obtained using the status command <71h>.

99 is a timing diagram of a reset command after FW update in the controller. When this command is entered, the FW is refreshed in the buffer RAM (step 1) and it is written in the memory chip (step 2). This data flush to the memory chip can be controlled using a hardware sequencer 27.

100 is a timing diagram of an address removal command <FFh>. This command is valid only in PNR mode.

101 is a timing diagram of an FW reload command <FDh>. Using this command, the FW can be read back from the flush memory and loaded into the buffer SRAM at the controller. This data reading and sending can be controlled using hardware sequencer 27.

102 shows a sequence of instructions <FBh> for use at the end of the read / write currently being processed. This command responds as follows:

During the data read in the Ready period, the data buffer is cleared after completion of the data output. If write data is being input, after writing the received write data to the flush memory, the data buffer is cleared to end this command. If no data is being read, the data buffer is cleared to end this command. If write data is not being input, after writing to the flush memory of write data already received, the data buffer is cleared to end this command.

During the busy period, no commands are allowed.

103 is a command sequence of data transfer from the host to the LBA-NAND memory for FW update. The data structure of 528 bytes includes 512 bytes of data body + 2 bytes of dummy data + 2 bytes of CRC16 + 11 bytes of dummy data + 1 byte of address. The last 528th byte corresponds to the address.

Data is always multiplied = 4 and is sent on a 528-byte basis. The figure shows a data transmission unit of 2K bytes in which an address of 5 bytes and 2K bytes of data are transmitted together. In the example shown, when a transmission error "failure" is detected via status check, the same data is sent again.

At the five byte address, the first, second, fourth and fifth bytes are dummy and the third byte is a code page.

104 shows a sequence of controller FW updates. The host device (music engine) sequentially transmits commands and FW data to the LBA-NAND memory. When the host interface in LBA-NAND memory receives them, the memory controller downloads the FW from the buffer SRAM.

When the host enters the reset command <FAh> and the LBA-NAND memory becomes busy, the FW is refreshed from the buffer SRAM and sequentially written to the flash memory.

105 shows an outline of error processing for the FW update command. After the start setting, the first command and address and data are transferred to the LBA-NAND memory. The data transfer is checked from state "ST", and when the host detects an error, the data is retransmitted.

After the input of the second command, the same operation is repeated after an arbitrary busy period has been placed. When an error is found in the last FW update status check, this command is soft reset to abandon the FW update. When no error is found, a write command FAh for writing the FW in the NAND flash memory is issued to update the FW.

106 is a timing diagram of a data refresh command. This command is used to identify the consistency of the data written in the flash memory. If one block is found to contain an error in the read read data, it is replaced with a spare block and the original block is reused as a spare block.

This command serves as a background command and the Ready / Busy pin outputs the Ready state. Adoption of this command requires new settings of the data refresh status command and the data refresh end command.

107 shows an instruction used to erase all data in the MDA area from flash memory for security.

108 shows a flash cache command to terminate all processes running in LBA-NAND memory, which is the recommended input before powering down. That is, after execution of this command <F9h> and any busy period, the ready state is set to indicate the end of all processes. Powering off in this state can avoid system problems caused by powering down in this state when the processes are not completely shut down.

109 is a timing diagram of a transport protocol setting command. The basic data transmission format is ECC corrected in the form of 1 sector = 528 bytes. The data input following the configuration command makes it possible to set the data transfer protocol as shown in Fig. 11D.

110 is a timing diagram of a minimum busy time setting command. The one byte data input following the configuration command makes it possible to determine the minimum busy time as shown in Fig. 11F.

111 is a timing diagram of a power saving mode setting command. This command brings the read / write access to an operating mode with lower power consumption than normal operation.

112 relates to the case where the power saving mode is specifically applied to the read operation. The setting of the power saving mode makes it possible to set the busy period and the like longer than usual.

113 illustrates another power saving mode setting method. Between the power save mode command and the busy period after input of the next address and the timing of the command latch enable CLE, an offset time is set to reduce power consumption.

114 is a timing diagram of a power saving mode end command. This command makes it possible to reset the power saving mode to the normal mode.

115 is a timing diagram of an address acquisition command. This command makes it possible to notify the host of the base in the address latch period of the LBA-NAND memory.

116 is a timing diagram of a maximum capacity acquisition command. This command makes it possible to use 5 byte data to indicate the total number of sectors in the sum of the VFA area and the MDA area supported by the LBA-NAND memory. One sector contains 512 bytes.

117 is a timing diagram of a pin information acquisition command. This command allows the host to identify the level at the common pins (COME, COM0, COM1) detected in the LBA-NAND memory.

118 is a timing diagram of a read data retransmission request command. When the host detects a transfer failure and enters this command <31h>, the LBA-NAND memory retransmits the same read data.

Additional Examples

119, 120, and 121 show timing charts of three types of sector reads applied to MDA and VFA, that is, timing charts of types A, B, and C, respectively, with status information "Status_1". Each of these is an example of specifying a start address by a 2-byte sector count SC and a 3-byte sector address AD.

The transmission data length is selected from six options, but is 512 bytes N or (512 + 16 bytes) N (N = 1, 4, 8). In this example, N is set to four. The +16 bytes in the data length are transmission data check bits by CRC, ECC, or the like.

Type A shown in Fig. 119 is that input of dummy sector addresses < 00h >-< xx >-< 30h > (xx is a 5-byte dummy address) is performed after reading data from sectors N to N + 3, and the next sector. This is an example where reading continues.

Type B shown in FIG. 120 is an example in which the next sector read is continued by the input of the continue command <F8h> after reading from sector N to N + 3.

Type C shown in FIG. 121 is an example in which the next sector read continues without input of a continue command after reading from sector N to N + 3.

Each of FIGS. 119-121 shows busy state (I) from 1/01 to I / 08, apart from internal Ready / Busy, until the first data is read and the last data packet of sector read arrives. / 06 = "0") shows an example in which "Status_1" is displayed continuously.

The read "Status_1" serves as the next command sequence <70h>-[Status_1 value].

122 and 123 show timing charts of two type sector writes applied to MDA and VFA, that is, timing charts of type A and B, respectively, with status information "Status_1". Each of these is an example of specifying the start address by a sector count SC of 2 bytes and a sector address AD of 3 bytes.

Type A shown in FIG. 122 is an example in which input of dummy sector addresses < 80h >-< xx > is performed after data writing from sectors N to N + 3, and subsequent sector writing continues.

Type B shown in FIG. 123 is an example in which the next sector read is continued without inputting a dummy sector address after writing from sector N to N + 3.

Note that the read mode of the status information "Status_1" includes the case in the PNR mode (FIG. 124), the case in the VFA / MDA mode (FIG. 125), and the case in the boot code maintenance mode (FIG. 126).

In each case, when data reading or writing is performed continuously after reading [Status_1 value] according to the command sequence, it is necessary to return to the data reading mode or the data writing mode by the input. The states &quot; Status_1 &quot; shown in Figs. 119-123 are shown in Fig. 125, where the busy state is continuously displayed until the last data packet of sector read or sector write using I / 06.

The host may determine whether the LBA-NAND memory system operates in a series of sector read / write operations, or whether the LBA-NAND memory system has already completed the series of operations and is ready to perform a new operation. Can be determined using 06.

For example, suppose a new task with a high priority level is created while an application performing a sector read is running on a multi-task operating host, and new access to the LBA-NAND memory system is sought. In this case, if I / 06 of "Status_1" is busy, the termination command <FBh> shown in FIG. 50 may be issued. Thereafter, after the series of operations in process are completed, access to the LBA-NAND memory system corresponding to the new task may begin.

LBA-NAND System-Summary

FIG. 127 shows an overview of the operation modes of the LBA-NAND memory including an operation mode change as described in FIGS. 8 and 9. After initial setup at power-up, an arbitrary command is entered to set the PNR mode or serial EEP mode to read PNA data, whereby boot code load and system boot are executed.

The PNR mode or serial EEP mode can be changed to MDA access mode using the change command <FCh>. This change command can be used to change the LBA-NAND access mode between accesses to three areas, namely between MDA access mode, PNA access mode, and VFA access mode. These access modes terminate after completion of the flash cache, which finally writes all data from the buffer RAM to the flash memory.

Claims (16)

A nonvolatile memory system connectable to a host device, A nonvolatile memory having a plurality of data areas; And A memory controller operative to control read and write operations to the nonvolatile memory; The memory controller continuously executes read / write operations on a plurality of sectors in a selected data area of the nonvolatile memory in accordance with a command provided from a host device and a sector count and a sector address, The memory controller determines that data received from the host device when the address latch enable signal is activated indicates the sector count and the sector address, The plurality of data areas includes a booting data recording area for a host system, The nonvolatile memory is configured to store multivalue bits of data for each nonvolatile memory cell, and the memory controller performs write control in the boot data write area so that one-bit data storage is performed for each nonvolatile memory. A nonvolatile memory system. The method of claim 1, A first application program area capable of increasing / decreasing capacity according to an input of a capacity change command as the plurality of data areas, and a capacity of which is reduced or increased in response to an increase or decrease in capacity of the first application program area; 2 is provided with an application program area and the boot data recording area. 3. The method of claim 2, And the first application program area is a program area for a vendor application, and the second application program area is a program area for an end user application. 3. The method of claim 2, The nonvolatile memory includes a plurality of NAND cell units having a plurality of electrically rewritable nonvolatile memory cells connected in series, bit lines connected to one end of the NAND cell unit through a selection gate transistor, and having a common source. And a memory cell array wherein a line is connected to the other end of the NAND cell unit through a select transistor. 5. The method of claim 4, And the memory controller performs write control in the boot data write area so that writing to a cell adjacent to the selection gate transistor is not performed. 5. The method of claim 4, And the memory controller performs write control in the boot data write area such that writing is performed only for one of odd pages and even pages of the memory cell array. delete The method of claim 1, The memory controller, A first interface for performing data transfer with the nonvolatile memory; A second interface for performing data transfer with the host device; A data register to temporarily hold data transmitted by the first and second interfaces; And And a processing unit for controlling data transfer via the first and second interfaces. 3. The method of claim 2, And the first and second application program areas have read / write data transfer units that can be set changeably by selection of sector multiples. The method of claim 1, A first application program area capable of increasing / decreasing capacity according to an input of a capacity change command as the plurality of data areas, and a capacity of which is reduced or increased in response to an increase or decrease in capacity of the first application program area; 2 An application program area, the boot data write area, and a system data write area for the memory controller are provided. The method of claim 10, When power is applied, data is automatically read-in from the boot data recording area and the system data recording area into the memory controller, and thereafter, a read command for setting a read mode in which the boot data is read-in to the host device is issued. Input, non-volatile memory system. The method of claim 10, And the first and second application program areas have read / write data transfer units that can be set changeably by selection of sector multiples. A data reading / writing method of a nonvolatile memory system comprising a nonvolatile memory having a plurality of data regions and a memory controller operative to control read and write operations to the nonvolatile memory, the system being connectable to a host device. and, The method, Providing a command, sector count, and sector address from a host device; And Continuously executing read / write to a plurality of sectors in a selected data area of the nonvolatile memory according to a command, a sector count and a sector address provided from the host device under the control of the memory controller. Including, The memory controller determines that data received from the host device when the address latch enable signal is activated indicates the sector count and the sector address, The plurality of data areas includes a boot data recording area for a host system, The nonvolatile memory is configured to store multivalue bits of data for each nonvolatile memory cell, and the memory controller performs write control in the boot data write area so that one-bit data storage is performed for each nonvolatile memory. Performing a data read / write method of a non-volatile memory system. The method of claim 13, A first application program area capable of increasing / decreasing capacity according to an input of a capacity change command as the plurality of data areas, and a capacity of which is reduced or increased in response to an increase or decrease in capacity of the first application program area; 2 An application program area and a boot data write area are provided. The method of claim 14, And said first and second application program areas have read / write data transfer units that can be set changeably by selection of sector multiples. The method of claim 13, A first application program area capable of increasing / decreasing capacity according to an input of a capacity change command as the plurality of data areas, and a capacity of which is reduced or increased in response to an increase or decrease in capacity of the first application program area; 2 An application program area, the boot data write area, and a system data write area for the memory controller are provided.

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