CN112632882A - Device and method for verifying arbiter based on formal verification - Google Patents
Device and method for verifying arbiter based on formal verification Download PDFInfo
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Abstract
The embodiment of the application provides a device and a method for verifying an arbiter based on formal verification, wherein the device comprises: the excitation constraint module is configured to constrain the excitation signal input into the arbiter to be verified to obtain a legal excitation signal; an auxiliary code module configured to derive a reference response signal based on the legitimate excitation signal; and the assertion checking module is configured to compare the reference response signal with an actual response signal to complete logic verification of the arbiter to be verified, wherein the actual response signal is obtained by inputting the legal excitation signal into the arbiter to be verified. Some embodiments of the application build the verification arbiter model faster based on formal verification, and the verification efficiency is higher.
Description
Technical Field
The present application relates to the field of chip verification, and in particular, to an apparatus and method for verifying an arbiter based on formal verification.
Background
With the rapid development of integrated circuit technology, the design scheme of the chip becomes more and more complex, and the corresponding requirement on the verification scheme of the chip is higher and higher. It is more complete and fast to verify a single sub-module in a chip. For example, for the authentication of arbiter arbiters, the related art scheme generally adopts the systemverilog language and builds an authentication environment based on the uvm framework. Taking the example of independently building the arbiter UVM verification environment, it is necessary to compile a plurality of UVM _ components (including driver/monitor/checker, etc.) and implement connections between them, then compile a random test sequence to provide an incentive, and finally start the sequence in testcase for simulation verification, and it takes a lot of effort to build the independent environment. However, if the arbiter arbiters are placed in the existing subsystem verification environment or SOC environment, the internal functions of the arbiters cannot be precisely controlled in the upper environment, and thus the arbiters cannot be quickly and completely verified.
Therefore, how to efficiently verify the arbiter becomes a technical problem to be solved urgently.
Disclosure of Invention
Some embodiments of the present application can complete the building of a test model based on formal verification vc format, greatly reduce the time required for building a verification environment, and when simulation (or verification) has a problem, only related functional components need to be changed to perform iteration quickly, thereby improving the simulation efficiency.
In a first aspect, some embodiments of the present application provide an apparatus for validating an arbiter based on formal validation, the apparatus comprising: the excitation constraint module is configured to constrain the excitation signal input into the arbiter to be verified to obtain a legal excitation signal; an auxiliary code module configured to derive a reference response signal based on the legitimate excitation signal; and the assertion checking module is configured to compare the reference response signal with an actual response signal to complete logic verification of the arbiter to be verified, wherein the actual response signal is obtained by inputting the legal excitation signal into the arbiter to be verified.
Some embodiments of the application build the verification arbiter model faster based on formal verification, and the verification efficiency is higher.
In some embodiments, the to-be-verified arbiter comprises: a polling arbiter, a zero priority arbiter, and a Qos arbiter.
Some embodiments of the application can verify various arbiters implemented by different logics, and have better universality.
In some embodiments, the auxiliary code module is obtained by writing processing code according to the definition of the arbiter to be verified.
The auxiliary code module of some embodiments of the present application may output complex logic as simple signals for rapid checking of the assertion checking module.
In some embodiments, the auxiliary code module is configured to: receiving an input legal excitation signal, wherein the legal excitation signal comprises a plurality of paths of legal signals; obtaining an expected output signal corresponding to each path of legal signals in the multiple paths of legal signals according to the processing code to obtain the reference response signal, wherein the reference response signal comprises multiple paths of expected output signals; inputting the reference response signal to the assertion checking module.
Some embodiments of the present application obtain correct output logic for each legal stimulus through pre-written processing code, so as to facilitate the assertion checking module to check whether the logic output by the arbiter to be verified is accurate.
In some embodiments, the assertion detection module is output logic that checks the to-be-verified arbiter by writing an assertion.
Some embodiments of the present application verify, through a pre-edited assertion, whether the output logic of the arbiter to be verified is the same as the reference logic of the auxiliary code module, thereby verifying whether the arbiter output logic meets the requirements.
In some embodiments, the assertion detection module is configured to: receiving the actual response signal, wherein the legal excitation signal comprises a plurality of legal signals, and the actual response signal comprises a plurality of output logic signals which are output by the arbiter to be verified and correspond to the legal signals; receiving a plurality of said desired output signals; comparing each path of signal in the multi-path expected output signal with the output logic signal of the corresponding path; and confirming that the multi-path expected output signal is the same as the multi-path output logic signal, and then the verification is passed.
Some embodiments of the application may improve simulation efficiency by comparing whether output logic of the arbiter to be verified is accurate through pre-programmed assertions.
In some embodiments, the apparatus further comprises: a coverage collection module configured to collect whether the logic of the set timing is covered.
Some embodiments of the present application.
In a second aspect, some embodiments of the present application provide a method of validating an arbiter based on formal validation, the method comprising: constraining an excitation signal input into an arbiter to be verified to obtain a legal excitation signal; inputting the legal excitation signal into an arbiter to be verified to obtain an actual response signal corresponding to the legal excitation signal; inputting the legal excitation signal into an auxiliary code module to obtain a reference response signal corresponding to the legal excitation signal; and comparing the actual response signal with the reference response signal to finish the verification of the arbiter to be verified.
In some embodiments, before the constraint inputs the excitation signal of the arbiter to be verified and the legal excitation signal is obtained, the method further comprises: writing an excitation constraint to convert the excitation signal to the legitimate excitation signal.
In some embodiments, before the comparing the actual response signal and the reference response signal to complete the validation of the arbiter to be validated, the method further comprises: an assertion is written to check the output logic of the arbiter to be verified.
In some embodiments, the method further comprises: modifying the incentive constraints or modifying the arbiter to be verified when the verification is not confirmed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
FIG. 1 is a block diagram illustrating an apparatus for validating an arbiter based on formal validation according to an embodiment of the present disclosure;
FIG. 2 is a block diagram illustrating an apparatus for validating a polling arbiter based on formal validation according to an embodiment of the present application;
FIG. 3 is a block diagram illustrating an apparatus for validating a zero-priority arbiter based on formal validation according to an embodiment of the present application;
fig. 4 is a block diagram illustrating an apparatus for validating a Qos arbiter based on formal validation according to an embodiment of the present application;
FIG. 5 is a flowchart of a method for validating an arbiter based on formal validation according to an embodiment of the present application;
fig. 6 is a flowchart for building a verification model and verifying an arbiter to be verified by using the built model according to the embodiment of the present application;
FIG. 7 is a flow diagram of a verification process performed by the assertion checking module.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
The following lists some embodiments of the application that relate to the content and meaning of the relevant english word or phrase.
formall, formal verification.
vc formal A simulation tool for formal verification.
arbiters are arbiters.
Design under test, design source code, embodiments of the present application refer to the source code of the arbiter.
assumptions, some embodiments of the present application refer to the functionality of stimulus constraint modules, assuming that constraints are placed on the input stimuli of the source code module DUT.
helper code, in the embodiments referred to herein as the module for generating the reference output signal.
assertion, a timing check syntax.
checker is a logic check code.
Overlay Performance, the overlay property, collects whether a particular sequential logic is overlaid.
uvm Universal Verification Methodology
uv component-Components that make up uvm Environment.
driver for driving the DUT input signal.
monitor for monitoring DUT output signals.
sequence, used to define the drive.
testcase test case.
SOC is a system on chip.
Round robin is the Round robin scheduling.
Quality of service, the arbiter incentivizes that the bandwidth can be configured.
Zero priority, the zeroth incentive has the highest priority.
Testbench is the verification environment.
Fifo is first in first out.
The formal verification technique of the embodiment of the present application does not require a test vector, but requires two designs for comparison (i.e., comparing the outputs of the reference object and the object to be verified, specifically referring to the output result of the reference arbiter implemented by the auxiliary code module of some embodiments of the present application and the actual response result output by the arbiter to be verified), and one of the two objects specifically compared by some embodiments of the present application serves as the reference design (i.e., the reference response signal output by the auxiliary code module of embodiments of the present application), and the other serves as the design to be verified (i.e., the logic output signal of the arbiter to be verified). In the process of equivalence verification, the reference design is considered to be a verified design which can be used as a reference standard, and any part of the design to be verified, which is inconsistent with the reference design, is considered to be a logic function error of the arbiter to be verified, or the input excitation signal is an illegal value.
Some embodiments of the present application provide a method for performing fast simulation verification for various types of arbiter arbiters based on formal verification format. That is to say, some embodiments of the present application are implemented based on formal verification vc format, and can quickly establish a verification environment for an arbiter to be verified and improve verification efficiency. The authentication apparatus of some embodiments of the present application includes: the stimulus constraint module classes is used for constraining stimulus signals of a DUT (source code of a design in an arbiter to be verified) to make all input stimuli legal stimuli; the auxiliary code module helper code is auxiliary logic and is used for simulating the reference logic output by the verified arbiter to the legal excitation signal and inputting the reference logic into the assertion checking module for checking; the assertion checking module assertion checker is used for checking whether the output logic of the DUT (namely the source code designed in the arbiter to be verified) is correct (namely whether the reference logic input is verified to be consistent with the actual output logic of the arbiter to be verified); the coverage collection module cover property is used for collecting a specific signal logic sequence and viewing the waveform of the sequence. Through above-mentioned functional component (being above-mentioned each module), establish the verification model based on formal verification vc formal, very big reduction build the required time of verification environment to when emulation or verification go wrong, only need to change above-mentioned functional component can iterate fast, thereby improve the efficiency of emulation.
Referring to fig. 1, fig. 1 is a block diagram illustrating an apparatus 10 for validating an arbiter based on formal validation according to some embodiments of the present application, where the apparatus 10 includes: a stimulus constraint module 100 configured to constrain the stimulus signal input to the arbiter to be verified to obtain a legal stimulus signal (i.e. to obtain req [0], req [1], … …, req [ n ] of fig. 1, where n is the number of paths of the legal stimulus signal and n is a natural number greater than 1); an auxiliary code module 400 configured to derive a reference response signal (i.e. the signal that the auxiliary code module 400 of fig. 1 outputs to the assertion checking module 300) based on the legitimate excitation signal (i.e. req [0], req [1], … …, req [ n ] of fig. 1); an assertion checking module 300 configured to compare the reference response signal with an actual response signal (i.e., gnt [0], gnt [1], … …, gnt [ n ] output by the arbiter 200 to be verified in fig. 1) to complete logic verification of the arbiter 200 to be verified, wherein the actual response signal (i.e., gnt [0], gnt [1], … …, gnt [ n ] output by the arbiter 200 to be verified in fig. 1) is obtained by inputting the legal excitation signal (i.e., req [0], req [1], … …, req [ n ] into the arbiter 200 to be verified.
It should be noted that the to-be-verified arbiter 200 of fig. 1 includes: a polling arbiter, a zero priority arbiter, or a QOS arbiter, etc., and the embodiments of the present application do not limit the type of arbiter to be verified. The arbiter 200 to be verified in fig. 1 is further configured to receive a clock signal clk, a reset signal reset, and an enable signal en, where the clock signal clk is used to provide a clock for the arbiter to be verified, the reset signal reset is used to reset the arbiter to be verified to an initial state, the enable signal is used to define an operation mode of the arbiter to be verified, when the signal is valid, the arbiter to be verified normally operates, otherwise, the arbiter to be verified cannot normally operate. The arbiter to be verified processes the input excitation signal to obtain a corresponding response signal according to the definition of the arbiter, taking a polling arbiter as an example, the arbiter performs polling response among the reqs, that is, each req has the same priority, and if several reqs are valid at the same time, the plurality of reqs are responded in turn.
In order to enable the auxiliary code module 400 to output the reference response signal, the processing code comprised by the auxiliary code module 400 needs to be written according to the definition of the arbiter to be verified, which means that the specific behavior of the arbiter is described, i.e. the response value should also be some certain value determined when a certain set of specific stimuli is input. The auxiliary code module 400 generates corresponding reference values based on these definitions and the input stimuli (so that the assertion checking module 300 can verify the performance of the arbiter to be verified by comparing the reference values with the actual values obtained by the same stimuli loaded on the arbiter to be verified). The respective auxiliary code module 400 is configured to: receiving an input legal excitation signal (i.e., req [0], req [1], … …, req [ n ] of FIG. 1), wherein the legal excitation signal (i.e., req [0], req [1], … …, req [ n ] of FIG. 1) comprises a multi-path legal signal (e.g., the n-path signal of FIG. 1); obtaining expected output signals corresponding to each path of legal signals in the multiple paths of legal signals according to the processing codes to obtain the reference response signals, wherein the reference response signals comprise the multiple paths of expected output signals (at most one path of the multiple paths of expected output signals at the same time is an effective response, and the other paths of the multiple paths of expected output signals are invalid response values); the reference response signal (including n desired output logic signals, not shown in fig. 1) is input to the assertion checking module 300.
In order for the assertion checking module 300 to have the function of comparing whether the output logic of the arbiter to be verified is consistent with the reference response signal containing the expected output signal (or called expected output logic), the assertion needs to be written in advance for the assertion checking module 300 so that the assertion checking module 300 can check whether the output logic of the arbiter to be verified is consistent with the expected output logic output by the auxiliary code module 400. The assertion is a syntax, and through this syntax, it can check whether the sequential logic at a certain time is correct, that is, at each rising edge of the clock, the output logic signal (or called actual response value) of the arbiter to be verified is compared with the reference logic signal (or called reference response signal) of the auxiliary code module, and if they are consistent, the comparison is passed; if the two are not consistent, an error is reported. For example, in some embodiments of the present application, assertion checking module 300 is configured to: receiving the actual response signals (i.e. gnt [0], gnt [1], … …, gnt [ n ] output by the arbiter 200 to be verified in fig. 1), wherein the legal excitation signals include multiple legal signals, and the actual response signals include multiple output logic signals corresponding to the legal signals output by the arbiter 200 to be verified; receiving a plurality of desired output signals output by the auxiliary code module 400; comparing each expected output signal in the plurality of expected output signals with the output logic signal of the corresponding path; and confirming that the multi-path expected output signal is the same as the multi-path output logic signal, and then the verification is passed.
To confirm whether the verification model covers all legitimate incentives, in some embodiments of the present application, the apparatus 10 further comprises: a coverage collection module 500, the coverage collection module 500 configured to collect whether logic of the set time sequence is covered. It should be noted that the input signals of the coverage collection module 500 are the legal excitation signals req [0], req [1], … …, req [ n ] of fig. 1. For example, the coverage collection module 500 employs a cover property grammar that uses assertions and the tool displays whether the cover property is covered.
That is to say, the embodiment of the application realizes the verification model based on formal verification vc format, and can quickly build a verification environment for an arbiter and improve verification efficiency. Meanwhile, the quick verification can be realized for similar small modules which are strongly related to time sequence, such as fifo modules. Some embodiments of the present application include an incentive constraint module 100 for constraining the incentive signals of the arbiters to be verified, the function of the incentive constraint module 100 including making all input incentives legitimate incentives. For example, a plurality of property properties are programmed in the excitation constraint module 100 (that is, after a legal excitation property required in the arbiter definition, for example, a certain req is valid, valid values are required to be maintained until a response signal corresponding to the req is valid, and after a response signal corresponding to the req is obtained, the valid values may be changed into invalid values or may be maintained continuously), and then the property properties are used to constrain excitation signals by assuming an asseme syntax so as to obtain legal excitation signals, and then the legal excitation signals are transmitted to the arbiter to be verified. The auxiliary code module 400 is auxiliary logic whose function includes reference logic for simulating the output of a validated arbiter to a legitimate stimulus signal, which is then input. For example, the auxiliary code module performs corresponding processing on the input multi-channel excitation signals according to the definition (explained in the foregoing) of the arbiter to be verified, and calculates to obtain an expected response signal value under the current excitation; the function of the assertion checking module assertion checker includes checking whether the output logic of the arbiter to be verified to the legal stimulus is correct (for example, receiving the response signal of the arbiter to be verified and the expected response signal of the auxiliary code module, and comparing the two signals), and the module includes many assertion syntax (for example, checking whether each path of response signal is consistent with the expected response signal in each clock cycle, and reporting an error if the response signal is not consistent with the expected response signal), and if the sequential logic signal is not satisfied with the expectation, reporting corresponding error information. The function of the coverage collection module cover property comprises a function for collecting a specific signal logic sequence and a function for looking up the waveform of the sequence to check whether certain specific sequential logic appears, that is, specific excitation signal sequential logic can be programmed in the module, and a vc format tool can display whether the logic appears after the simulation is finished, so that the purpose of collecting the coverage is achieved. The construction of the verification environment can be completed after the components corresponding to the functional modules are realized in the formal verification simulation tool vc format, the time for constructing the verification environment is greatly shortened, and when the simulation has problems, the components corresponding to the functional modules are required to be changed to quickly iterate, so that the simulation efficiency is improved.
The structure of an apparatus for validating an arbiter based on formal validation is exemplarily described below with a polling arbiter, a zero-priority arbiter, and a Qos arbiter as arbiters to be validated, respectively.
The to-be-verified arbiter 200 of FIG. 1 is used at least for providing arbitration logic of the to-be-verified arbiter, the to-be-verified arbiter of some embodiments of the present application comprising: round robin arbiter, Qos (quality of service) arbiter, and zero priority arbiter. The specific description parameters and descriptions of each arbiter to be authenticated are shown in table 1. The verification environments shown in fig. 1 (such as fig. 2, fig. 3, and fig. 4) are respectively built for the three arbiters to be verified, and then a formal verification tool vc format is configured correspondingly, so that the three arbiters can be simulated respectively. In simulation time, complete verification of the arbiters of the three arbiters can be completed generally at the level of minutes, and the traditional verification method can perform comprehensive verification only by the level of hours at least, so that the verification efficiency is greatly improved.
As shown in FIG. 1, the verification environment includes an incentive constraint module associations, an auxiliary code module helper code, a coverage collection module cover property, and an assertion checking module assertion checker. The excitation constraint module classes is used for constraining the input signal of the arbiter to be verified, and if the excitation constraint module is not added, the system defaults to traverse all possible excitations; since the assertion syntax is difficult to check complex logic, an auxiliary code module helper code is required to process the complex logic, and a simpler logic that the assertion checking module 300 can check is generated; the coverage rate collection module cover property is used for collecting certain specific logic sequences and checking the waveform to confirm whether the logic sequences really appear; the assertion checking module 300 checks the output logic of the to-be-verified arbiter, for example, checks whether the output result of the round robin arbiter loops among several input legal drivers req without a higher priority of a legal driver req, and generally checks the logic processed by the auxiliary code module helper code, thereby simplifying the complexity of the assertion checking module assertion checker.
TABLE 1 arbiter description parameters to be verified and meanings
Fig. 2 illustrates a specific implementation of an apparatus for validating a polling arbiter based on formal validation according to some embodiments of the present application. The excitation constraint module 100 in fig. 2 generates a legal excitation signal req and provides the legal excitation signal req to the polling arbiter to be verified, where an actual response signal gnt output by the polling arbiter to be verified is a response signal corresponding to each legal excitation signal req. Then, each path of actual response signal gnt is input to the assertion checking module, and meanwhile, the auxiliary code module helper code also calculates a reference response signal according to the legal response signal req (i.e., obtains an expected value corresponding to each path of gnt signal output by the arbiter to be verified), and inputs the reference response signal to the assertion checking module 300, and then the assertion checking module 300 performs logic check on the gnt signal and the reference value thereof (e.g., checks by using assertion syntax, i.e., checks whether the two signals are consistent at each clock), and if there is an error, an error is reported. In addition, the legal stimulus signals req are input to the coverage collection module 500, and the coverage collection module 500 may set a specific logical sequence to see if each legal stimulus sequence is covered.
Fig. 3 illustrates a specific implementation of an apparatus for validating a to-be-validated zero-priority arbiter based on formal validation according to some embodiments of the present application. The system of fig. 3 is similar to the system of fig. 2, except that the logic relationship between the legal stimulus req and the corresponding gnt of the zero-priority arbiter 220 is different from that of the polling arbiter 210, and the logic relationship between the legal stimulus req and the corresponding gnt of fig. 3 satisfies the logic of the zero-priority arbiter, so that the apparatus of fig. 3 is modified according to the definition of different arbiters compared to fig. 2, i.e. the response signals of different arbiters are different for the same stimulus signal, and the calculation manner of the response signals is changed.
Fig. 4 illustrates a specific implementation of a device for validating a to-be-validated Qos arbiter 230 based on formal validation according to some embodiments of the present application. The system of fig. 4 is similar to the system of fig. 2, except that the logical relationship between the legal incentive req and the corresponding gnt of the Qos arbiter of fig. 4 is different from that of the polling arbiter 210, and the logical relationship between the legal incentive req and the corresponding gnt of fig. 4 satisfies the logic of the Qos arbiter, so that fig. 4 only needs to be modified according to the definitions of different arbiters compared with fig. 2, that is, for the same incentive signal, the response signals of different arbiters are different, and the calculation manner of the response signals is changed. In addition, the bw _ ratio signal is used for setting the response bandwidth of req [0] and other req, the signal is input to a helper code for generating a reference value corresponding to the gnt signal, and the reference value is input to an assertion checker for checking.
A method for verifying an arbiter verification-based device using formal verification according to an embodiment of the present application is exemplarily described below with reference to fig. 5.
As shown in fig. 5, some embodiments of the present application provide a method of validating an arbiter based on formal validation, the method comprising: s101, restricting the excitation signal input into the arbiter to be verified to obtain a legal excitation signal; s102, inputting the legal excitation signal into an arbiter to be verified to obtain an actual response signal corresponding to the legal excitation signal; s103, inputting the legal excitation signal into an auxiliary code module to obtain a reference response signal corresponding to the legal excitation signal; s104, comparing the actual response signal with the reference response signal to complete the verification of the arbiter to be verified. Wherein, the legal excitation signal is a subset of the excitation signal, only comprises legal excitation, and eliminates illegal excitation. For example, if a valid response signal is not obtained after a certain excitation signal req becomes a valid value, the excitation signal req becomes an invalid value, the excitation is illegal, and the legal excitation signal does not include the excitation. It should be noted that the restricting of the excitation signal input to the arbiter to be verified specifically includes: when a legal excitation signal req of a certain path is valid, the valid value needs to be maintained until a response signal corresponding to the path is valid, and the valid value can be changed into an invalid value after the response is obtained, or the valid value can be maintained continuously. For example, constraints are implemented by asserting the corresponding respective syntax.
In some embodiments of the present application, before the constraint is input to the excitation signal of the arbiter to be verified and the legal excitation signal is obtained, the method further includes: writing an excitation constraint to control translation of the excitation signal into the legal constraint.
In some embodiments of the present application, before the comparing the actual response signal and the reference response signal to complete the verification of the arbiter to be verified, the method further comprises: an assertion is written to check the output logic of the arbiter to be verified.
In some embodiments of the present application, the method further comprises: modifying the excitation constraint, modifying the assertion.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working process of the method described above may refer to the corresponding process in the foregoing apparatus, and will not be described in too much detail herein.
The following describes an exemplary procedure for building a verification model and verifying the arbiter to be verified by using the built model in conjunction with fig. 6.
As shown in fig. 6, in order to perform the authentication method, a method provided by some embodiments of the present application includes: s201, preparing a register conversion level circuit RTL file, for example, the RTL file is verilog source code written by a designer according to the definition of an arbiter; s202, verifying the environment by adopting a Tcl script configuration form (namely configuring vc format), wherein the Tcl script is used for configuring vc format and is basically a fixed format required by a vc format tool. The specific configuration comprises the steps of configuring a clock of an arbiter to be tested, resetting, specifying a vc format working mode, specifying a source code rtl file of the arbiter and a simulation starting command of the vc format; s203, compiling excitation constraints to control all excitation legality, namely compiling characteristics of an excitation constraint module; s204, writing assertion to check the output logic of the arbiter, namely writing assertion in the assertion checking module so that the assertion checking module can check whether the logic output by the arbiter to be verified is accurate; s205, instantiating the RTL, namely, instantiating the RTL, and binding the excitation constraint module and the assertion check module to the RTL instance, namely, completing the construction of the verification environment; and S206, starting formal verification formal simulation, and debugging according to a simulation result so as to change the corresponding component of the corresponding functional module. And S208, judging whether the simulation fails, if so, reporting an error by the Vc format tool, if so, finishing the simulation by executing S209, otherwise, executing S207, and modifying excitation constraint, assertion or RTL.
As shown in fig. 7, the verification process performed by the assertion checking module includes: s301, receiving the gnt signal output by the arbiter to be verified; s302, receiving the expected signal of each gnt output by the auxiliary code module; s303, comparing the expected signal with the gnt signal; s304, judging whether the expected signal and the corresponding gnt signal have the same result, if so, executing S306 simulation to end, and if not, executing S305 to report errors.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (11)
1. An apparatus for validating an arbiter based on formal validation, the apparatus comprising:
the excitation constraint module is configured to constrain the excitation signal input into the arbiter to be verified to obtain a legal excitation signal;
an auxiliary code module configured to derive a reference response signal based on the legitimate excitation signal;
and the assertion checking module is configured to compare the reference response signal with an actual response signal to complete logic verification of the arbiter to be verified, wherein the actual response signal is obtained by inputting the legal excitation signal into the arbiter to be verified.
2. The apparatus of claim 1, wherein the to-be-verified arbiter comprises: a polling arbiter, a zero priority arbiter, and a Qos arbiter.
3. The apparatus of claim 1, wherein the auxiliary code module is to write processing code according to a definition of the arbiter to be authenticated.
4. The apparatus of claim 3, wherein the auxiliary code module is configured to:
receiving an input legal excitation signal, wherein the legal excitation signal comprises a plurality of paths of legal signals;
obtaining an expected output signal corresponding to each path of legal signals in the multiple paths of legal signals according to the processing code to obtain the reference response signal, wherein the reference response signal comprises multiple paths of expected output signals;
inputting the reference response signal to the assertion checking module.
5. The apparatus of claim 4, wherein the assertion checking module is output logic to check the arbiter to be authenticated by writing an assertion.
6. The apparatus of claim 5, wherein the assertion checking module is configured to:
receiving the actual response signal, wherein the legal excitation signal comprises a plurality of legal signals, and the actual response signal comprises a plurality of output logic signals which are output by the arbiter to be verified and correspond to the plurality of legal signals;
receiving a plurality of said desired output signals;
comparing each path of signal in the multi-path expected output signal with the output logic signal of the corresponding path;
and confirming that the multi-path expected output signal is the same as the multi-path output logic signal, and then the verification is passed.
7. The apparatus of claim 1, wherein the apparatus further comprises: a coverage collection module configured to collect whether the logic of the set timing is covered.
8. A method for validating an arbiter based on formal validation, the method comprising:
constraining an excitation signal input into an arbiter to be verified to obtain a legal excitation signal;
inputting the legal excitation signal into an arbiter to be verified to obtain an actual response signal corresponding to the legal excitation signal;
inputting the legal excitation signal into an auxiliary code module to obtain a reference response signal corresponding to the legal excitation signal;
and comparing the actual response signal with the reference response signal to finish the verification of the arbiter to be verified.
9. The method of claim 8, wherein before constraining the stimulus signal input to the arbiter to be authenticated to result in a legitimate stimulus signal, the method further comprises: writing an excitation constraint to convert the excitation signal to the legitimate excitation signal.
10. The method of claim 8, wherein before comparing the actual response signal to the reference response signal to complete the validation of the arbiter to be validated, the method further comprises: an assertion is written to check the output logic of the arbiter to be verified.
11. The method of claim 8, wherein the method further comprises: modifying an incentive constraint or modifying the arbiter to be verified when the validation fails.
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