CN117829043A - Chip design verification platform, method, terminal, medium and system - Google Patents
Chip design verification platform, method, terminal, medium and system Download PDFInfo
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Abstract
The application provides a chip design verification platform, a method, a terminal, a medium and a system, wherein a memory bus interface proxy module in the verification platform directly performs data interaction with a core in a chip design to be verified, so that a verification platform interaction module connected with the memory bus interface proxy module executes corresponding chip design verification operation based on a received chip design verification instruction sent by the core, and after the chip design verification operation is executed, the obtained corresponding verification result data is sent to the core. The data interaction mode of the kernel and the verification platform avoids unnecessary data paths, shortens response period, reduces response delay, improves instantaneity, and enhances comprehensiveness and instantaneity in the verification process, so that chip verification is more complete.
Description
Technical Field
The present disclosure relates to the field of integrated circuit design technologies, and in particular, to a chip design verification platform, a method, a terminal medium, and a system.
Background
When the chip is verified, the entire chip design is embedded in the simulator and the verification platform is written using verilog language. The verification platform is used for enabling the chip design in the simulator to normally operate and observing the chip behaviors. The chip design in the simulator runs the embedded program written in the language C, and a technician can judge whether the chip design meets the requirements according to whether the behavior of the chip design in the simulator is consistent with the expected behavior of the embedded program. In this verification method, the chip design in the simulator is considered to be a true circuit that has been produced, and the outside world can only interact with it using pins in the chip design.
In the verification method, an embedded program written in the language C runs in a kernel of a chip design, and independently executes tasks with a verification platform written in the verilog language. However, through pin interaction in the chip design, the data passes through unnecessary paths, and has the advantages of large delay, long response period, low instantaneity and excessive simulator system resources are occupied. Ultimately, the lack of comprehensiveness and cooperativity in the verification process may result in insufficient verification of the chip design, affecting the overall evaluation of the entire chip design.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a chip design verification platform, a method, a terminal, a medium and a system, for solving the problem of insufficient verification of a chip design caused by interaction between the verification platform and the chip design through pins in the chip design in the prior art.
To achieve the above and other related objects, a first aspect of the present application provides a chip design verification platform, including: the memory bus interface agent module is used for performing bus access operation on a system bus connected with a target memory in a chip design to be verified, and capturing a chip design verification instruction issued to the target memory by a core in the chip design in the process of performing the bus access operation; the chip design verification instruction is issued by the kernel based on target chip design verification requirements; and the verification platform interaction module is connected with the memory bus interface proxy module and is used for executing corresponding chip design verification operation based on the received chip design verification instruction captured and issued by the memory bus interface proxy module, and uploading the obtained corresponding verification result data to the kernel through the memory bus interface proxy module after the chip design verification operation is executed.
In some embodiments of the first aspect of the present application, the method for building the chip design verification platform includes: screening a memory in the chip design to be verified and determining the memory as a target memory; writing a memory bus interface proxy module by using verilog language, and enabling the memory bus interface proxy module to take over bus access operation executed by an internal core in the chip design and connected with a system bus of the target memory; writing a verification platform interaction module according to the target chip design verification requirement so as to obtain a preliminarily built chip design verification platform; generating a definition file, and applying the definition file to the preliminarily built verification platform to obtain a final chip design verification platform.
In some embodiments of the first aspect of the present application, the means for generating the definition file includes: configuring a system bus address segment corresponding to the target memory; defining interaction rules of the chip design and the verification platform according to the configured system bus address field; and distributing corresponding index segments for each interaction unit in the verification platform interaction module based on the interaction rule so as to generate a definition file.
In some embodiments of the first aspect of the present application, the memory bus interface agent module includes: the read-write operation execution unit and the communication processor; the read-write operation execution unit is used for performing bus access operation on a system bus connected with a target memory in the chip design and capturing a chip design verification instruction issued to the target memory by the core in the process of performing the bus access operation; the system is also used for writing a captured chip design verification instruction into the communication processor and reading verification result data uploaded by the verification platform interaction module from the communication processor; the communication processor is connected with the read-write operation execution unit and is used for notifying the verification platform interaction module to obtain specific information of the chip design verification instruction from the communication processor after receiving the chip design verification instruction written by the read-write operation execution unit so that the verification platform interaction module can execute corresponding chip design verification operation based on the specific information of the chip design verification instruction; and the verification platform interaction module is also used for storing the verification result data after uploading the verification result data so that the read-write operation execution unit reads out the verification result data and sends the verification result data to the kernel.
In some embodiments of the first aspect of the present application, the read/write operation execution unit includes: the bus interface subunit is used for performing bus access operation on a system bus connected with a target memory in the chip design and capturing a chip design verification instruction issued to the target memory by the core in the process of performing the bus access operation; a bus behavior analysis subunit, connected to the bus interface subunit, for determining and applying a corresponding bus communication protocol based on the type of the system bus accessed by the bus interface subunit; and the memory behavior abstraction subunit is connected with the bus behavior analysis subunit and is used for writing the chip design verification instruction captured by the bus interface subunit into the communication processor and reading verification result data uploaded by the verification platform interaction module from the communication processor.
In some embodiments of the first aspect of the present application, the communication processor includes: an event processor subunit and a virtual memory subunit connected to the event processor subunit; the virtual memory subunit is respectively connected with the memory behavior abstraction subunit and the verification platform interaction module and is used for storing specific information of a chip design verification instruction written in by the memory behavior abstraction subunit and verification result data uploaded by the verification platform interaction module; the event processor subunit is respectively connected with the memory behavior abstraction subunit and the verification platform interaction module, and is used for notifying the verification platform interaction module to read out specific information of the chip design verification instruction from the virtual memory subunit after receiving the transmitted chip design verification instruction written in by the memory behavior abstraction subunit, so that the verification platform interaction module can execute corresponding chip design verification operation based on the specific information of the chip design verification instruction.
To achieve the above and other related objects, a second aspect of the present application provides a chip design verification method applied to a chip design verification platform, the chip design verification platform comprising: a memory bus interface proxy module, the method comprising: performing bus access operation on a system bus connected with a target memory in a chip design to be verified, and capturing a chip design verification instruction issued to the target memory by a core in the chip design in the process of performing the bus access operation; the chip design verification instruction is issued by the kernel based on target chip design verification requirements; based on the received chip design verification instruction captured and issued by the memory bus interface proxy module, executing corresponding chip design verification operation, and uploading the obtained corresponding verification result data to the kernel through the memory bus interface proxy module after the chip design verification operation is executed.
To achieve the above and other related objects, a third aspect of the present application provides an electronic terminal, including: a processor and a memory; the memory is used for storing a computer program, and the processor is used for executing the computer program stored in the memory so as to enable the terminal to execute the chip design verification method.
To achieve the above and other related objects, a fourth aspect of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the chip design verification method.
To achieve the above and other related objects, a fifth aspect of the present application provides a chip design verification system, comprising: the chip design verification platform and the chip design to be verified by the chip design verification platform are described above.
As described above, the chip design verification platform, the chip design verification method, the chip design verification terminal, the chip design verification medium and the chip design verification system have the following beneficial effects:
the memory bus interface agent module in the verification platform directly performs data interaction with the kernel in the chip design to be verified, so that the verification platform interaction module connected with the memory bus interface agent module executes corresponding chip design verification operation based on the received chip design verification instruction sent by the kernel, and sends the obtained corresponding verification result data to the kernel after the chip design verification operation is executed. The data interaction mode of the kernel and the verification platform avoids unnecessary data paths, shortens response period, reduces response delay, improves instantaneity, and enhances comprehensiveness and instantaneity in the verification process, so that chip verification is more complete.
Drawings
Fig. 1 is a schematic diagram of a chip design verification platform according to an embodiment of the disclosure.
Fig. 2 is a schematic flow chart of a method for setting up a verification platform according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a specific structure of a chip design according to an embodiment of the present application.
FIG. 4 is a flow chart illustrating a method for generating a definition file according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a memory bus interface agent module according to an embodiment of the disclosure.
FIG. 6 is a schematic diagram of a read/write operation execution unit according to an embodiment of the present application.
Fig. 7 is a schematic diagram of a communication processor according to an embodiment of the present application.
Fig. 8 is a flowchart illustrating a chip design verification method according to an embodiment of the present application.
Fig. 9 is a schematic structural diagram of a terminal according to an embodiment of the present application.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It is noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "upper," and the like, may be used herein to facilitate a description of one element or feature as illustrated in the figures as being related to another element or feature.
In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," "held," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. It will be further understood that the terms "or" and/or "as used herein are to be interpreted as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.
The application provides a chip design verification platform, a method, a terminal, a medium and a system, wherein a memory bus interface proxy module in the verification platform directly performs data interaction with a core in a chip design to be verified, so that a verification platform interaction module connected with the memory bus interface proxy module executes corresponding chip design verification operation based on a received chip design verification instruction sent by the core, and after the chip design verification operation is executed, the obtained corresponding verification result data is sent to the core. The data interaction mode of the kernel and the verification platform avoids unnecessary data paths, shortens response period, reduces response delay, improves instantaneity, and enhances comprehensiveness and instantaneity in the verification process, so that chip verification is more complete.
In order to make the objects, technical solutions and advantages of the present invention more apparent, further detailed description of the technical solutions in the embodiments of the present invention will be given by the following examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Fig. 1 is a schematic structural diagram of a chip design verification platform according to an embodiment of the invention.
The verification platform 2 includes:
the memory bus interface agent module 21 is configured to perform a bus access operation on a system bus connected to a target memory 12 in a chip design 1 to be verified, and capture a chip design verification instruction issued to the target memory 12 by a core 11 in the chip design 1 during the bus access operation; the chip design verification instruction is issued by the kernel based on target chip design verification requirements;
the verification platform interaction module 22 is connected to the memory bus interface proxy module 21, and is configured to execute a corresponding chip design verification operation based on a received chip design verification instruction captured and issued by the memory bus interface proxy module 21, and send obtained corresponding verification result data to the kernel 11 through the memory bus interface proxy module 21 after the execution of the chip design verification operation is completed.
It should be noted that, it should be understood that the division of the modules of the above apparatus is merely a division of a logic function, and may be fully or partially integrated into a physical entity or may be physically separated. And these modules may all be implemented in software in the form of calls by the processing element; or can be realized in hardware; the method can also be realized in a form of calling software by a processing element, and the method can be realized in a form of hardware by a part of modules. For example, the memory bus interface agent 21 may be a processing element that is set up alone, may be implemented as integrated in a chip of the above-described apparatus, or may be stored in the memory of the above-described apparatus in the form of program codes, and the functions of the above-described memory bus interface agent 21 may be called and executed by a processing element of the above-described apparatus. The implementation of the other modules is similar. In addition, all or part of the modules can be integrated together or can be independently implemented. The processing element described herein may be an integrated circuit having signal processing capabilities. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in a software form.
For example, the modules above may be one or more integrated circuits configured to implement the methods above, such as: one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), or one or more microprocessors (digital signal processor, abbreviated as DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGA), or the like. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
In one embodiment, chip design verification operations include, but are not limited to: functional verification operation is performed on each functional module in the chip design 1, verification operation is performed on the time sequence relation of the chip design 1, and performance verification operation is performed on the chip design 1.
The specific functions of the verification platform interaction module 22 will be explained in detail below:
the invention adopts a mode of embedding the chip design 1 into the simulator and enabling the chip design in the simulator to run an embedded program written by using a C language to verify the chip design 1. The embedded program is written according to the design verification requirement of the target chip. The chip design verification target requirement includes items that need to be verified for the chip design 1, for example, functional verification for each functional module. After verification of the chip design 1 is started, the chip design 1 in the simulator starts to run the embedded program, and issues a plurality of chip design verification instructions corresponding to the target chip design verification requirements to the target memory 12 during the running process.
Since the memory bus interface agent 21 performs a bus access operation on the system bus connected to the target memory 12 in the chip design 1, the data originally transmitted from the core 11 to the target memory 12 through the system bus connected to the target memory 12 is acquired by the memory bus interface agent 21. Under such a data transmission path, the core 11 will send the chip design verification instruction generated by the core to the verification platform interaction module 22 through the memory bus interface agent module 21.
When the verification platform interaction module 22 receives a chip design verification instruction sent by the core 11 through the memory bus interface proxy module 21, a corresponding chip design verification operation is performed by driving a corresponding module in the chip design 1 through the verification platform interaction module 22 based on specific information of the chip design verification instruction. For example, the specific content of the chip design verification instruction is to test the function of pin a in chip design 1, and the verification platform interaction module drives pin a to work. After the chip design verification operation corresponding to the chip design verification instruction is executed, the verification platform interaction module 22 generates corresponding verification result data, and sends the verification result data to the kernel 11 through the memory bus interface proxy module 21, so that a technician can judge whether the subsequent verification result data meets the expected test requirement.
In one embodiment, the method for building the chip design verification platform includes: screening a memory in the chip design to be verified and determining the memory as a target memory; writing a memory bus interface proxy module by using verilog language, and enabling the memory bus interface proxy module to take over bus access operation executed by an internal core in the chip design and connected with a system bus of the target memory; writing a verification platform interaction module according to the target chip design verification requirement so as to obtain a preliminarily built chip design verification platform; generating a definition file, and applying the definition file to the preliminarily built verification platform to obtain a final chip design verification platform.
It should be noted that Verilog HDL, abbreviated as Verilog, is a hardware description language used for the system design of digital circuits. It can model various abstract design levels such as algorithm level, gate level, switch level and the like. Verilog defines not only grammar, but also clear simulation semantics for grammar structures. Thus, a digital model written by Verilog can be validated using a Verilog simulator.
In one embodiment, the method for generating the definition file includes: configuring a system bus address segment corresponding to the target memory; defining interaction rules of the chip design and the verification platform according to the configured system bus address field; and distributing corresponding index segments for each interaction unit in the verification platform interaction module based on the interaction rule so as to generate a definition file.
The manner in which the verification platform is built will be explained in detail below in connection with fig. 2:
the first step: determining a target memory in a chip design to be verified;
specifically, the method for determining the target memory in the chip design to be verified includes: screening a memory with memory attribute conforming to at least one of attribute characteristics from a plurality of memories included in the chip design to be verified based on a memory selection rule, and determining the screened memory as a target memory;
wherein the attribute features include:
first feature: the system bus of the memory is connected with the kernel and belongs to slave equipment on the system bus; for example, the connection between the core and the memory in the first feature is shown in the connection between the core and the memory in fig. 3;
the second feature is: the system bus response of the memory can be simplified into read-write operation, that is, the system bus can only execute the read operation and the write operation in the system bus operation;
third feature: the memory is directly addressable by the core, i.e., the core can directly access the address of the memory;
fourth feature: the delay of the operation of the kernel to the memory is low;
Fifth feature: the data path from the core to the memory is shortest; specifically, as shown in fig. 3, the data path from the core to the memory is the core and the memory, that is, the data passes through two units, and the path from the core to the pin is the core, the peripheral 1, and the pin, that is, the data passes through three units. The core-to-memory data path is short compared to the core-to-pin path. When selecting the memory, referring to the mode of judging the data path, selecting the memory with the shortest data path from the memory to the kernel in the chip design.
It should be noted that, the memory with the shortest data path is not necessarily the target memory, and those skilled in the art may select the optimal memory from all memories in the chip design as the target memory in the present invention according to actual requirements.
And a second step of: and writing the memory bus interface proxy module by using verilog language.
Specifically, after the memory bus interface proxy module is written, the memory bus interface proxy module takes over the bus access operation originally executed by the kernel in the chip design and connected with the system bus connected with the target memory by utilizing the mandatory (force) characteristic of verilog language, so as to realize the data interaction between the verification platform and the chip design kernel.
It should be noted that, the reason that the verification platform can directly interact with the chip design kernel is that the verification platform and the chip design are written in verilog language.
And a third step of: and writing an interactive module of the verification platform according to the design verification requirement of the target chip.
Specifically, the verification platform interaction module includes a plurality of interaction units, and each interaction unit is used for executing a chip design verification operation. And writing corresponding interaction units according to each chip design verification project included in the target chip design verification requirement, so that the verification platform interaction module can complete all projects needing verification. After the memory bus interface proxy module and the verification platform interaction module are written, and the two modules are correspondingly connected as shown in fig. 1, a preliminarily built verification platform is obtained.
Fourth step: after the initially built verification platform is obtained, a definition file is required to be generated, and the verification platform is further configured. The definition file defines a rule for distinguishing various data. Because the verification platform and the chip design use a common definition file, the verification platform can better distinguish the information types from the kernel so as to execute corresponding operations.
The manner of generating the definition file is shown in fig. 4, specifically:
firstly, configuring a system bus address segment corresponding to a target memory; for example, the address of the selected target memory in the chip design is 9000, the address transfer instruction information of the target memory address +0 is allocated, and the address transfer instruction specific information of the target memory address +800 is allocated. Thus, the memory bus interface agent module can distinguish the types of the information according to the address field after obtaining the information in the bus so as to execute corresponding operations.
And secondly, defining interaction rules of the kernel and the verification platform according to the configured system bus address field. The interaction rules specify the data format of the chip design verification instructions sent by the core and how the verification platform parses the received chip design verification instructions for the verification platform to determine the type of chip design verification operation to be performed after receiving the chip design verification instructions sent by the chip design.
For example, the kernel sends a trigger command through the 9000 bus address, the Index for transmitting the trigger command through the 9800 address is 500, the memory bus interface agent module receives the trigger command sent by the 9000 bus address, and determines the specific content of the instruction to be executed according to the Index500 transmitted through the 9800 address through the defined interaction rule.
Then, different index (index) segments are allocated for different interaction units, namely different verification items, so that the verification platform can determine the type of chip design verification operation to be performed based on the index segments; for example, after receiving an instruction with index segment 500-600, the verification platform controls the chip design to execute the verification operation of pin a, and after receiving an instruction with index segment 600-700, the verification platform controls the chip design to execute the verification operation of pin B.
In one embodiment, as shown in fig. 5, the memory bus interface agent module 21 includes: the read-write operation execution unit and the communication processor; the read-write operation execution unit 211 is configured to execute a bus access operation on a system bus connected to a target memory in the chip design 1, and capture a chip design verification instruction issued to the target memory by the core during the bus access operation; and is further configured to write captured chip design verification instructions to the communication processor 212 and read verification result data uploaded by the verification platform interaction module 22 from the communication processor 212;
a communication processor 212, connected to the read-write operation execution unit 211, configured to notify, when receiving a chip design verification instruction written by the read-write operation execution unit 211, the verification platform interaction module 22 to obtain specific information of the chip design verification instruction from the communication processor 212, so that the verification platform interaction module 22 performs a corresponding chip design verification operation based on the specific information of the chip design verification instruction; and is further configured to store the verification result data uploaded by the verification platform interaction module 22, so that the read-write operation execution unit 211 reads out and sends the verification result data to the kernel.
Note that, since the read/write operation execution unit 211 performs a bus access operation on the system bus connected to the target memory in the chip design, the data that the core originally transmits to the target memory through the system bus connected to the target memory is acquired by the read/write operation execution unit 211. Under such a data transmission path, the read-write operation execution unit 211 will write the chip design verification instruction issued by the core into the communication processor 212 after receiving it, and the verification result data uploaded by the verification platform interaction module 22 stored in the communication processor will be read out and sent to the core by the read-write operation execution unit 211.
In one embodiment, as shown in fig. 6, the read/write operation execution unit includes: a bus interface subunit 211a, configured to perform a bus access operation on a system bus connected to a target memory in the chip design 1, and capture a chip design verification instruction issued by the core to the target memory in a process of performing the bus access operation;
the bus behavior analysis subunit 211b is connected with the bus interface subunit 211a, and is configured to determine and adopt a corresponding bus communication protocol based on a type of a system bus accessed by the bus interface subunit 211a, so that data transmission is performed between the kernel and the verification platform interaction module 22 through the bus communication protocol;
A memory behavior abstraction subunit 211c, connected to the bus behavior parsing subunit 211b, is configured to write the chip design verification instruction captured by the bus interface subunit 211a to the communication processor 212, and read out the verification result data uploaded by the verification platform interaction module 22 from the communication processor 212.
It should be noted that, the function of the memory behavior abstraction subunit 211c is to use only the communication protocol related to the read/write operation in the bus communication protocol, so as to implement the read/write operation function for the communication processor 212.
In one embodiment, the bus behavior analysis subunit 211b determines the type of the system bus connecting the target memory and the kernel based on the type of the target memory; and determining and adopting a bus communication protocol adopted by the system bus based on the type of the system bus.
In one embodiment, as shown in fig. 7, the communication processor 212 includes:
an event processor subunit 212b, a virtual memory subunit 212a connected to the event processor subunit 212 b;
the virtual memory subunit 212a is connected to the memory behavior abstraction subunit 211c and the verification platform interaction module 22, and is configured to store specific data of a chip design verification instruction written by the memory behavior abstraction subunit 211c and verification result data sent by the verification platform interaction module 22;
The event processor subunit 212b is respectively connected to the memory behavior abstraction subunit 211c and the verification platform interaction module 22, and is configured to notify, after receiving a chip design verification instruction written by the memory behavior abstraction subunit 211c, the verification platform interaction module 22 to read out specific information of the chip design verification instruction from the virtual memory subunit 212a, so that the verification platform interaction module 22 performs a corresponding chip design verification operation based on the specific information of the chip design verification instruction.
It should be noted that, the communication processor 212 also stores tasks (tasks) and functions (functions) that can be directly invoked by the verification platform interaction module 22. Event handler subunit 212b may also convert event instructions sent by verification platform interaction module 22 into memory data to wait for core reads.
Similar to the above embodiment, the present invention also provides a chip design verification method.
Specific embodiments are provided below with reference to the accompanying drawings:
fig. 8 is a schematic flow chart of a chip design verification method according to an embodiment of the invention.
The chip design verification method is applied to a chip design verification platform, and the chip design verification platform comprises: a memory bus interface proxy module, the method comprising:
Step S801: performing bus access operation on a system bus connected with a target memory in a chip design to be verified, and capturing a chip design verification instruction issued to the target memory by a core in the chip design in the process of performing the bus access operation; the chip design verification instruction is issued by the kernel based on target chip design verification requirements;
step S802: based on the received chip design verification instruction captured and issued by the memory bus interface proxy module, executing corresponding chip design verification operation, and uploading the obtained corresponding verification result data to the kernel through the memory bus interface proxy module after the chip design verification operation is executed.
In one embodiment, the method for building the chip design verification platform includes: screening a memory in the chip design to be verified and determining the memory as a target memory; writing a memory bus interface proxy module by using verilog language, and enabling the memory bus interface proxy module to take over bus access operation executed by an internal core in the chip design and connected with a system bus of the target memory; writing a verification platform interaction module according to the target chip design verification requirement so as to obtain a preliminarily built chip design verification platform; generating a definition file, and applying the definition file to the preliminarily built verification platform to obtain a final chip design verification platform.
In one embodiment, the method for generating the definition file includes: configuring a system bus address segment corresponding to the target memory; defining interaction rules of the chip design and the verification platform according to the configured system bus address field; and distributing corresponding index segments for each interaction unit in the verification platform interaction module based on the interaction rule so as to generate a definition file.
In one embodiment, the memory bus interface agent module comprises: the read-write operation execution unit and the communication processor; the read-write operation execution unit is used for performing bus access operation on a system bus connected with a target memory in the chip design and capturing a chip design verification instruction issued to the target memory by the core in the process of performing the bus access operation; the system is also used for writing a captured chip design verification instruction into the communication processor and reading verification result data uploaded by the verification platform interaction module from the communication processor; the communication processor is connected with the read-write operation execution unit and is used for notifying the verification platform interaction module to obtain specific information of the chip design verification instruction from the communication processor after receiving the chip design verification instruction written by the read-write operation execution unit so that the verification platform interaction module can execute corresponding chip design verification operation based on the specific information of the chip design verification instruction; and the verification platform interaction module is also used for storing the verification result data after uploading the verification result data so that the read-write operation execution unit reads out the verification result data and sends the verification result data to the kernel.
In one embodiment, the read/write operation execution unit includes: the bus interface subunit is used for performing bus access operation on a system bus connected with a target memory in the chip design and capturing a chip design verification instruction issued to the target memory by the core in the process of performing the bus access operation; a bus behavior analysis subunit, connected to the bus interface subunit, for determining and applying a corresponding bus communication protocol based on the type of the system bus accessed by the bus interface subunit; and the memory behavior abstraction subunit is connected with the bus behavior analysis subunit and is used for writing the chip design verification instruction captured by the bus interface subunit into the communication processor and reading verification result data uploaded by the verification platform interaction module from the communication processor.
In one embodiment, the communication processor comprises: an event processor subunit and a virtual memory subunit connected to the event processor subunit; the virtual memory subunit is respectively connected with the memory behavior abstraction subunit and the verification platform interaction module and is used for storing specific information of a chip design verification instruction written in by the memory behavior abstraction subunit and verification result data uploaded by the verification platform interaction module; the event processor subunit is respectively connected with the memory behavior abstraction subunit and the verification platform interaction module, and is used for notifying the verification platform interaction module to read out specific information of the chip design verification instruction from the virtual memory subunit after receiving the transmitted chip design verification instruction written in by the memory behavior abstraction subunit, so that the verification platform interaction module can execute corresponding chip design verification operation based on the specific information of the chip design verification instruction.
It should be noted that, the chip design verification method in this embodiment is similar to all the functions of the chip design verification system provided above, and therefore, the description thereof is omitted.
Fig. 9 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
The terminal 9 includes: a processor 92 and a memory 91; the memory 91 is used for storing a computer program; the processor 92 is configured to execute the computer program stored in the memory, so that the terminal 9 performs the chip design verification method as described in fig. 8.
Alternatively, the number of the memories 91 may be one or more, and the number of the processors 92 may be one or more, and one is taken as an example in fig. 9.
Alternatively, the processor 92 in the control device loads one or more instructions corresponding to the process of the application program into the memory 91 according to the steps as shown in fig. 8, and the processor 92 executes the application program stored in the first memory, thereby implementing various functions in the chip design verification method as shown in fig. 8.
Optionally, the memory 91 may include, but is not limited to, high speed random access memory, nonvolatile memory. Such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices; the processor 92 may include, but is not limited to, a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but also digital signal processors (Digital Signal Processing, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), field-programmable gate arrays (Field-Programmable Gate Array, FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
Alternatively, the processor 92 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but also digital signal processors (Digital Signal Processing, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), field-programmable gate arrays (Field-Programmable Gate Array, FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
The present invention also provides a computer readable storage medium storing a computer program which when run implements a chip design verification method as described in fig. 8. The computer-readable storage medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (compact disk-read only memories), magneto-optical disks, ROMs (read-only memories), RAMs (random access memories), EPROMs (erasable programmable read only memories), EEPROMs (electrically erasable programmable read only memories), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions. The computer readable storage medium may be an article of manufacture that is not accessed by a computer device or may be a component used by an accessed computer device.
In some embodiments of the invention, the computer-readable and writable storage medium may include read-only memory, random-access memory, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, U-disk, removable hard disk, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable and data storage media do not include connections, carrier waves, signals, or other transitory media, but are intended to be directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.
Similar to the above embodiment, the present invention also provides a chip design verification system, including: chip design verification platform and chip design to be verified by the chip design verification platform.
It should be noted that, since the chip design verification platform in this embodiment is similar to the chip design verification platform implementation in the above embodiment, the description is not repeated here.
In summary, the present application provides a chip design verification platform, a method, a terminal, a medium, and a system, where a memory bus interface proxy module in the verification platform directly performs data interaction with a core in a chip design to be verified, so that a verification platform interaction module connected with the memory bus interface proxy module executes a corresponding chip design verification operation based on a received chip design verification instruction sent by the core, and sends obtained corresponding verification result data to the core after the execution of the chip design verification operation is completed. The data interaction mode of the kernel and the verification platform avoids unnecessary data paths, shortens response period, reduces response delay, improves instantaneity, and enhances comprehensiveness and instantaneity in the verification process, so that chip verification is more complete.
The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.
Claims (10)
1. A chip design verification platform, comprising:
the memory bus interface agent module is used for performing bus access operation on a system bus connected with a target memory in a chip design to be verified, and capturing a chip design verification instruction issued to the target memory by a core in the chip design in the process of performing the bus access operation; the chip design verification instruction is issued by the kernel based on target chip design verification requirements;
and the verification platform interaction module is connected with the memory bus interface proxy module and is used for executing corresponding chip design verification operation based on the received chip design verification instruction captured and issued by the memory bus interface proxy module, and uploading the obtained corresponding verification result data to the kernel through the memory bus interface proxy module after the chip design verification operation is executed.
2. The chip design verification platform of claim 1, wherein the means for building the chip design verification platform comprises:
screening a memory in the chip design to be verified and determining the memory as a target memory;
writing a memory bus interface proxy module by using verilog language, and enabling the memory bus interface proxy module to take over bus access operation executed by an internal core in the chip design and connected with a system bus of the target memory;
writing a verification platform interaction module according to the target chip design verification requirement so as to obtain a preliminarily built chip design verification platform;
generating a definition file, and applying the definition file to the preliminarily built verification platform to obtain a final chip design verification platform.
3. The chip design verification platform of claim 2, wherein the means for generating the definition file comprises:
configuring a system bus address segment corresponding to the target memory;
defining interaction rules of the chip design and the verification platform according to the configured system bus address field;
and distributing corresponding index segments for each interaction unit in the verification platform interaction module based on the interaction rule so as to generate a definition file.
4. The chip design verification platform of claim 2, wherein the memory bus interface agent module comprises: the read-write operation execution unit and the communication processor;
the read-write operation execution unit is used for performing bus access operation on a system bus connected with a target memory in the chip design and capturing a chip design verification instruction issued to the target memory by the core in the process of performing the bus access operation; the system is also used for writing a captured chip design verification instruction into the communication processor and reading verification result data uploaded by the verification platform interaction module from the communication processor;
the communication processor is connected with the read-write operation execution unit and is used for notifying the verification platform interaction module to obtain specific information of the chip design verification instruction from the communication processor after receiving the chip design verification instruction written by the read-write operation execution unit so that the verification platform interaction module can execute corresponding chip design verification operation based on the specific information of the chip design verification instruction; and the verification platform interaction module is also used for storing the verification result data after uploading the verification result data so that the read-write operation execution unit reads out the verification result data and sends the verification result data to the kernel.
5. The chip design verification platform of claim 4, wherein the read-write operation execution unit comprises: the bus interface subunit is used for performing bus access operation on a system bus connected with a target memory in the chip design and capturing a chip design verification instruction issued to the target memory by the core in the process of performing the bus access operation;
a bus behavior analysis subunit, connected to the bus interface subunit, for determining and applying a corresponding bus communication protocol based on the type of the system bus accessed by the bus interface subunit;
and the memory behavior abstraction subunit is connected with the bus behavior analysis subunit and is used for writing the chip design verification instruction captured by the bus interface subunit into the communication processor and reading verification result data uploaded by the verification platform interaction module from the communication processor.
6. The chip design verification platform of claim 5, wherein the communication processor comprises:
an event processor subunit and a virtual memory subunit connected to the event processor subunit;
The virtual memory subunit is respectively connected with the memory behavior abstraction subunit and the verification platform interaction module and is used for storing specific information of a chip design verification instruction written in by the memory behavior abstraction subunit and verification result data uploaded by the verification platform interaction module;
the event processor subunit is respectively connected with the memory behavior abstraction subunit and the verification platform interaction module, and is used for notifying the verification platform interaction module to read out specific information of the chip design verification instruction from the virtual memory subunit after receiving the transmitted chip design verification instruction written in by the memory behavior abstraction subunit, so that the verification platform interaction module can execute corresponding chip design verification operation based on the specific information of the chip design verification instruction.
7. The chip design verification method is characterized by being applied to a chip design verification platform, wherein the chip design verification platform comprises the following components: a memory bus interface proxy module, the method comprising:
performing bus access operation on a system bus connected with a target memory in a chip design to be verified, and capturing a chip design verification instruction issued to the target memory by a core in the chip design in the process of performing the bus access operation; the chip design verification instruction is issued by the kernel based on target chip design verification requirements;
Based on the received chip design verification instruction captured and issued by the memory bus interface proxy module, executing corresponding chip design verification operation, and uploading the obtained corresponding verification result data to the kernel through the memory bus interface proxy module after the chip design verification operation is executed.
8. A terminal, comprising: a processor and a memory;
the memory is used for storing a computer program;
the processor is configured to execute the computer program stored in the memory, so as to cause the terminal to perform the method according to claim 7.
9. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method of claim 7.
10. A chip design verification system, comprising: a chip design verification platform according to any one of claims 1 to 6 and a chip design to be verified by the chip design verification platform.
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