CN115587026A

CN115587026A - Chip testing method and device, storage medium and chip

Info

Publication number: CN115587026A
Application number: CN202211180751.7A
Authority: CN
Inventors: 杨健明; 黄立伟; 刘浩; 张静
Original assignee: Zhuhai Huge Ic Co ltd
Current assignee: Zhuhai Huge Ic Co ltd
Priority date: 2022-09-27
Filing date: 2022-09-27
Publication date: 2023-01-10

Abstract

The embodiment of the application discloses a chip testing method and device, a storage medium and a chip, and relates to the field of chips. This application uses the chip of same set of procedure to different packaging methods to test, improves test process's compatibility to and reduce test code's the work load of compiling, in addition, through externally setting up the test data that off-chip memory storage chip produced, for test equipment initiative gather test data on the IO pin of chip, can reduce the IO operation of chip, reduce the processing cost of chip.

Description

Chip testing method and device, storage medium and chip

Technical Field

The present disclosure relates to the field of chips, and in particular, to a chip testing method and apparatus, a storage medium, and a chip.

Background

FT (Final Test) is performed on the chips before mass production, and for cost reasons, different packaging manners may be adopted for the same core die, and the number of IO pins of the chips with different packaging manners may also be different. In the existing FT, the test device communicates with each IO pin of the chip to complete the test process, however, when testing chips of different packaging modes, the test device and the test codes in the chip need to be configured according to the distribution of the IO pins of the chip, which greatly increases the writing workload of the test codes and reduces the test efficiency.

Disclosure of Invention

The embodiment of the application provides a chip testing method, a chip testing device, a storage medium and a chip, and can solve the problem that testing efficiency is not high when testing equipment writes testing codes for chips in different packaging modes during testing in the prior art. The technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a chip testing method, where the chip is provided with a first debug pin and a second debug pin, where the first debug pin and the second debug pin are IO pins, the first debug pin is connected to a clock pin of an off-chip memory, and the second debug pin is connected to a data pin of the off-chip memory;

wherein the method comprises the following steps:

when a preset condition is met, switching to a test mode;

receiving a clock signal through the first debugging pin in a test mode;

receiving a test instruction from test equipment through the second debugging pin;

executing a test operation according to the test instruction;

and if the test operation generates test data, writing the test data into an off-chip memory through the second debugging pin.

In a second aspect, an embodiment of the present application provides a chip testing apparatus, which is applied to a chip, where the chip is provided with a first debug pin and a second debug pin, the first debug pin and the second debug pin are IO pins, the first debug pin is connected to a clock pin of an off-chip memory, and the second debug pin is connected to a data pin of the off-chip memory;

wherein, the chip testing device includes:

the switching unit is used for switching to a test mode when a preset condition is met;

the receiving and sending unit is used for receiving a clock signal through the first debugging pin in a test mode;

the transceiver unit is further configured to receive a test instruction from the test device through the second debug pin;

the execution unit is used for executing the test operation according to the test instruction;

and the writing unit is used for writing the test data into an off-chip memory through the second debugging pin if the test operation generates the test data.

In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the above-mentioned method steps.

In a fourth aspect, an embodiment of the present application provides a chip, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the above-mentioned method steps.

The beneficial effects brought by the technical scheme provided by some embodiments of the application at least comprise:

two universal debugging pins of the chip are interacted with the chip, one debugging pin is used as a clock signal of the chip, the other debugging pin is used as an input pin for sending a test instruction by the test equipment, the chip executes test operation based on the test instruction from the test equipment, and then test data generated in the test process is written into an external memory so that the test equipment can read the test data from the external memory to judge whether the test is passed or not. Therefore, when the test equipment tests the chips of the same core in different packaging modes, the same set of program is used for testing the chips in different packaging modes without changing the program in the test equipment and the chip, the compatibility of the test process is improved, the writing workload of test codes is reduced, in addition, the test data generated by the chip is stored in an off-chip memory through the external setting, the test data is actively collected on the IO pin of the chip relative to the test equipment, the IO operation of the chip can be reduced, and the processing expense of the chip is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic diagram of a network architecture provided in an embodiment of the present application;

FIG. 2 is a schematic flowchart of a chip testing method according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram illustrating a memory space distribution of an on-chip memory according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a chip testing apparatus provided in the present application;

fig. 5 is a schematic structural diagram of a chip provided in the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be noted that the chip testing method provided by the present application is generally executed by a chip testing apparatus, and accordingly, the chip testing apparatus is generally disposed in a chip.

Fig. 1 shows an exemplary system architecture that can be applied to the chip testing method or the chip testing apparatus of the present application.

As shown in fig. 1, the system architecture may include: a test device 1, a chip 2, an off-chip memory 3 and a test fixture (not shown in fig. 1) provided with one or more sockets into which the chip is embedded for communication with the test device and the off-chip memory 3.

The testing device 1 communicates with the chip 2 in a serial mode, the chip 2 communicates with the off-chip memory 3 in a serial mode, and the testing device 1 communicates with the off-chip memory 3 in a serial mode. For example: the Serial port communication protocol is an SPI (Serial Peripheral Interface) protocol, and the corresponding off-chip memory is a flash memory of the SPI Interface.

Wherein, chip 2 of this application can be singlechip, microcontroller, treater or other integrated circuit that play the control effect, for example: the model of the chip is STM32. In the prior art, chip 2 is provided with a plurality of IO pins, and there are at least two debugging pins in a plurality of IO pins: the first debugging pin (debug 1) and the second debugging pin (debug 2), the debugging pin of the chip is used as a common IO pin in a normal working mode, and the debugging pin plays a debugging role in a testing mode. In the embodiment of the application, a first debugging pin of a chip is used as an input pin of a clock signal, and a second debugging pin is used as an input pin of a control instruction. The test device 1 is connected with the chip 2 through a first debugging pin and a second debugging pin, the first debugging pin of the chip 2 is connected with a clock pin (clk) of the off-chip memory, and the second debugging pin of the chip 2 is connected with a data pin (data) of the off-chip memory.

The test equipment 1 includes, but is not limited to, a test machine, a test host, a test server, or the like.

It should be understood that the number of test equipment, chips, and off-chip memories in FIG. 1 are merely illustrative. Any number may be used, depending on implementation needs.

The chip testing method provided by the embodiment of the present application will be described in detail below with reference to fig. 2. The chip testing apparatus in the embodiment of the present application may be the chip testing apparatus shown in fig. 1.

Fig. 2 is a schematic flow chart of a chip testing method according to an embodiment of the present disclosure. As shown in fig. 2, the method of the embodiment of the present application may include the steps of:

s201, when a preset condition is met, switching to a test mode.

In the present embodiment, the preset conditions are not limited to: receiving a switching instruction of a user, receiving a specified sequence on a second debugging pin, or detecting a high level on a first debugging pin or a second debugging pin, switching a chip to a test mode when the chip meets a preset condition, and testing the chip by test equipment in the test mode to test whether each index of the chip is normal. And in the normal working mode, the first debugging pin and the second debugging pin are used as common IO pins, and the chip calls a main program code in the on-chip memory to execute a corresponding function.

S202, in a test mode, receiving a clock signal through a first debugging pin.

In this embodiment, a first debug pin of a chip is used as a clock pin to receive a clock signal, where the clock signal may be provided by a test device or an external clock source.

S203, receiving a test instruction from the test equipment through the second debugging pin.

In this embodiment, the second debug pin receives a test instruction from the test device, where the test instruction includes but is not limited to: the method comprises the following steps of reading a register instruction, writing the register instruction, reading an on-chip memory instruction, writing the on-chip memory instruction, continuing to execute a program and setting a program starting address.

The chip inquires the corresponding register according to the register address after receiving the register reading instruction, then reads the value in the register, and writes the read value into the off-chip memory through the second debugging pin.

The chip inquires a corresponding register according to the register address after receiving the register writing instruction, and then writes the value in the register.

The on-chip memory reading instruction is used for reading a value of an on-chip memory in the chip, the on-chip memory comprises a ROM and a RAM, the on-chip memory comprises a plurality of memory units, each memory unit corresponds to a memory unit address, the size of each memory unit can be determined according to actual requirements, the on-chip memory reading instruction carries the memory unit address and a reading operation code, and the chip writes the read value into the off-chip memory through a second debugging pin.

Further, after the chip writes the main program code, whether the main program code is correct is judged according to an on-chip memory instruction from the test equipment, and the judgment process is as follows: the chip reads the main program code and the corresponding CRC check code in the main code area, calculates the main program code to obtain the CRC check code, compares whether the calculated CRC check code is the same as the read CRC check code, if so, the check is passed, otherwise, the check is not passed.

The chip receives the command of writing the on-chip memory, and firstly points to an erasing operation on a sector where the memory unit is located, and then executes the writing operation.

The program continuous execution instruction is used for instructing the chip to continuously execute the program, after the chip completes the test of one test item, the chip can execute a waiting operation to wait for executing the next test item, and after the test equipment sends the program continuous execution instruction to the chip, the chip executes the next test item.

The program starting address setting instruction is used for setting a starting address of a main program code of the chip, and the chip can execute the main program code at the starting address after being electrified.

For example: referring to the schematic memory space distribution diagram of the on-chip memory of the chip shown in fig. 3, the on-chip memory is provided with a start boot area and a main code area, the start boot area and the main code area are continuously distributed, the chip sets a start address of the main code area according to a program start address, and the chip runs a main program code in the main code area according to the start after being powered on.

And S204, executing test operation according to the test command.

And S205, if the test operation generates test data, writing the test data into the off-chip memory through the second debugging pin.

When the test operation is write operation, modifying the value of the on-chip memory or the register; the test operation is a write operation, which reads a value of an on-chip register or a register, and then writes the read value (i.e., test data) into the off-chip memory through the second debug pin. Further, the off-chip memory may be a flash memory of the SPI interface. After the test equipment finishes testing, the test equipment reads out the test data in the off-chip memory, and compares the read test data with the pre-stored standard data to judge whether the chip test is passed. By the method for storing the test data by the off-chip memory, the test equipment does not need to collect data at an IO pin, and the test efficiency is improved.

When the test equipment tests the chip in the embodiment of the application, two universal debugging pins of the chip are interacted with the chip, one debugging pin is used as the chip to provide a clock signal, the other debugging pin is used as an input pin for the test equipment to send a test instruction, the chip executes a test operation based on the test instruction from the test equipment, and then test data generated in the test process is written into an external memory so that the test equipment can read the test data in the external memory to judge whether the test is passed or not. Therefore, when the test equipment tests the chips of the same cores in different packaging modes, the same set of programs can be used for testing the chips in different packaging modes without changing the programs in the test equipment and the chips, the compatibility of the test process is improved, the writing workload of test codes is reduced, in addition, the test data generated by storing the chips by the off-chip memory is arranged outside, the test data is actively collected on the IO pins of the chips relative to the test equipment, the IO operation of the chips can be reduced, and the processing overhead of the chips is reduced.

The following are embodiments of the apparatus of the present application that may be used to perform embodiments of the method of the present application. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.

Referring to fig. 4, a schematic structural diagram of a chip testing apparatus provided in an exemplary embodiment of the present application is shown, which is hereinafter referred to as an apparatus 4. The means 4 may be implemented as all or part of a chip by software, hardware or a combination of both. The device 4 comprises: switching section 401, transmitting/receiving section 402, execution section 403, and writing section 404.

A switching unit 401, configured to switch to a test mode when a preset condition is met;

a transceiving unit 402, configured to receive a clock signal through the first debug pin in a test mode;

the transceiver unit 402 is further configured to receive a test instruction from a test device through the second debug pin;

an execution unit 403, configured to execute a test operation according to the test instruction;

a writing unit 404, configured to write the test data into an off-chip memory through the second debug pin if the test operation generates the test data.

In one or more possible embodiments, the test instructions include:

a register read instruction, a register write instruction, an on-chip memory read instruction, an on-chip memory write instruction, a program continue execution instruction, or a program start address set instruction.

In one or more possible embodiments, the chip and the off-chip memory communicate via a Serial Peripheral Interface (SPI) protocol.

In one or more possible embodiments, the performing a test operation according to the test instruction:

reading a main program code and an associated cyclic check CRC code in a main code area according to the memory reading instruction;

calculating a CRC code according to the read main program code;

comparing whether the read CRC code and the calculated CRC code are the same;

if the main program codes are the same, the main program codes pass the verification;

and if not, the main program code passes the verification.

In one or more possible embodiments, the preset conditions include: receiving a switching instruction from a user; or receiving a specified sequence from the test equipment through a second debugging pin; or detecting that the level on the first debugging pin and the second debugging pin is high level.

In one or more possible embodiments, the clock signal is provided by the test equipment or an external clock source.

In one or more possible embodiments, the chip is an STM32 series chip.

It should be noted that, when the apparatus 4 provided in the foregoing embodiment executes the chip testing method, only the division of each functional module is illustrated, and in practical applications, the function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the chip testing apparatus and the chip testing method provided by the above embodiments belong to the same concept, and details of implementation processes thereof are referred to in the method embodiments and are not described herein again.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

An embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, where the instructions are suitable for being loaded by a processor and executing the method steps in the embodiment shown in fig. 2, and a specific execution process may refer to a specific description of the embodiment shown in fig. 2, which is not described herein again.

The present application further provides a computer program product, which stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the chip testing method according to the above embodiments.

Fig. 5 is a schematic diagram of a chip according to an embodiment of the present disclosure. As shown in fig. 5, the chip 500 may include: at least one processor 501, at least one network interface 504, memory 503, at least one communication bus 502.

Wherein a communication bus 502 is used to enable connective communication between these components.

The network interface 504 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.

Processor 501 may include one or more processing cores, among other things.

The processor 501 connects various parts within the entire chip 500 using various interfaces and lines, and performs various functions of the chip 500 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 503 and calling data stored in the memory 503. Optionally, the processor 501 may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 501 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 501, but may be implemented by a single chip.

The Memory 503 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 503 includes a non-transitory computer-readable medium. The memory 503 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 503 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above-mentioned method embodiments, and the like; the storage data area may store data and the like referred to in the above respective method embodiments. The memory 503 may alternatively be at least one memory device located remotely from the processor 501. As shown in fig. 5, the memory 503, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and an application program.

In the chip 500 shown in fig. 5, the processor 501 may be configured to call an application program stored in the memory 503 and specifically execute the method shown in fig. 2, and the specific process may refer to fig. 2 and is not described herein again.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory or a random access memory.

The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and is not to be construed as limiting the scope of the present application, so that the present application is not limited thereto, and all equivalent variations and modifications can be made to the present application.

Claims

1. A chip testing method is characterized in that the method is applied to a chip, the chip is provided with a first debugging pin and a second debugging pin, the first debugging pin and the second debugging pin are IO pins, the first debugging pin is connected with a clock pin of an off-chip memory, and the second debugging pin is connected with a data pin of the off-chip memory;

wherein the method comprises the following steps:

when a preset condition is met, switching to a test mode;

receiving a clock signal through the first debugging pin in a test mode;

executing test operation according to the test instruction;

2. The method of claim 1, wherein the test instructions comprise:

a read register instruction, a write register instruction, a read on-chip memory instruction, a write on-chip memory instruction, a program resume instruction, or a program start address set instruction.

3. The method of claim 1 or 2, wherein the chip and the off-chip memory communicate via a Serial Peripheral Interface (SPI) protocol.

4. The method of claim 2, wherein the performing a test operation according to the test instruction:

reading a main program code and a related cyclic check CRC code in a main code area according to the memory reading instruction;

calculating a CRC code according to the read main program code;

comparing whether the read CRC code is the same as the calculated CRC code;

and if not, the main program code passes the verification.

5. The method according to claim 1, 2 or 4, wherein the preset conditions comprise: receiving a switching instruction from a user; or receiving a specified sequence from the test equipment through a second debugging pin; or detecting that the level on the first debugging pin and the second debugging pin is high level.

6. The method of claim 5, wherein the clock signal is provided by test equipment or an external clock source.

7. The method of claim 6, wherein the chip is an STM32 series chip.

8. A chip testing device is characterized in that the chip testing device is applied to a chip, the chip is provided with a first debugging pin and a second debugging pin, the first debugging pin and the second debugging pin are IO pins, the first debugging pin is connected with a clock pin of an off-chip memory, and the second debugging pin is connected with a data pin of the off-chip memory;

wherein, the chip testing device includes:

the receiving and transmitting unit is used for receiving a clock signal through the first debugging pin in a test mode;

9. A computer storage medium, characterized in that it stores a plurality of instructions adapted to be loaded by a processor and to perform the method steps according to any one of claims 1 to 7.

10. A chip, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1 to 7.