CN114116364A - Chip debugging method, storage medium, related device and system - Google Patents
Chip debugging method, storage medium, related device and system Download PDFInfo
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- CN114116364A CN114116364A CN202111416658.7A CN202111416658A CN114116364A CN 114116364 A CN114116364 A CN 114116364A CN 202111416658 A CN202111416658 A CN 202111416658A CN 114116364 A CN114116364 A CN 114116364A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- G06F11/273—Tester hardware, i.e. output processing circuits
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Abstract
The embodiment of the application discloses a debugging method and device of a chip, a storage medium, a test host and a system. The debugging method comprises the following steps: sending a connection request to a debugger; after receiving a connection success response sent by the debugger, establishing communication connection with the debugger; determining a chip model of a target chip, and acquiring a dynamic configuration file associated with the chip model; sending the dynamic configuration file to the debugger through the communication connection; and after receiving a transmission success response from the debugger, indicating the debugger to debug the target chip. The debugging equipment can flexibly debug chips of various different models, improves compatibility of the debugging equipment, does not need to be replaced, and therefore testing efficiency can be improved.
Description
Technical Field
The present application relates to the field of testing, and in particular, to a method for debugging a chip, a storage medium, a related apparatus, and a related system.
Background
The existing debugger generally uses an SWD (serial wire Debug) protocol, the debugger is internally provided with an STM32F103 (32-bit ARM microcontroller), and the framework fixes the communication protocol of the debugger and a target chip. Most of the communication protocol is only suitable for the chips of the ARM core, so that the chips of the RISC (Reduced Instruction Set computer) core and the 8051 core cannot be debugged. Therefore, the compatibility of the existing debugger is poor, and the debugger cannot debug chips of various models.
Disclosure of Invention
The embodiment of the application provides a chip debugging method, a chip debugging device, a storage medium and debugging equipment, and can solve the problem of insufficient compatibility of a debugger in the related technology. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a method for debugging a chip, where the method includes:
sending a connection request to a debugger;
after receiving a connection success response sent by the debugger, establishing communication connection with the debugger;
determining a chip model of a target chip, and acquiring a dynamic configuration file associated with the chip model;
sending the dynamic configuration file to the debugger through the communication connection;
and after receiving a transmission success response from the debugger, indicating the debugger to debug the target chip.
In a second aspect, an embodiment of the present application provides a debugging apparatus for a chip, including:
sending a connection request to a debugger;
after receiving a connection success response sent by the debugger, establishing communication connection with the debugger;
determining a chip model of a target chip, and acquiring a dynamic configuration file associated with the chip model;
sending the dynamic configuration file to the debugger through the communication connection;
and after receiving a transmission success response from the debugger, indicating the debugger to debug the target chip.
In a third aspect, an embodiment of the present application provides a chip debug system, including: testing a host, a debugger and a target chip;
the test host is used for sending a connection request to the debugger; after receiving a connection success response sent by the debugger, establishing communication connection with the debugger; determining the chip model of the target chip, and acquiring a dynamic configuration file associated with the chip model; sending the dynamic configuration file to the debugger through the communication connection; after receiving a transmission success response from the debugger, indicating the debugger to debug the target chip;
the debugger is used for acquiring a fixed configuration file for configuration after the power-on is successful; after configuration is successful, receiving a connection request from the test host; after the connection request passes the authentication, sending a connection success response to the test host; receiving a dynamic configuration file from the test host; configuring according to the dynamic configuration file; after the configuration is successful, sending a transmission success response to the test host; and receiving a debugging instruction from a test host, and calling the dynamic configuration file to debug the target chip based on the debugging instruction.
In a fourth aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the above-mentioned method steps.
In a fifth aspect, an embodiment of the present application provides a test host, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the above-mentioned method steps.
The beneficial effects brought by the technical scheme provided by some embodiments of the application at least comprise:
when the target chip is debugged, the debugger loads the fixed configuration file for configuration, receives the dynamic configuration file from the test host according to the fixed configuration file, the dynamic configuration file is obtained by the test host according to the model of the target chip, and the debugger configures the debugging function of the target chip according to the dynamic configuration file so as to debug the target chip. Because chips of different models have difference in function design, the dynamic configuration file is correspondingly adjusted according to the difference, so that the flexibility and the expansibility of the debugger can be increased; in addition, the implementation can support a customized communication protocol without replacing a debugger.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a network structure diagram provided in an embodiment of the present application;
fig. 2 is a schematic flowchart of a debugging method of a chip according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a debugging apparatus of a chip according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a test host according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the appended claims.
In the description of the present application, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art. Further, in the description of the present application, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
Referring to fig. 1, a network architecture diagram provided for an embodiment of the present application includes: a test host 11, a debugger 12, and a target chip 13. The number of the debuggers 12 may be plural, and the test host 11 may perform online debugging or offline debugging on a plurality of control boards simultaneously in batch.
The test host 11 of the present application has a display device, including but not limited to: desktop, laptop, tablet, or cell phone, etc.; debugger 12 has one or more microcontrollers that include read-only memory for storing application code. The communication mode between the test host 11 and the debugger 12 may be a wired communication mode including, but not limited to, a USB cable, a URAT cable, a network cable, a coaxial cable, or other cables, or a wireless communication mode including, but not limited to: cellular data networks, bluetooth networks, WIFI networks, etc., such as: the debugging equipment and the control panel are internally provided with a cellular network data module, and communication is carried out between the cellular network and the control panel, such as: cellular networks include, but are not limited to, 2G, 3G, 4G, 5G, or next generation networks.
The interaction flow among the test host 11, the debugger 12, and the target chip 13 in this application includes: the test host 11 sends a connection request to the debugger 12; after receiving a connection success response sent by the debugger 12, establishing communication connection with the debugger 12; determining the chip model of the target chip 13 and acquiring a dynamic configuration file associated with the chip model; sending the dynamic configuration file to debugger 12 via a communication connection; after receiving the transmission success response from the debugger 12, the debugger 12 is instructed to debug the target chip 13.
After the debugger 12 is successfully powered on, acquiring a fixed configuration file from the read-only memory for configuration; after the configuration is successful, receiving a connection request from the test host 11; after the connection request passes the authentication, a connection success response is sent to the test host 11; receiving a dynamic configuration file from the test host 11; configuring according to the dynamic configuration file; after the configuration is successful, a transmission success response is sent to the test host 11; and receiving a debugging instruction from the test host 11, and calling the dynamic configuration file to debug the target chip 13 based on the debugging instruction 11. The debugging equipment 12 of the application supports two debugging modes simultaneously, can meet debugging requirements of different control panels flexibly, and improves debugging efficiency.
Referring to fig. 2, a schematic flow chart of a chip debugging method according to an embodiment of the present application is shown based on the network architecture of fig. 1. As shown in fig. 2, the method of the embodiment of the present application may include the steps of:
s201, executing a power-on process.
The user opens the switches of the test host and the debugger, and the test host and the debugger execute the power-on process.
S202, loading a fixed configuration file for configuration.
The fixed configuration file is a code downloaded to a memory before the debugger leaves the factory, and is generally called firmware, and the debugger acquires the fixed configuration file from the ROM and then records the fixed configuration file, and the fixed configuration file is used for executing a fixed and unchangeable function. The debugger supports a plurality of different chip models, the fixed configuration file is a common function of the plurality of chip models, and the common function refers to a function common to a plurality of chips of different models, for example: and functions of inquiring debugging version information, inquiring debugger ID, updating dynamic configuration files and the like.
S203, the test host sends a connection request to the debugger, and the debugger receives the connection request from the test host.
The test host sends a connection request to the debugger after being successfully powered on, the connection request is used for establishing communication connection, the connection request can carry a device ID of the test host, and the device ID can be an MAC address of the test host. The test host and the debugger may communicate with each other in a wired or wireless manner, which is not limited in this embodiment.
And S204, the debugger authenticates the connection request.
After receiving a connection request from the test host, the debugger analyzes the connection request to obtain an equipment ID of the test host, the debugger prestores an equipment white list, whether the equipment ID in the connection request is in the equipment white list is judged, and if the equipment ID in the connection request is in the equipment white list, authentication is passed; if not, the authentication is not passed.
S205, the debugger sends a connection success response to the test host.
When the authentication is passed, the debugger sends a connection success response to the test host; and when the authentication fails, the debugger sends a connection failure response to the test host.
And S206, establishing communication connection between the test host and the debugger.
When the test host receives the connection success response from the debugger, the test host establishes communication connection with the debugger, and then data can be transmitted through the communication connection. And if the test host receives a connection failure response from the debugger, displaying an error prompt message, wherein the error prompt message comprises the reason of the connection failure.
In addition, the test host can start a timer to time after sending the connection request, and if a connection success response from the debugger is received within a preset time length, communication connection is established between the test host and the debugger; if the connection success response from the debugger is not received within the preset time length, the communication connection between the test host and the debugger cannot be established, the test host displays an error prompt message, and the error prompt message indicates that the communication connection between the test host and the debugger is not successfully established. The preset duration can be determined according to actual requirements, and the application is not limited, for example: the preset time period is 3 seconds.
And S207, determining the chip model of the target chip.
The target chip is connected with the debugger, and the target chip is a chip to be debugged by the debugger.
The method for determining the chip model of the target chip by the test host may be as follows:
the method comprises the following steps: the test host displays a chip model list through the display device; and the user triggers a selection instruction for the chip model list through the input device, and the test host takes the chip model selected by the selection instruction as the chip model of the target chip.
In the second method, when the target chip and the debugger establish communication connection, for example: the target chip is inserted into a chip slot of the debugger, the debugger can read a chip signal of the target chip, and then the chip signal of the target chip is sent to the test host according to the communication connection of the S206, and the test host determines the chip model of the target chip accordingly.
And S208, acquiring a dynamic configuration file associated with the chip model.
The test host stores mapping relationship between chip signals and dynamic configuration files in advance, the dynamic configuration files are used for executing the difference function of the chips, and the difference function is different from other chips, namely different chip models correspond to different dynamic configuration files. The dynamic configuration file mainly performs a program downloading function and an online debugging function. The Program download functions include a full Erase (CHIP Erase), a Sector Erase (Sector Erase), a Program download (Code Program), and a Program Verify (Code Verify). The online debugging function includes Run (Run), Stop (Stop), single Step (Step), Set Breakpoint (Set Breakpoint), Read Memory (Read Memory), program Memory (Write Memory), and the like.
S209, the test host sends the dynamic configuration file to the debugger, and the debugger receives the dynamic configuration file from the test host.
The test host sends the dynamic configuration file to the debugger after acquiring the dynamic configuration file, and can divide the dynamic configuration file into a plurality of data frames, wherein each data frame comprises a frame header and a frame header, and the frame header comprises a frame number, a total frame number and a check bit. The total frame number represents the number of a plurality of data frames into which the dynamic configuration file is divided; the check bits are used to check the integrity of the data frame, for example: the check bit is a cyclic check code; the frame number indicates the number of the data frame, and the frame number may be numbered from 1 and incremented by 1.
S210, the debugger sends a transmission success response to the test host, and the test host receives the transmission success response from the debugger.
When the debugger successfully receives the dynamic configuration file from the test host, a transmission success response is sent to the test host, and the process of the debugger receiving the dynamic configuration file may be: when the debugger receives a data frame, analyzing a frame header of the data frame to obtain a frame number, a total frame number and a check bit, firstly checking the integrity of the data frame according to the check bit, judging whether the data frame is the last data frame according to the frame number and the total frame number after the check is passed, if the frame number is equal to the total frame number, judging that the data frame is the last data frame of the dynamic configuration file, and sending a transmission success response to the test host by the debugger; and if the data frame is not the last data frame, continuing to wait for receiving the next data frame.
And S211, loading the dynamic configuration file for configuration.
And the debugger loads the dynamic configuration file to configure the difference function.
S212, executing a debugging process.
The test host sends a debugging instruction and data to the debugger, the debugger calls the dynamic configuration file, the target chip is debugged based on the debugging instruction and the data, and the debugging instruction is used for executing an execution program downloading function and an online debugging function. The Program download functions include a full Erase (CHIP Erase), a Sector Erase (Sector Erase), a Program download (Code Program), and a Program Verify (Code Verify). The online debugging function includes Run (Run), Stop (Stop), single Step (Step), Set Breakpoint (Set Breakpoint), Read Memory (Read Memory), program Memory (Write Memory), and the like. When the debugging process is executed, the debugger returns the debugging result to the test host, and the test host displays the debugging result.
The beneficial effect of this application includes: when the target chip is debugged, the debugger loads the fixed configuration file for configuration, receives the dynamic configuration file from the test host according to the fixed configuration file, the dynamic configuration file is obtained by the test host according to the model of the target chip, and the debugger configures the debugging function of the target chip according to the dynamic configuration file so as to debug the target chip. Because chips of different models have difference in function design, the dynamic configuration file is correspondingly adjusted according to the difference, and the flexibility and the expansibility of the debugger can be increased.
The following are embodiments of the apparatus of the present application that may be used to perform embodiments of the method of the present application. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.
Referring to fig. 3, a schematic structural diagram of a debugging apparatus of a chip according to an exemplary embodiment of the present application is shown, which is hereinafter referred to as an apparatus 3 for short. The device 3 may be implemented as all or part of a test host, in software, hardware or a combination of both. The apparatus 3 comprises: a transceiving unit 301, a connection unit 302, an acquisition unit 303 and a debugging unit 304.
A transceiving unit 301 for sending a connection request to a debugger;
a connection unit 302, configured to establish a communication connection with the debugger after receiving a connection success response sent by the debugger;
an obtaining unit 303, configured to determine a chip model of a target chip, and obtain a dynamic configuration file associated with the chip model;
the transceiver unit 301 is further configured to send the dynamic configuration file to the debugger through the communication connection;
and the debugging unit 304 is configured to instruct the debugger to debug the target chip after receiving the transmission success response from the debugger.
In one or more possible embodiments, the determining the chip model of the target chip includes:
displaying a chip model list through a display device;
receiving a selection instruction of a user for the chip model list;
taking the chip model selected by the selection instruction as the chip model of the target chip; or
Sending a chip type number query request to the debugger through the communication connection;
and receiving a chip model inquiry response which is sent by the debugger and carries the chip model of the target chip.
In one or more possible embodiments, the sending the dynamic configuration file to the debugger through the communication connection includes:
partitioning the dynamic configuration file into a plurality of data frames;
sequentially sending the plurality of data frames to the debugger through the communication connection; the data frame comprises a frame head and a frame body, wherein the frame head comprises a frame sequence number, a total frame number and a check bit.
In one or more possible embodiments, the instructing the debugger to debug the target chip includes:
sending a debugging instruction to the debugger; the debugging instruction instructs the debugger to call the dynamic configuration file to debug the target chip and send a debugging result to a test host;
and receiving a debugging result from the debugger and displaying the debugging result through a display device.
In one or more possible embodiments, communication between the test host and the debugger is based on a USB protocol.
In one or more possible embodiments, the connection unit is further configured to:
starting a timer after sending the connection request;
and if the connection success response from the debugger is not received within the preset time length, displaying a connection failure message.
It should be noted that, when the device 3 provided in the foregoing embodiment executes the debugging method of the chip, only the division of the functional modules is illustrated, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the apparatus is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the chip debugging device and the chip debugging method provided by the above embodiments belong to the same concept, and details of implementation processes thereof are referred to in the method embodiments and are not described herein again.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
An embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, where the instructions are suitable for being loaded by a processor and executing the method steps in the embodiment shown in fig. 2, and a specific execution process may refer to a specific description of the embodiment shown in fig. 2, which is not described herein again.
The present application further provides a computer program product, which stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the debugging method of the chip according to the above embodiments.
Fig. 4 is a schematic structural diagram of a test host according to an embodiment of the present disclosure. As shown in fig. 4, the test host 400 may include: at least one processor 401, at least one network interface 404, a user interface 403, memory 405, at least one communication bus 402.
Wherein a communication bus 402 is used to enable connective communication between these components.
The user interface 403 may include a Display screen (Display) and a Camera (Camera), and the optional user interface 403 may also include a standard wired interface and a wireless interface.
The network interface 404 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.
The Memory 405 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 405 includes a non-transitory computer-readable medium. The memory 405 may be used to store instructions, programs, code sets, or instruction sets. The memory 405 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, and the like; the storage data area may store data and the like referred to in the above respective method embodiments. The memory 405 may alternatively be at least one storage device located remotely from the aforementioned processor 401. As shown in fig. 4, the memory 405, which is a type of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and an application program.
In the test host 400 shown in fig. 4, the user interface 403 is mainly used as an interface for providing input for a user, and acquiring data input by the user; the processor 401 may be configured to call the application program stored in the memory 405 and specifically execute the method shown in fig. 2, and the specific process may refer to fig. 2 and is not described herein again.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory or a random access memory.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and is not to be construed as limiting the scope of the present application, so that the present application is not limited thereto, and all equivalent variations and modifications can be made to the present application.
Claims (10)
1. A method for debugging a chip, comprising:
sending a connection request to a debugger;
after receiving a connection success response sent by the debugger, establishing communication connection with the debugger;
determining a chip model of a target chip, and acquiring a dynamic configuration file associated with the chip model;
sending the dynamic configuration file to the debugger through the communication connection;
and after receiving a transmission success response from the debugger, indicating the debugger to debug the target chip.
2. The method of claim 1, wherein determining the chip model of the target chip comprises:
displaying a chip model list through a display device;
receiving a selection instruction of a user for the chip model list;
taking the chip model selected by the selection instruction as the chip model of the target chip; or
Sending a chip type number query request to the debugger through the communication connection;
and receiving a chip model inquiry response which is sent by the debugger and carries the chip model of the target chip.
3. The method of claim 1 or 2, wherein sending the dynamic configuration file to the debugger through the communication connection comprises:
partitioning the dynamic configuration file into a plurality of data frames;
sequentially sending the plurality of data frames to the debugger through the communication connection; the data frame comprises a frame head and a frame body, wherein the frame head comprises a frame sequence number, a total frame number and a check bit.
4. The method of claim 3, wherein the instructing the debugger to debug the target chip comprises:
sending a debugging instruction to the debugger; the debugging instruction instructs the debugger to call the dynamic configuration file to debug the target chip and send a debugging result to a test host;
and receiving a debugging result from the debugger and displaying the debugging result through a display device.
5. The method of claim 1, 2 or 4, wherein the communication between the test host and the debugger is based on a USB protocol.
6. The method of claim 5, further comprising:
starting a timer after sending the connection request;
and if the connection success response from the debugger is not received within the preset time length, displaying a connection failure message.
7. A debugging device of a chip is characterized by comprising:
a receiving and transmitting unit for sending a connection request to a debugger;
the connection unit is used for establishing communication connection with the debugger after receiving a connection success response sent by the debugger;
the system comprises an acquisition unit, a storage unit and a processing unit, wherein the acquisition unit is used for determining the chip model of a target chip and acquiring a dynamic configuration file associated with the chip model;
the transceiver unit is further configured to send the dynamic configuration file to the debugger through the communication connection;
and the debugging unit is used for indicating the debugger to debug the target chip after receiving the transmission success response from the debugger.
8. A computer storage medium, characterized in that it stores a plurality of instructions adapted to be loaded by a processor and to perform the method steps according to any of claims 1 to 6.
9. A test host, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1 to 6.
10. A chip debug system, comprising: testing a host, a debugger and a target chip;
the test host is used for sending a connection request to the debugger; after receiving a connection success response sent by the debugger, establishing communication connection with the debugger; determining the chip model of the target chip, and acquiring a dynamic configuration file associated with the chip model; sending the dynamic configuration file to the debugger through the communication connection; after receiving a transmission success response from the debugger, indicating the debugger to debug the target chip;
the debugger is used for acquiring a fixed configuration file for configuration after the power-on is successful; after configuration is successful, receiving a connection request from the test host; after the connection request passes the authentication, sending a connection success response to the test host; receiving a dynamic configuration file from the test host; configuring according to the dynamic configuration file; after the configuration is successful, sending a transmission success response to the test host; and receiving a debugging instruction from a test host, and calling the dynamic configuration file to debug the target chip based on the debugging instruction.
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| CN116401114B (en) * | 2023-06-08 | 2024-06-07 | 北京华电众信技术股份有限公司 | Mainboard debugging system, method and device, storage medium and computer equipment |
| CN117234951A (en) * | 2023-11-13 | 2023-12-15 | 建信金融科技有限责任公司 | Function test method and device of application system, computer equipment and storage medium |
| CN117520082A (en) * | 2024-01-08 | 2024-02-06 | 凌思微电子(杭州)有限公司 | Chip debugging method and device and electronic equipment |
| CN117520082B (en) * | 2024-01-08 | 2024-04-02 | 凌思微电子(杭州)有限公司 | Chip debugging method and device and electronic equipment |
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