CN116381452A

CN116381452A - Chip testing method, device and system and readable storage medium

Info

Publication number: CN116381452A
Application number: CN202310259352.8A
Authority: CN
Inventors: 陈戈; 张健; 张传美
Original assignee: Hangzhou Lingce Technology Co ltd
Current assignee: Hangzhou Lingce Technology Co ltd
Priority date: 2022-12-08
Filing date: 2023-03-13
Publication date: 2023-07-04
Anticipated expiration: 2043-03-13
Also published as: CN116381452B

Abstract

The invention discloses a chip testing method, a device, a system and a readable storage medium, wherein the chip testing method comprises the steps of detecting the chip placement condition of each testing station in a sorting machine; if the target test station where the chip placement is finished is detected, sending a station identifier of the target test station to a testing machine, so that the testing machine tests the target chip placed at the target test station according to the station identifier; receiving a test response message returned by the tester, wherein the test response message comprises a category identifier obtained after testing the target chip; and sending a sorting control signal to the sorting machine according to the category identification so as to control the sorting machine to sort the target chips into the chip categories represented by the category identification. The reliability is high.

Description

Chip testing method, device and system and readable storage medium

Technical Field

The present invention relates to the field of integrated circuit testing, and in particular, to a method, apparatus, system and readable storage medium for testing a chip.

Background

Before the chip leaves the factory, the chip needs to be tested to judge whether the chip has defects, faults or failures and the like. When the chip is tested, the chip to be tested is placed at a test station, and then a test signal is sent to the chip by a tester so as to test the chip.

Currently, in chip testing, a mode (also called a multi-Site mode) in which multiple testing stations perform chip testing simultaneously is generally adopted. In the mode, a plurality of chips can be tested at the same time, and the testing efficiency of the chips is improved. However, as the number of test stations increases, the connection between the tester and the test stations is more and more complex, and the problem of chip test errors caused by connection errors often occurs.

Disclosure of Invention

In view of this, the embodiments of the present invention provide a chip testing method, a chip testing system, a chip testing device, and a computer readable storage medium, which can reduce the error rate of chip testing and have high reliability.

In one aspect, the present invention provides a chip testing method, including:

detecting the chip placement condition of each test station in the sorting machine;

if a target test station where the chip placement is finished is detected, sending a station identifier of the target test station to a testing machine, so that the testing machine tests the target chip placed at the target test station according to the station identifier;

receiving a test response message returned by the tester, wherein the test response message comprises a category identifier obtained after the target chip is tested; a kind of electronic device with high-pressure air-conditioning system

And sending a sorting control signal to the sorting machine according to the category identification so as to control the sorting machine to sort the target chips into chip categories represented by the category identification.

In some embodiments, when sending the station identification of the target test station to a tester, the method further comprises:

and sending a test starting identifier to the testing machine so that the testing machine starts the test of the target chip when receiving the test starting identifier.

In some embodiments, the sending the test initiation identification and the station identification of the target test station to the tester includes:

in a message sent to the tester, transmitting the station identifier of the target test station using one or more first data bits, and transmitting the test initiation identifier using one or more second data bits, so that the tester tests the target chip according to the identifiers transmitted by the first data bits and the second data bits.

In some embodiments, the test response message includes a test end identification;

and sending a sorting control signal to the sorting machine according to the category identification, wherein the sorting control signal comprises the following components:

and under the condition that the test ending identification is received, sending a sorting control signal to the sorting machine according to the category identification.

In some embodiments, the sorter includes a plurality of communication ports, different test stations correspond to different communication ports, and the test response message further includes a station identifier of a test station where the target chip is located;

determining a target communication port corresponding to the target chip based on the station identifier in the test response message;

and sending a sorting control signal to the sorting machine through the target communication port according to the category identification.

In some embodiments, after receiving the test response message, the method further comprises:

analyzing from one or more first appointed data bits of the test response message to obtain a station identifier of a target test station, and analyzing from one or more second appointed data bits of the test response message to obtain a category identifier of a target chip, so that the sorting control signal is sent to the sorting machine based on the station identifier and the category identifier obtained by analysis.

In some embodiments, various identifications are transmitted based on the following method:

representing an identity to be transmitted using different combinations of values of the plurality of data bits; and/or

At least some of the identifiers are in one-to-one correspondence with data bits used to transmit the identifiers, each data bit being used to transmit the corresponding identifier.

The invention also provides a chip testing system, which comprises a sorting machine, a testing machine and a sorting control module, wherein the sorting machine comprises a testing station; wherein, the liquid crystal display device comprises a liquid crystal display device,

in some embodiments, the sorting control module is specifically configured to send a test start identifier to the testing machine when sending the station identifier of the target test station to the testing machine, so that the testing machine starts testing the target chip when receiving the test start identifier.

In some embodiments, the sorting control module is specifically configured to transmit the station identifier of the target test station using one or more first data bits and transmit the test initiation identifier using one or more second data bits in a message sent to the tester, so that the tester tests the target chip according to the identifiers transmitted by the first data bits and the second data bits.

In some embodiments, the test response message includes a test end identification; the sorting control module is specifically used for sending a sorting control signal to the sorting machine according to the category identification under the condition that the test ending identification is received.

the sorting control module is specifically configured to determine a target communication port corresponding to the target chip based on the station identifier in the test response message, and send a sorting control signal to the sorting machine through the target communication port according to the category identifier.

In some embodiments, the sorting control module is further configured to parse the test response message from one or more first specified data bits of the test response message to obtain a station identifier of the target test station, and parse the test response message from one or more second specified data bits of the test response message to obtain a category identifier of the target chip, so as to send the sorting control signal to the sorting machine based on the parsed station identifier and the category identifier.

The invention also provides a chip testing device, which comprises a processor and a memory, wherein the memory is used for storing a computer program, and the computer program is executed by the processor to realize the method.

In a further aspect the invention provides a computer readable storage medium for storing a computer program which, when executed by a processor, implements a method as described above.

In the technical solutions of some embodiments of the present application, by detecting the chip placement condition of each test station in the sorting machine, the station identifier corresponding to the target test station where the chip placement is completed is sent to the testing machine, so that the testing machine tests the target chip of the target test station according to the station identifier, and feeds back a test response message. By sending the station identification, the target test station which needs to be subjected to chip test is informed to the tester, so that the target test station can be detected without a one-to-one hardware connection mode between the tester and the sorting machine, the problem of connection errors between the tester and the sorting machine is reduced, the error rate of chip test can be reduced, and the reliability of test is improved.

Drawings

The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and should not be construed as limiting the invention in any way, in which:

FIG. 1 shows a schematic diagram of a chip testing apparatus in some techniques;

FIG. 2 is a schematic diagram showing the chip test apparatus of FIG. 1 when a wiring fault occurs;

FIG. 3 shows a schematic diagram of a chip testing system provided by an embodiment of the present application;

FIG. 4 is a flow chart of a method for testing a chip according to an embodiment of the present application;

FIG. 5 illustrates a schematic transmission of station identification provided by one embodiment of the present application;

FIG. 6 illustrates a transmission schematic of a station identifier provided in another embodiment of the present application;

FIG. 7 shows a schematic diagram of a test response message provided by an embodiment of the present application;

FIG. 8 illustrates a transmission schematic of a station identifier and a test initiation identifier provided by an embodiment of the present application;

FIG. 9 is a schematic diagram illustrating information interaction between a sort control module and a tester provided by one embodiment of the present application;

FIG. 10 illustrates a timing diagram of information interaction between a sort control module and a tester provided by one embodiment of the present application;

fig. 11 shows a schematic structural diagram of a chip testing device according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, based on the embodiments of the invention, which a person skilled in the art would obtain without making any inventive effort, are within the scope of the invention.

Referring to fig. 1, a schematic diagram of a chip testing apparatus 100 in some technologies is shown. In fig. 1, a chip testing apparatus 100 includes a sorter 11, a tester 12, a test strip 13, and a sorting signal strip 14. Wherein the sorter 11 comprises a plurality of test stations 111 and communication ports 112. Different test stations 111 correspond to different communication ports 112. Tester 12 includes a plurality of test stations 121. The

test stations

111 and 121 are connected in one-to-one correspondence by the test flat cable 13. The communication ports 112 are connected to the test stations 121 in one-to-one correspondence via the sorting signal flat cables 14. Each test station 111 may be used to place one chip. Taking fig. 1 as an example, a sorter 11 may be used to place 4 chips. Each test station 121 may be used to test a chip on a connected test station 111. The test station 111 and the communication port 112 connected to the same test station 121 need to correspond. For example, assume that test station 1 corresponds to communication port 1. If test station a is connected to test station 1, then test station a needs to be simultaneously connected to communication port 1.

The sorter 11 may also include a robot arm (not shown). The robot arm may communicate with the test station 121 through the communication port 112. The robot arm may automatically place the chip into the test station 111 during the chip inspection, and automatically remove the chip from the test station 111 after the chip inspection is completed. For ease of understanding, the following describes the detection process of one chip by way of example.

Assuming that the manipulator has placed a chip in the test station 1, a message may be sent to the test station a via the communication port 1 corresponding to the test station 1. After receiving the message, the test station a may send a test signal to the chip on the test station 1 to perform a chip test. After the chip test is completed, the test station a may generate a test result of the chip. The test result may be used to characterize the class (e.g., good, bad) to which the chip belongs. The test station a may feed back the test results to the manipulator via the communication port 1. Because the communication port 1 corresponds to the test station 1, after the test result is received by the manipulator, the chip on the test station 1 is taken down from the test station 1 and placed into the category to which the chip belongs. For example, if the test station a detects that the chip belongs to the good, the chip is placed in the chip of the good class.

In the chip testing apparatus 100 shown in fig. 1, a line connection error often occurs due to the number of the testing stations 111, the testing stations 121, and the communication ports 112. Referring to fig. 2 in combination, a schematic diagram of the chip testing apparatus 100 in fig. 1 when a wiring error occurs is shown. In fig. 2, it is assumed that the communication port 3 corresponds to the test station 3 and the communication port 4 corresponds to the test station 4, and the test station C connects the communication port 3 and the test station D connects the communication port 4 and the test station 4, under the correct wiring. Taking test station 3 as an example. Normally, after the manipulator places the chip on the test station 3, a message is sent to the test station C via the communication port 3. After receiving the message, the testing station C tests the chip on the testing station 3, and feeds back the test result to the manipulator through the communication port 3, so that the manipulator takes down the chip on the testing station 3.

However, due to the line connection error, the test station C is actually connected to the communication port 4, and the test station D is connected to the communication port 3. After the manipulator places the chip in the test station 3, a message is actually sent to the test station D via the communication port 3. After receiving the message, the testing station D tests the chip on the testing station 4 and feeds back the test result to the manipulator through the communication port 3. Since the manipulator is the test result received from the communication port 3, the chip on the test station 3 will be placed into the chip category characterized by the test result. It can be seen here that the actual test is of the chip on the test station 4, and the result is the chip type to which the chip on the test station 4 belongs. However, due to the wrong connection of the lines, the manipulator may erroneously remove the chip from the test station 3, which may lead to an accident in the chip test. For example, if the chip of the test station 4 is a qualified chip, but the chip of the test station 3 is a failed chip, under the condition of line connection error, the failed chip of the test station 3 is placed into a qualified chip category, so as to cause chip test accidents.

Generally, since the test station 111 and the test station 121 are located in the same plane (e.g., both are located on the upper surface of the device), there is less chance of a line connection error between the test station 111 and the test station 121. The communication port 112 is located on the side of the sorting machine 11 and is not located on the same plane as the test station 121, so that the probability of line connection error between the communication port 112 and the test station 121 is high. For this reason, in solving the problem of the line connection error of the chip test apparatus 100, the problem of the line connection error between the communication port 112 and the test station 121 may be emphasized.

In view of this, the present application provides a chip testing method, which can reduce the problem of line connection errors between the communication port 112 and the testing station 121, and further can reduce the error rate of chip testing, and improve the reliability of chip testing. Before describing the chip testing method of the present application, a chip testing system 200 provided in the present application is first described.

Referring to fig. 3 in combination, a schematic diagram of a chip testing system 200 according to an embodiment of the present application is provided. In fig. 3, the chip test system 200 includes a sorter 21, a tester 22, a test strip 23, a sort signal line 24, and a sort control module 25. The sorter 21 includes a plurality of test stations 211 and communication ports 212. Tester 22 includes a plurality of test stations 221.

The chip test system 200 in fig. 3 is substantially similar to the chip test system 100 in fig. 1, with the main differences: in fig. 3, a plurality of test stations 221 are connected to the communication port 212 through a sorting control module 25. Wherein, a plurality of test stations 221 are connected with a sorting control module 25 through a sorting signal line 24. The sorting signal line 24 may be a serial line. Each communication port 212 is connected to the sorting control module 25, respectively. There is a correspondence between the test stations 211 and the communication ports 212. In the corresponding test station 211 and communication port 212, after the test station 221 is connected to the test station 211, the manipulator is communicatively connected through the sorting control module 25 and the communication port 212 corresponding to the test station 211. The sorting control module 25 may be disposed on the sorting machine 21 or disposed at a position closer to the sorting machine 21 to shorten the connection distance between each communication port 212 and the sorting control module 25, and reduce the problem of connection errors between the communication ports 212 and the sorting control module 25.

Referring to fig. 4, a flow chart of a chip testing method according to an embodiment of the present application is shown based on the chip testing system 200 shown in fig. 3. The chip test method can be applied to the sort control module 25 in fig. 3. In fig. 4, the chip testing method includes the following steps:

in step S41, the chip placement condition of each test station 211 in the sorting machine 21 is detected.

In some embodiments, the sorting control module 25 may communicate with the robots in the sorters 21 through respective communication ports 212. When the manipulator places the chips at each test station 211, the manipulator may send a first signal to the sorting control module 25 through the communication port 212 corresponding to the test station 211. Accordingly, when the manipulator removes the chip at each test station 211, the manipulator may send a second signal to the sorting control module 25 through the communication port 212 corresponding to the test station 211. Wherein the first signal and the second signal may be different. In this way, the sorting control module 25 can determine the chip placement of each test station 211 by detecting the signals at each communication port 212.

Taking test station 1 and test station 2 in fig. 3 as an example. Assume that test station 1 corresponds to communication port 1 and test station 2 corresponds to communication port 2. After the manipulator has placed the chip at the test station 1, a first signal may be sent to the sorting control module 25 via the communication port 1. The sorting control module 25 may determine that the chip of the test station 1 has been placed when the communication port 1 detects the first signal. Accordingly, after the manipulator removes the chip at the test station 2, a second signal may be sent to the sorting control module 25 through the communication port 2. The sorting control module 25 may determine that the chip of the test station 2 has been removed when the communication port 2 detects the second signal.

In step S42, if the target test station 211 with the chip placement completed is detected, the station identifier of the target test station 211 is sent to the testing machine 22, so that the testing machine 22 tests the target chip placed at the target test station 211 according to the station identifier.

Specifically, each test station 211 may correspond to a station identifier. The station identification of the different test stations 211 is different.

In this embodiment, the correspondence between the test stations 211 and the station identifiers may be set in the sorting control module 25 in advance. When the sorting control module 25 detects the target test station 211 with the chip placed, according to the preset corresponding relation between the test station 211 and the station identifier, the station identifier corresponding to the target test station 211 is searched, and the searched station identifier is sent to the testing machine 22 in a serial port communication mode through the sorting signal line 24.

One or more first data bits may be used to transmit the station identification of the target test station 211 in a message sent to the tester 22. One data bit is one bit. In this embodiment, when the station identifier is transmitted, different numerical combinations of a plurality of data bits may be used to represent the station identifier to be transmitted. Wherein the value of each data bit may be 0 or 1.

For ease of understanding, referring to fig. 5 in combination, a schematic diagram of the transmission of station identifiers is provided for one embodiment of the present application. Fig. 5 illustrates, by way of example, 8 data bits (i.e., one byte) sent by the sort control module 25 to the tester 22. Of these 8 data bits, different numerical combinations of the first four data bits may be used to represent the station identification of the different test stations 211. For example, 0001 is used to represent the station identifier of the first test station 211, 0010 is used to represent the station identifier of the second test station 211, and 0011 is used to represent the station identifier of the third test station 211. After detecting the target test station 211 where the chip placement is completed, the numerical combination of the data bits may be set as the station identifier corresponding to the target test station 211, so as to transmit the station identifier of the target test station 211 to the tester 22.

In other embodiments, at least some of the station identifiers are in one-to-one correspondence with data bits used to transmit the station identifiers, each data bit being used to transmit the corresponding station identifier. Specifically, the data bits may correspond one-to-one to the station identifications. The different values of each data bit are used for indicating whether the corresponding station identifier is transmitted or not.

For ease of understanding, referring to fig. 6 in combination, a schematic diagram of the transmission of station identifiers is provided for another embodiment of the present application. In fig. 6, two test stations 211 are illustrated. It is assumed that the first data bit corresponds to test station 1 and the second data bit corresponds to test station 2 from the right. The first data bit has a first value (e.g., 1) indicating that the station identifier of the test station 1 is transmitted, and the first data bit has a second value (e.g., 0) indicating that the station identifier of the test station 1 is not transmitted. Similarly, when the second data bit has a first value, the station identifier of the test station 2 is transmitted, and when the second data bit has a second value, the station identifier of the test station 2 is not transmitted currently. In short, after detecting the target test station 211 where the placement of the chip is completed, the data bit corresponding to the target test station 211 is set to the first value, so as to transmit the station identifier of the target test station 211.

Accordingly, on the tester 22 side, the station identification of the connected test stations 211 can be preset at the respective test stations 221. For example, if the test station a is connected to the test station 1, the station identifier of the test station 1 is set in the test station a in advance. It will be appreciated that the station identification provided at the different test stations 221 is different due to the different test stations 211 to which the different test stations 221 are connected. After the tester 22 receives the messages sent by the sorting control module 25, each test station 221 may parse the messages separately. If the station identifier obtained by analysis is the same as the station identifier locally set by the test station 221, the target chip on the connected test station 211 is tested.

For example. Assume that test station a is connected to test station 1, and that test station 1 corresponds to communication port 1. During chip testing, after the manipulator places the chips at the testing station 1, a message is sent to the sorting control module 25 through the communication port 1. The sorting control module 25 sends the station identification of the test station 1 to the tester 22. Each test station 221 in tester 22 may parse the message separately. At this time, only the station identifier analyzed by the test station A is the same as the station identifier stored locally. Then test station a tests the target chip on the connected test station 1.

The process of testing the target chip by the test station 221 is a technology that should be known to those skilled in the art, and will not be described in detail herein.

In step S43, a test response message returned by the tester 22 is received, where the test response message includes a category identifier obtained after testing the target chip.

In some embodiments, the class identification characterizes a quality class of the target chip. Such as good, bad, and unqualified products. Different quality levels are represented using different category identifications. For example, 1 indicates a good product, and 2 indicates a good product.

Similar to the transmission of the station identification, tester 22 may also transmit the class identification of the target chip via one or more data bits. The related transmission principle can be referred to as the transmission principle of the station identifier, and will not be described herein.

Step S44, according to the category identification, a sorting control signal is sent to the sorting machine 21 to control the sorting machine 21 to sort the target chips into the chip categories characterized by the category identification.

In some embodiments, different class identifications characterize different chip classes. Different chip types correspond to different sorting control signals. For example, the superior chip corresponds to the first control signal; the good chip corresponds to the second control signal. The manipulator in the sorter 21 may analyze the sorting control signal and sort the target chips into the chip categories characterized by the category identification according to the analysis result.

Specifically, the sorting control module 25 may determine, according to the target test station 211 where the target chip is located, a communication port 212 corresponding to the target test station 211, and send a sorting control signal through the communication port 212. The manipulator determines a target chip to be sorted according to the communication port for transmitting the sorting control signal, and determines the chip type to which the target chip belongs according to the received sorting control signal. For example, assuming that the test station 1 corresponds to the communication port 1, the sorting control signal is a first control signal, and the target chip is located at the test station 1. Then a sorting control signal may be sent to the sorting machine 21 through the communication port 1 corresponding to the test station 1, so as to control the manipulator to sort the target chips on the test station 1 into the chip categories represented by the first control signal.

In the technical solutions of some embodiments of the present application, by detecting the chip placement condition of each test station 211 in the sorting machine 21, the station identifier corresponding to the target test station 211 where the chip placement is completed is sent to the testing machine 22, so that the testing machine 22 tests the target chip of the target test station 211 according to the station identifier, and feeds back a test response message. By sending the station identification, the target test station 211 which needs to be subjected to chip test is informed to the tester 22, so that the target test station 211 can be detected without a one-to-one hardware connection mode between the tester 22 and the sorting machine 21, the problem of connection errors between the tester 22 and the sorting machine 21 is reduced, the error rate of chip test can be reduced, and the reliability of test is improved.

The chip testing method of the present application is further described below.

Based on the above description of fig. 1 to 3, it may be known that each test station 211 has a corresponding communication port, and in order to facilitate the determination of the communication port to which the sorting control signal is to be sent by the sorting control module 25, in some embodiments, the test response message may further include a station identifier of the test station 211 where the target chip is located. The above-mentioned sending of the sorting control signal to the sorting machine 21 according to the category identification includes:

the sorting control signal is sent to the sorting machine 21 through the target communication port according to the category identification.

In this way, the sorting control module 25 can determine the communication port to which the sorting control signal is to be sent according to the station identifier, thereby improving the feasibility of the scheme.

In some embodiments, after receiving the test response message, the sorting control module 25 may parse the station identifier of the target test station 211 from one or more first specified data bits of the test response message and parse the class identifier of the target chip from one or more second specified data bits of the test response message, so as to send a sorting control signal to the sorter 21 based on the parsed station identifier and class identifier.

The first designated data bit and the second designated data bit may be data bits agreed by the tester 22 and the sorting control module 25 for transmitting the station identifier and the category identifier. For ease of understanding, referring to fig. 7 in combination, a schematic diagram of a test response message is provided for one embodiment of the present application. In fig. 7, the first 4 data bits from the right are used for exemplary transmission station identification, and the 5 th to 7 th data bits from the right are used for transmission category identification. The first 4 data bits are the first designated data bits and the 5 th to 7 th data bits are the second designated data bits.

In some embodiments, when the station identifier of the target test station 211 is sent to the tester 22, a test initiation identifier may also be sent to the tester 22, so that the tester 22 initiates testing of the target chip when receiving the test initiation identifier. Specifically, the test initiation identifier is used to characterize initiation of testing of the target chip. After detecting that the target chip has been placed at the target test station 211, the sorting control module 25 may send a test start identifier to the tester 22, so that the tester 22 starts a test on the target chip when receiving the test start identifier. In this manner, the tester 22 may be prevented from initiating testing of the target chip when the target chip has not been fully placed at the test station 211. The reliability of the chip test can be improved.

In some embodiments, the test response message may include an end of test identification. The above-mentioned sending of the sorting control signal to the sorting machine 21 according to the category identification includes:

upon receiving the test end flag, a sorting control signal is sent to the sorting machine 21 according to the category flag. Specifically, the test ending identifier is used for representing ending the test on the target chip. After the test machine 22 tests the target chip, a test end identifier may be sent to the sorting control module 25, so that the sorting control module 25 may determine that the test for the target chip is completed according to the test end identifier, and may send a sorting control signal to the sorting machine 21 to sort the target chip. In this way, it is prevented that the sorting control module 25 starts sending the sorting control signal to the sorting machine 21 when the target chip is not tested, so that the target chip is sorted in case of not being tested. The reliability of the chip test can be improved.

In some embodiments, the sort control module 25 may also transmit the test initiation identification via one or more data bits, similar to the transmission of the station identification. Specifically, in the message sent to the tester 22, one or more second data bits may be used to transmit a test initiation flag, so that the tester tests the target chip according to the first data bit and the flag transmitted by the second data bit.

For ease of understanding, reference may be made to fig. 8 for a schematic transmission of station identification and test initiation identification provided for one embodiment of the present application. In fig. 8, the station identification is transmitted using four data bits from the right side, and the test initiation identification is transmitted using two data bits from the left side. The transmission principle of the test start identifier is similar to that of the station identifier, and will not be described in detail herein. In this embodiment, the first data bit from the left is used as the test start flag, and when the data bit takes a first start value (for example, 1), it indicates that the test needs to be started. Conversely, when the first data bit from the left side assumes a second start value (e.g., 0), it indicates that the start of the test is not required.

Similarly, in the test response message, the test end identifier may also be transmitted using one or more third data bits, and the principle is similar to the test start identifier, which is not described herein.

For ease of understanding, please refer to fig. 9 and 10. Fig. 9 is a schematic diagram illustrating information interaction between the sorting control module 25 and the tester 22 according to an embodiment of the present application. Fig. 10 is a timing diagram of information interaction between sorting control module 25 and tester 22 according to one embodiment of the present application.

In fig. 9, the sorting control module 25 is provided with a sorting chip. The sorting chip communicates with the tester 22 according to the SPI (Serial Peripheral Interface ) protocol. The tester 22 is a master device in the SPI protocol, and the sorting chip is a slave device in the SPI protocol. The tester 22 provides a clock signal (which may be used for timing) to the sorting chips via the CLK signal line, and an enable signal (which may be used to control the sorting chips to start or stop operation) to the sorting chips via the CS signal line. The clock signal and the enable signal are conventional technical means that should be known to one skilled in the art and are not described in detail herein.

After detecting the target test station 211 where the chip placement is completed, the sorting control module 25 sends a first message to the tester 22 through the MISO signal line to send a test start identifier and a station identifier of the target test station 211 to the tester 22. The tester 22 sends a second message to the sort control module 25 via the MOSI signal line to send the test results to the sort control module 25. The content formats and transmission timings of the first and second messages may be as shown in fig. 10.

In fig. 10, the content format of the first message may be: the first four data bits from the right may transmit a station identification, the first data bit from the left may transmit a start identification (value 1 valid), and the second data bit from the left may transmit a completion identification (value 1 valid). The content format of the second message may be: the first four data bits from the right side may transmit the station identification and the first four data bits from the left side may transmit the class identification of the target chip.

As can be seen in fig. 10, the first message sent by sort control module 25 to tester 22 is "10000001" indicating that testing is initiated on the target chip at target test station "0001". The second message returned by test 22 is "00010001", indicating that the category identification of the target chip on the target test station "0001" is "0001". After the die at target test station 211 is removed, sort control module 25 sends a first message to tester 22 of "01000001" indicating that the test is complete on the target die at target test station "0001".

In summary, in the chip testing system 200 provided in the present application, the sorting control module 25 is configured to detect a chip placement condition of each testing station 211 in the sorting machine 21, and send a station identifier of the target testing station 211 to the testing machine 22 when detecting the target testing station 211 where the chip placement is completed;

the testing machine 22 is configured to test a target chip placed at the target testing station 211 according to the station identifier, and return a test response message to the sorting control module 25, where the test response message includes a category identifier obtained after the target chip is tested;

the sorting control module 25 is further configured to receive a test response message returned by the tester 22, and send a sorting control signal to the sorter 21 according to the category identifier in the test response message;

the sorter 21 is configured to sort the target chips into chip categories characterized by category identifiers based on the sorting control signals.

Fig. 11 is a schematic structural diagram of a chip testing device according to an embodiment of the present application. The chip testing device comprises a processor and a memory, wherein the memory is used for storing a computer program, and the chip testing method is realized when the computer program is executed by the processor.

The processor may be a central processing unit (Central Processing Unit, CPU). The processor may also be any other general purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof.

The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as program instructions/modules, corresponding to the methods in embodiments of the present invention. The processor executes various functional applications of the processor and data processing, i.e., implements the methods of the method embodiments described above, by running non-transitory software programs, instructions, and modules stored in memory.

The memory may include a memory program area and a memory data area, wherein the memory program area may store an operating system, at least one application program required for a function; the storage data area may store data created by the processor, etc. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some implementations, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

An embodiment of the present application further provides a computer readable storage medium, where the computer readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the chip testing method is implemented.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. A method of testing a chip, the method comprising:

2. The method of claim 1, wherein upon sending the station identification of the target test station to a tester, the method further comprises:

3. The method of claim 2, wherein said transmitting a test initiation flag and said station flag of said target test station to said tester comprises:

4. The method of claim 1, wherein the test response message includes a test end identification;

5. The method of claim 1, wherein the sorter includes a plurality of communication ports, different test stations corresponding to different communication ports, the test response message further including a station identification of a test station in which the target chip is located;

6. The method of claim 5, wherein after receiving the test response message, the method further comprises:

7. The method according to claim 3 or 6, characterized in that the various identities are transmitted based on the following method:

8. The chip testing system is characterized by comprising a sorting machine, a testing machine and a sorting control module, wherein the sorting machine comprises a testing station; wherein, the liquid crystal display device comprises a liquid crystal display device,

the sorting control module is used for detecting the chip placement condition of each test station in the sorting machine, sending the station identification of the target test station to the testing machine when detecting the target test station with the completed chip placement, receiving a test response message returned by the testing machine, and sending a sorting control signal to the sorting machine according to the category identification in the test response message;

the testing machine is used for testing the target chip placed in the target testing station according to the station identifier, and returning a testing response message to the sorting control module, wherein the testing response message comprises a category identifier obtained after the target chip is tested;

the sorting machine is used for sorting the target chips into the chip categories characterized by the category identifiers based on the sorting control signals.

9. The system of claim 8, wherein the sort control module is specifically configured to send a test initiation identifier to the tester when sending the station identifier of the target test station to the tester, such that the tester initiates testing of the target chip when receiving the test initiation identifier.

10. The system of claim 9, wherein the sort control module is specifically configured to transmit the station identification of the target test station using one or more first data bits and transmit the test initiation identification using one or more second data bits in a message sent to the tester to cause the tester to test the target chip based on the first data bits and the second data bit transmitted identifications.

11. The system of claim 8, wherein the test response message includes a test end identification; the sorting control module is specifically used for sending a sorting control signal to the sorting machine according to the category identification under the condition that the test ending identification is received.

12. The system of claim 8, wherein the sorter includes a plurality of communication ports, different test stations corresponding to different communication ports, the test response message further including a station identification of a test station in which the target chip is located;

13. The system of claim 12, wherein the sort control module is further configured to parse a station identification of a target test station from one or more first designated data bits of the test response message and parse a category identification of a target chip from one or more second designated data bits of the test response message after receiving the test response message, so as to send the sort control signal to the sorter based on the parsed station identification and category identification.

14. Chip testing device, characterized in that it comprises a processor and a memory for storing a computer program which, when executed by the processor, implements the method according to any of claims 1 to 7.

15. A computer readable storage medium for storing a computer program which, when executed by a processor, implements the method of any one of claims 1 to 7.