CN113578781A

CN113578781A - Chip sorting method, device, equipment and storage medium

Info

Publication number: CN113578781A
Application number: CN202110842389.4A
Authority: CN
Inventors: 林瑞清
Original assignee: Bitmain Technologies Inc
Current assignee: Bitmain Technologies Inc
Priority date: 2021-07-26
Filing date: 2021-07-26
Publication date: 2021-11-02
Anticipated expiration: 2041-07-26
Also published as: CN113578781B; WO2023005918A1

Abstract

The disclosure provides a chip sorting method, device, equipment and storage medium. The method may include obtaining position information of a current chip in a first feeding tray; determining grouping information of the current chip according to the mapping relation between the position information of the chip to be sorted in the first feeding tray and the grouping information of the chip to be sorted; and placing the current chip into a blanking tray on a first sorting position corresponding to the grouping information of the current chip, wherein the blanking tray is configured to be placed with one or more grouped chips. In this disclosure, the sorter confirms the grouping information of this chip according to the position of each chip on the pay-off tray, and then puts into corresponding unloading tray with this chip, need not to carry out retest to the chip, can accomplish the sorting to the group chip, has improved efficiency of software testing.

Description

Chip sorting method, device, equipment and storage medium

Technical Field

The present disclosure relates to, but not limited to, the field of chip testing, and in particular, to a method, an apparatus, a device, and a storage medium for sorting chips.

Background

In the chip production process, the test is the only link throughout the production and application process. Firstly, the chip design passes the prototype test, otherwise, the chip design cannot be put into mass production; in mass production, if a wafer or a bare chip does not pass a wafer (CP) test (which may also be referred to as an intermediate test), packaging cannot be performed in the next process; the final test (also called a package test or a Final Test (FT)) after packaging is a final process, and only chips that pass the test can be shipped. Therefore, the test becomes an important link for ensuring the product quality and reducing the cost in the chip production process.

Currently, in a finished product test, a sorter and a tester are used in cooperation to perform functional and electrical parameter tests on a packaged chip. However, due to the limited trays of the sorting machine, repeated tests are needed when a large number of chips are sorted, so that the test efficiency is affected, and the test cost is increased.

Disclosure of Invention

The disclosure provides a chip sorting method, a chip sorting device and a storage medium, so that the testing efficiency of chip testing is improved, and the testing cost is saved.

In a first aspect, the present disclosure provides a chip sorting method, which can be applied to a test sorting system. The method can comprise the following steps: obtaining the position information of the current chip in the first feeding tray; determining grouping information of the current chip according to the mapping relation between the position information of the chip to be sorted in the first feeding tray and the grouping information of the chip to be sorted; and placing the current chip into a blanking tray on a first sorting position corresponding to the grouping information of the current chip, wherein the blanking tray is configured to be placed with one or more grouped chips.

In some possible embodiments, the position information of the current chip in the first feeding tray includes: coordinate information of a current chip in a first feeding tray; or the coordinate information of the current chip in the first feeding tray and the tray information of the first feeding tray are used for uniquely identifying the first feeding tray.

In some possible embodiments, before determining the grouping information of the first chip according to the mapping relationship between the position information of the chip to be sorted in the first feeding tray and the grouping information of the chip to be sorted, the method further includes: obtaining grouping information of chips to be sorted; after the chips to be sorted are placed in the first feeding tray, position information of the chips to be sorted in the first feeding tray is obtained; and storing the position information of the chips to be sorted in the first feeding tray in association with the grouping information of the chips to be sorted.

In some possible embodiments, obtaining grouping information of the chips to be sorted includes: performing packaging test on the chips to be sorted to obtain grouping information of the chips to be sorted; or, receiving grouping information of the chips to be sorted from the testing machine.

In some possible embodiments, the placing the current chip into the blanking tray on the first sorting bit corresponding to the grouping information of the current chip includes: judging whether a first sorting position exists in each sorting position corresponding to the first feeding tray or not according to the grouping information of the current chip; if so, putting the current chip into a blanking tray on the first sorting position; after determining whether the first sorting bit exists on each sorting bit according to the grouping information of the current chip, the method further includes: if not, the position information of the next chip in the first feeding tray is obtained.

In some possible embodiments, before obtaining the position information of the current chip in the first feeding tray, the method further includes: obtaining the grouping number of chips to be sorted and the number of sorting positions corresponding to the first feeding tray; determining whether multiple sorting is needed or not according to the number of the groups and the number of the sorting bits; if multiple sorting is needed, the chips to be sorted are at least placed into a first feeding tray and a second feeding tray; if the chips do not need to be sorted for multiple times, placing the chips to be sorted into a first feeding tray; wherein the second feeding tray is different from the first feeding tray.

In some possible embodiments, determining whether multiple sorting is required based on the number of packets and the number of sorting bits includes: judging whether the number of the packets is less than or equal to the number of the sorting bits; if yes, multiple sorting is not needed; if not, the sorting needs to be carried out for multiple times.

In some possible embodiments, when a plurality of grouped chips are placed in the blanking tray at the first sorting location, after the current chip is placed in the blanking tray at the first sorting location corresponding to the grouping information of the current chip, the method further includes: storing the position information of the current chip in the blanking tray on the first sorting position in a correlated manner with the grouping information of the current chip; and taking the blanking tray on the first sorting position as a first feeding tray, and returning to the step of obtaining the position information of the current chip in the first feeding tray. .

In a second aspect, the present disclosure provides a chip sorting apparatus, which may be a chip or a system on a chip in a sorting machine, and may also be a functional module in a sorting device for implementing the method according to any embodiment of the present disclosure. The chip sorting device can realize the functions executed by the sorting machine in any embodiment of the disclosure, and the functions can be realized by executing corresponding software through hardware. The hardware or software comprises one or more modules corresponding to the functions. A chip sorting apparatus comprising: the acquisition module is used for acquiring the position information of the current chip in the first feeding tray; the determining module is used for determining the grouping information of the current chip according to the mapping relation between the position information of the chip to be sorted in the first feeding tray and the grouping information of the chip to be sorted; and the control module is used for placing the current chip into a blanking tray on a first sorting position corresponding to the grouping information of the current chip, wherein the blanking tray is configured to be placed with one or more grouped chips.

In some possible embodiments, the apparatus further comprises: and the identification module is used for identifying the coordinate information of the chips to be sorted in the first feeding tray and/or the tray information of the first feeding tray.

In some possible embodiments, the obtaining module is further configured to obtain grouping information of the chips to be sorted; after the control module puts the chips to be sorted into the first feeding tray, the position information of the chips to be sorted in the first feeding tray is obtained; storing the position information of the chips to be sorted in the first feeding tray and the grouping information of the chips to be sorted in a correlated manner; and the control module is also used for placing the chips to be sorted into the first feeding tray.

In some possible embodiments, the obtaining module is further configured to perform a package test on the chip to be sorted, and obtain grouping information of the chip to be sorted; or, receiving grouping information of the chips to be sorted from the testing machine.

In some possible embodiments, the control module is configured to determine whether a first sorting position exists in each sorting position corresponding to the first feeding tray according to grouping information of a current chip; if so, putting the current chip into a blanking tray on the first sorting position; and the obtaining module is also used for obtaining the position information of the next chip in the first feeding tray if the chip is not positioned in the first feeding tray.

In some possible embodiments, the obtaining module is further configured to obtain the number of groups of chips to be sorted and the number of sorting bits corresponding to the first feeding tray before obtaining the position information of the current chip in the first feeding tray; the determining module is further used for determining whether multiple sorting is needed according to the grouping number and the number of the sorting bits; the control module is also used for placing the chips to be sorted into at least a first feeding tray and a second feeding tray if the chips need to be sorted for multiple times; if the chips do not need to be sorted for multiple times, placing the chips to be sorted into a first feeding tray; wherein the second feeding tray is different from the first feeding tray.

In some possible embodiments, the determining module is further configured to determine whether the number of packets is less than or equal to the number of sorting bits; if yes, multiple sorting is not needed; if not, the sorting needs to be carried out for multiple times.

In some possible embodiments, when a plurality of grouped chips are placed in the blanking tray on the first sorting position, the obtaining module is further configured to store the position information of the current chip in the blanking tray on the first sorting position in association with the grouping information of the current chip after the control module places the current chip in the blanking tray on the first sorting position corresponding to the grouping information of the current chip; and taking the blanking tray on the first sorting position as a first feeding tray, and returning to the step of obtaining the position information of the current chip in the first feeding tray.

In a third aspect, the present disclosure provides a test sorting system comprising: the chip sorting device comprises a feeding tray for placing chips to be sorted, at least one sorting machine and a discharging tray for placing sorted chips; wherein at least one sorter is adapted to perform the chip sorting method according to any one of the first aspect and possible embodiments thereof.

In some possible embodiments, the test sorting system further comprises: the testing machine is used for carrying out packaging testing on the chips to be sorted so as to obtain grouping information of the chips to be sorted.

In a fourth aspect, the present disclosure provides a sorter comprising: a processor, and a memory for storing processor-executable instructions; wherein the processor is configured to: for implementing a chip sorting method as in any one of the first aspect and its possible embodiments when executing executable instructions.

In a fifth aspect, the present disclosure provides a computer-readable storage medium storing an executable program, wherein the executable program, when executed by a processor, implements the chip sorting method according to any one of the first aspect and its possible embodiments.

The technical scheme provided by the disclosure can comprise the following beneficial effects:

in the separation process, the separator can determine the grouping information of the chips according to the positions of the chips on the feeding tray, and then the chips are placed into the corresponding discharging trays, repeated tests are not needed to be carried out on the chips, the separation of the grouped chips can be completed, and the test efficiency is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram of a test sorting system in an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of another test sorting system in an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a sorter in an embodiment of the disclosure;

fig. 4 is a schematic flow chart illustrating an implementation of a chip sorting method according to an embodiment of the disclosure;

FIG. 5 is a schematic flow chart illustrating another chip sorting method according to an embodiment of the disclosure;

FIG. 6 is a schematic flow chart illustrating an implementation of another chip sorting method in an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a chip sorting apparatus according to an embodiment of the disclosure.

Detailed Description

The embodiments of the present disclosure are described below with reference to the drawings in the embodiments of the present disclosure. In the following description, reference is made to the accompanying drawings which form a part hereof and in which is shown by way of illustration specific aspects of embodiments of the disclosure or in which aspects of embodiments of the disclosure may be practiced. It should be understood that the disclosed embodiments may be used in other respects, and may include structural or logical changes not depicted in the drawings. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims. Further, features of the various exemplary embodiments and/or aspects described herein may be combined with each other, unless explicitly stated otherwise.

The terminology used in the embodiments of the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present disclosure. As used in the disclosed embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms "first", "second", "third", etc. may be used in the embodiments of the present disclosure to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, "first information" may also be referred to as "second information," and similarly, "second information" may also be referred to as "first information," without departing from the scope of embodiments of the present disclosure. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

Further, in the description of the embodiments of the present disclosure, "and/or" is only one kind of association relation describing an association object, and means that there may be three kinds of relations. For example, a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present disclosure, "a plurality" may mean two or more than two.

In the chip production process, the test is the only link throughout the production and application process. Firstly, the chip design passes the prototype test, otherwise, the chip design cannot be put into mass production; in mass production, if the wafer or the bare chip does not pass the CP test, the packaging cannot be performed in the next process; FT after packaging (which may also be referred to as FT test) is the final process, and only chips that pass the test can be shipped. Therefore, the test becomes an important link for ensuring the product quality and reducing the cost in the chip production process.

CP testing refers to the functional and electrical parametric testing of bare chips (die) on a wafer (wafer) by the use of a probe station in conjunction with a tester, such as an Automatic Test Equipment (ATE). The test process comprises the following steps: the probe station automatically transfers the wafer to the testing position piece by piece, and the bonding pads (pads) of the chip are connected with the functional modules of the testing machine through the probes and the special connecting wires. The tester applies input signals to the chip and collects output signals, and judges whether the function and performance of the chip meet the design specification requirements. The test result is transmitted to the probe station through the communication interface, and the probe station marks the chip according to the test result to form a wafer map (wafer map).

The FT test refers to a test of functional and electrical parameters of a packaged chip (chip) by using a sorter and a tester in cooperation. The test process comprises the following steps: the sorting machine automatically conveys the tested chips to the testing station one by one, and pins of the tested chips are connected with the functional modules of the testing machine through the base and the special connecting lines on the testing station. The tester applies input signals to the chip and collects output signals, and judges whether the function and performance of the chip meet the design specification requirements. The test result is transmitted to the sorting machine through the communication interface, and the sorting machine marks, sorts, receives or braids the tested chip according to the test result.

In FT, the sorter can output 6 pieces of packet (bin) information at a time, and the sorter catches the chip in an output tray (tray) based on the bin information sent from the tester. It can be seen that the sorter can only sort out a maximum of 6 packets (bins) at a time. Then, if more bins need to be dropped, multiple tests with the tester are required. For example, if 20 bins need to be grouped, 6 bins can be grouped after the first test by the tester, wherein 5 bins are grouped and 1 bin needs to be retested. And 6 bins are separated after the second test of the tester, wherein 5 bins are grouped and completed, and 1 bin needs to be tested again, so that the cycle is repeated. Finally, 20 bins in total require 4 packets to complete. In the process, part of chips need to be tested repeatedly, so that the testing efficiency is influenced, and the testing cost is increased.

To solve this problem, embodiments of the present disclosure provide a chip sorting method, which may be applied to a test sorting system.

Embodiments of the present disclosure provide a test sorting system that may be used to perform FT testing on a chip. The test sorting system may include a testing machine and at least one sorter. The tester is used for testing the packaged chips and sending test results (such as grouping information of the chips) to the sorter. The sorting machine is used for sorting the chips according to the test result. Alternatively, different sorters may sort the chips in multiple stages.

In some possible embodiments, fig. 1 and 2 are schematic diagrams of a test sorting system in an embodiment of the present disclosure, and referring to fig. 1, in a test sorting system 10, a testing machine 11 may be a piece of equipment physically integrated with at least one sorter 12. Alternatively, as shown in fig. 2, in the test sorting system 10, the testing machine 11 may also be physically separated from the sorter 12 into a plurality of pieces of equipment. Alternatively, and still referring to FIG. 2, the testing machine 11 may be integrated with one or more sorters 13 into a single apparatus.

Of course, other configurations of the test sorting system may exist, and this is not particularly limited in this disclosure.

In some possible embodiments, fig. 3 is a schematic structural diagram of a sorting machine in an embodiment of the present disclosure, and referring to fig. 3, the sorting machine 12 may include a robot arm 121, a controller 122, a feeding tray 123, and a discharging tray 124.

It is understood that the mechanical arm 121, the controller 122, the feeding tray 123 and the discharging tray 124 may be one or more, and the embodiment of the disclosure is not particularly limited thereto.

In the embodiment of the present disclosure, the feeding tray 123 is used for placing the chips (i.e., chips to be sorted) tested by the testing machine. The feeding tray may be at least one blanking tray configured on one sorting position of the sorting machine, or may be at least one tray specially used for feeding the sorting machine, which is not specifically limited in this disclosure. In addition, in the sorter 12, there may be a plurality of sets of feed trays, and a set of feed trays may be one or more feed trays. A set of feed trays may feed one or more sort bays.

Further, different groups of feeding trays may belong to the same sorter or to different sorters.

Optionally, the blanking tray 124 is used for placing the sorted chips. One sorting station can be provided with one or more blanking trays. The number of these blanking trays may be no greater than the first value. The first value may be preset, or may be calculated according to the number of groups of chips and the number of sorting bits corresponding to one group of feeding trays, for example, the first value is the number of groups/number of sorting bits and rounded up. In one embodiment, one or more groups of chips may be placed in the blanking tray on one sort location.

It should be noted that, in practical applications, the mapping relationship between the blanking tray and the grouping may be set manually, or may be determined by the sorting machine according to the sorting condition, and this is not particularly limited in the embodiment of the present disclosure.

In some possible embodiments, when the feeding tray is a plurality of trays, each feeding tray may be provided with a tray identifier, such as a two-dimensional code label, a bar code label, a Radio Frequency Identification (RFID), or the like. The sorter may obtain tray information (e.g., the number of each feeding tray) of the feeding tray by scanning or reading the tray identification.

Optionally, when the blanking trays are a plurality of trays, a tray identifier may be provided on each blanking tray, so that the sorter can identify the serial number of each blanking tray. Illustratively, the number of the blanking tray may be represented by grouping information of the chips (i.e., bin number).

In some possible embodiments, one robotic arm 121 may be responsible for sorting work at one or more sorting locations. For example, one mechanical arm 121 may be responsible for sorting chips at 1 sorting site, and may also be responsible for sorting at 6 sorting sites. Further, one robot arm 121 may be controlled by one controller 122, and a plurality of robot arms 121 may be controlled by one controller 122 to sort chips on one or more sorting locations.

Alternatively, the mechanical arm 121 and the controller 122 may be integrated together or may be disposed separately, and the embodiment of the disclosure is not particularly limited. If different mechanical arms are controlled by different controllers, the controllers can communicate with each other in a wireless or wired manner.

It should be noted that the above is merely an example of a test sorting system and a sorter. The test sorting system may have different structures for different implementations of the test sorting system, and this is not particularly limited in the embodiments of the present disclosure.

In an embodiment of the present disclosure, in combination with the structure of the sorting machine, fig. 4 is a schematic implementation flow diagram of a chip sorting method in an embodiment of the present disclosure, and referring to fig. 4, the chip sorting method may include:

s401, the sorting machine obtains the position information of the current chip in the feeding tray A (such as a first feeding tray).

Here, the feeding tray a may be a set of feeding trays, and may include one or more feeding trays.

It should be understood that after the chips are tested by the tester, the chips may be placed into the feeding tray a by the robot arm of the sorter to wait for sorting. Then, the sorter may perform S401 to obtain position information of the current chip in the feeding tray a.

In one embodiment, a feed tray may include multiple positions, one position capable of receiving a chip. After a chip is placed on the feeding tray, the position information of the chip in the feeding tray can be represented by the coordinate information (such as a row number and a column number) of the chip in the feeding tray. Illustratively, the position information of the chip can be expressed as a row number and a column number. In another embodiment, when there are a plurality of feeding trays, the position information of the chip may also be represented by tray information (such as a tray number) of the feeding tray where the chip is located, and coordinate information (such as a row number and a column number) of the slot in the feeding tray. Illustratively, the position information of the chip may be expressed as tray number, row number, column number.

For example, before the current chip is picked up by the mechanical arm, the sorter may scan a tray identifier on the feeding tray by the mechanical arm to obtain the tray number; then, the sorter may obtain the row number and the column number of the current chip at the position in the feeding tray a after the robot arm puts the current chip in the feeding tray a. Thus, the sorter can obtain the positional information of the current chip on the feeding tray a. Optionally, when the sorting of the previous feeding tray is completed and the sorting of the current feeding tray a is started, the sorting machine may scan the tray identifier of the current feeding tray a through the mechanical arm to obtain the tray number of the feeding tray a. Therefore, the sorting machine does not need to scan the tray identification of the feeding tray before picking up the current chip every time, the sorting flow is simplified, and the testing efficiency is improved.

It should be noted that the sorter may perform S401 while picking up the current chip from the feeding tray a, or may perform S401 before or after picking up the current chip, which is not specifically limited in this disclosure.

S402, the sorting machine determines the grouping information of the current chip according to the mapping relation between the position information of the chip to be sorted in the feeding tray A and the grouping information of the chip.

It should be understood that the sorter may obtain the grouping information of the current chip by querying the mapping relationship between the pre-stored position information of the chip to be sorted in the feeding tray a and the grouping information thereof after obtaining the position information of the current chip in the feeding tray a through S401.

In some possible embodiments, the chips to be sorted are picked up by the sorter after the test is completed and put into the feeding tray a. The sorter can store the grouping information of each chip to be sorted from the tester and the position information thereof in the feeding tray a in an associated manner, so as to obtain the mapping relationship. Alternatively, the mapping relationship may be stored locally in the sorter, so that the sorter can quickly acquire grouping information of the chip each time the chip is picked up. Or, the mapping relationship may also be stored in a remote server, so that a plurality of controllers in the sorting machine can access the remote server at the same time, thereby sharing the mapping relationship, so that the plurality of controllers execute S402 in parallel in the sorting process, and improving the testing efficiency.

In one embodiment, the mapping relationship may be represented by an information pair consisting of the position information of the chip and the grouping information thereof. For example, assume that the tray with chips on the feeding tray is coded as #1, row 3, column 5, and the grouping information is bin # 2. Then, the position information of the chip can be represented as (#1,3,5), and the above-described mapping relationship can be represented as (#1,3,5, bin # 2).

And S403, the sorting machine puts the current chip into a blanking tray of which the grouping information corresponds to the sorting position A (such as a first sorting position).

It should be understood that, after the sorting machine obtains the grouping information of the current chip through S402, the current chip is placed in the blanking tray of the sorting location a corresponding to the grouping information of the current chip according to the preset corresponding relationship between the grouping information of each chip and the sorting location.

In one embodiment, a sorting bit is configured to correspond to a group, and the blanking tray at the sorting bit is placed into a chip of a group, for example, sorting bit a corresponds to bin #3, and the blanking tray at sorting bit a can be placed into a chip of which the grouping information is bin # 3. Alternatively, in another embodiment, a sorting location is configured to correspond to a plurality of groups, and then the blanking tray on the sorting location places a plurality of groups of chips. For example, the sorting bit a corresponds to bin #1 to bin #6, and chips whose grouping information is bin #1 to bin #6 can be put into the blanking tray of the sorting bit a, and the order in which these chips are put into the blanking tray of the sorting bit a is not limited.

Optionally, the number of chips in different groups is different. A grouping chip with a smaller number can be generated, and a blanking tray can be put down; it may also happen that a group of chips has a large number of chips and a plurality of blanking trays can be put down. It can be seen that the same group of chips can be placed in one or more blanking trays.

In some possible embodiments, before the sorting machine performs sorting, it can be judged whether multiple sorting is needed. If multiple sortings are required, the sorter may generate a prompt message to prompt the user. If sorting is not required a plurality of times, the sorter may put the chips to be sorted into the feed tray a, and perform S401 to S403 for sorting.

In practical application, the sorting machine can determine whether multiple sorting is needed according to the grouping number of the chips and the sorting position number corresponding to the feeding tray A. For example, the sorting machine may determine whether the number of chips grouped is less than or equal to the number of sorting bits corresponding to the feeding tray a. If yes, multiple sorting is not needed; if not, the sorting needs to be carried out for multiple times.

Further, if multiple sorting is required, the sorting machine can also divide a part of the chips in the feeding tray a into a group of other feeding trays, such as the feeding tray B (e.g., a second feeding tray), so that the sorting machine corresponding to the feeding tray a and the sorting machine corresponding to the feeding tray B can perform parallel sorting, and the testing efficiency is improved. Of course, the sorting machine can also divide a part of the chips in the feeding tray A into more groups of feeding trays so as to further improve the testing efficiency. At this time, the different sets of feeding trays may correspond to the same sorter, may correspond to different sorters, and the present disclosure is not particularly limited thereto.

In some possible embodiments, if the baiting tray on the sorting site a puts a plurality of grouped chips, after S403, the method may further include: and the sorting machine stores the position information of the current chip on the blanking tray on the sorting position A and the grouping information of the current chip in a correlation manner. Then, waiting for the next-stage sorting machine or the current sorting machine to sort the chips in the blanking tray on the sorting position A again. In the process of sorting the chips in the feeding tray on the sorting location a again, the sorter may take the feeding tray on the sorting location a as the feeding tray a (denoted as a feeding tray a '), and repeatedly perform S401 to S403 on the chips in the feeding tray a'.

In an embodiment, reference may be made to the descriptions of S401 to S403 for the process of sorting the chips in the feeding tray a' again. Specifically, the sorter may repeatedly perform S401 to S403 on the blanking tray at the sorting location a after storing the position information of the current chip on the blanking tray at the sorting location a and the grouping information thereof in association with each other. That is, the sorting machine can obtain the position information of the current chip in the blanking tray on the sorting position A; then, the sorting machine determines the grouping information of the current chip according to the mapping relation between the position information of the chip in the blanking tray on the sorting position A and the grouping information thereof which are stored before; and finally, the sorting machine puts the current chip into a blanking tray on a sorting position B (namely a second sorting position) corresponding to the grouping information of the current chip. At this time, the blanking tray on the sorting station B may put one or more grouped chips. And if a plurality of grouped chips are placed on the blanking tray on the sorting position B, the sorting machine repeatedly executes the steps to re-sort the chips on the blanking tray on the sorting position B. So on, it is not described herein.

For example, it is assumed that the sorting bit #1 corresponding to the feeding tray a corresponds to the grouping bin #1 to bin # 6. Taking the two-stage sorting process as an example, the sorter picks up the current chip whose grouping information is bin #3 from the feeding tray a and puts it into the blanking tray of the sorting station #1 (i.e., the first-stage sorting) through the above-described S401 to S403. When at least one blanking tray on the sorting position #1 is full, the sorting machine may repeatedly perform the above-mentioned S401 to S403 (i.e., second-stage sorting) on the chips in the blanking tray of the sorting position #1, that is, the sorting machine may pick up one chip (e.g., the above-mentioned current chip) from the blanking tray of the sorting position #1, and determine the grouping information of the current chip according to the mapping relationship of the position information of the chip in the blanking tray of the sorting position #1 and the grouping information thereof. Finally, the sorter places the current chip into the discharge tray of sorting station # 3.

It should be noted that, in practical applications, the feeding tray a and the feeding tray a' may belong to the same sorting machine, or may belong to different sorting machines. When the feeding tray a and the feeding tray a 'belong to different sorting machines, the sorting machine to which the feeding tray a' belongs may be regarded as a next-stage sorting machine of the sorting machine to which the feeding tray a belongs, that is, a sorting machine that performs secondary sorting on chips.

In some possible embodiments, before S402 and before S403, the method may further include: and the sorting machine determines whether a corresponding blanking tray exists at the sorting position according to the grouping information of the current chip. If the chip exists, the current chip is put into a blanking tray of a sorting position A corresponding to the grouping information of the current chip; if the current chip does not exist, the current chip is picked up from the feeding tray A to be adjacent to the current chip, and the steps S401 to S403 are executed in a returning mode.

It should be understood that, after determining the grouping information of the current chip, the sorting machine may first determine whether there is a sorting location a corresponding to the grouping information in the sorting location corresponding to the feeding tray a. If so, the sorter can place the current chip into a blanking tray on sorting location A for sorting. If not, the sorter may select the next chip in the feeding tray a, regard the chip as the current chip, and return to perform S401 to S402 to complete sorting of the chip.

In one embodiment, prior to S401, the sorter may first pick the current chip from the feeding tray a. Then, after S402, if the sorting machine determines that there is no sorting location a corresponding to the grouping information in the sorting locations corresponding to the feeding tray a, the sorting machine may put the current chip back to the feeding tray a, or put the current chip into another feeding tray or a blanking tray on another sorting location. Thus, the chips in the feeding tray or the discharging tray on which the current chips are placed need to be sorted again.

In another embodiment, in S401, the sorter may also determine the position information of the current chip according to the position information of the last chip picked up, and at this time, the sorter does not need to pick up the current chip. Then, after executing S402, if it is determined that there is no sort-bit a tray corresponding to the grouping information in the sort bits corresponding to the feed tray a, the sorter may pick up the next chip in the feed tray a. Therefore, in the process, the current chip does not need to be picked up, the redundant flow is avoided, the sorting speed is increased, and the testing efficiency is improved.

In some possible embodiments, before S401, the sorter may further obtain the number of groups of chips to be sorted and the number of sorting places corresponding to the feeding tray a; then, the sorter can determine grouping information corresponding to each sorting location based on the number of groups and the number of sorting locations corresponding to the feed tray a. Next, S401 to S403 are executed, and the sorter may put the current chip into the blanking tray on the sorting location a corresponding to the grouping information thereof according to the grouping information corresponding to each sorting location. Next, the sorting machine may put the chips in the blanking tray at the sorting position a into the feeding tray B, and perform S401 to S403 on the chips in the feeding tray B, so that the chips (such as the current chips mentioned above) in the feeding tray B may be put into the blanking tray at the sorting position B corresponding to the grouping information thereof, so as to realize sorting of the chips.

In one embodiment, the sorter may also calculate the quotient of the number of packets and the number of sort bits and round up to obtain the number of packets for each sort bit. Then, the sorter sequentially assigns grouping information to the respective sorting bits according to the number of the groups and the number of the sorting bits. For example, the number of chips grouped is 31, and the number of sorting bits of the feed tray a is 6. It can be seen that the corresponding number of groups for each sort bin is 6, and the sorter can allocate blanking trays for bin #1 to bin #6 for bin #1, bin #7 to bin #12 for bin #2, and so on in sequence. Alternatively, the sorting machine may randomly allocate the grouping information to the respective sorting bits according to the number of packets and the number of sorting bits. For example, the number of chips grouped is 31, and the number of sorting bits of the sorter is 6. It can be seen that the corresponding number of packets per sort bin is 6, the sorter can randomly allocate bin #1 to the blanking trays of bin #2, bin #5, bin #7, bin #9, bin #20, and bin #30, bin #2 to bin #1, bin #3, bin #6, bin #8, bin #16, and bin #31, and so on. Of course, the sorting machine may also determine the grouping information of each sorting bit allocation by other methods, which is not specifically limited by the embodiment of the present disclosure.

For example, when the sorter picks up a chip, the chip may be placed in the current blanking tray (i.e., the second blanking tray) in the sorting location (i.e., the first sorting location) corresponding to the grouping information. Assume that bin #1 is allocated to chips put into bin #1 to bin # 5. When the grouping information of the chip picked up by the sorter is bin #3, the sorter puts the chip into the current blanking tray on the sorting bit # 1. Waiting for the chip in each blanking tray on the sorting position #1 to be sorted again by the local sorting machine or the next-stage sorting machine, so that each chip is sorted into the blanking tray corresponding to the grouping information, namely, the chip is put into the blanking tray of bin # 3.

The above method is further described below with specific example pairs.

In the first case, it is assumed that the number of sorting bits of the sorter is greater than or equal to the number of packets of the chip, one sorting bit corresponding to one packet.

Fig. 5 is a schematic flow chart of another chip sorting method in an embodiment of the present disclosure, and referring to fig. 5, the chip sorting method may include:

s501, after testing of each chip is completed, the testing machine sends grouping information of the chips to be sorted to the sorting machine.

S502, the sorting machine picks up each chip to be sorted from the test base of the testing machine and puts the chip into a corresponding position in the feeding tray A.

It should be understood that the sorter may place the chips to be sorted in sequence in different positions of the feeding tray in the order of picking. Optionally, chips in different groups can be placed in the same feeding tray, or chips in the same group can be placed in different feeding trays.

S503, the sorting machine stores the position information of each position on the feeding tray A and the grouping information of the corresponding chip in a correlation mode, and therefore the mapping relation between the position information of each chip to be sorted and the grouping information is obtained.

It should be understood that the mapping may be stored locally in the sorter so that the sorter can quickly obtain grouping information for the current chip each time the current chip is picked up. Or, the mapping relationship may also be stored in a remote server, so that a plurality of controllers in the sorting machine can access the remote server at the same time, thereby sharing the mapping relationship, so that the plurality of controllers execute S503 in parallel in the sorting process, and improving the testing efficiency.

S504, the sorter picks up the current chip from the first position of the feeding tray a and obtains position information of the first position.

And S505, the sorting machine inquires the mapping relation according to the position information of the first position to obtain the grouping information of the current chip.

S506, the sorting machine puts the current chip into the blanking tray of the sorting position A corresponding to the grouping information of the current chip.

It should be understood that the execution process of S503 to S506 may refer to the description of S401 to S403 in the embodiment of fig. 4, and is not described herein again.

It can be understood that, in the embodiment of fig. 5, regardless of the grouping number of the chips, as long as the number of the sorting bits of the sorter is greater than or equal to the sorting number of the chips, the sorting of the plurality of groups of chips can be completed at one time, the sorting process is simplified, and the testing efficiency is improved.

In the second case, assuming that the number of sorting bits of the sorter is smaller than the number of packets of the chip, one sorting bit corresponds to a plurality of packets.

Fig. 6 is a schematic flow chart of an implementation of another chip sorting method in an embodiment of the present disclosure, and referring to fig. 6, the chip sorting method may include:

s601, after the testing machine completes the testing of each chip, the grouping information of the chips to be sorted is sent to the sorting machine by the testing machine.

S602, the sorting machine picks up each chip to be sorted from the test base of the testing machine and puts the chip into a corresponding position in the feeding tray A.

In one embodiment, the sorter may place the individual chips to be sorted in the order of picking into different positions of the feeding tray a in sequence. Optionally, chips in different groups can be placed in the same feeding tray, or chips in the same group can be placed in different feeding trays.

S603, the sorting machine stores the position information of each position on the feeding tray A and the grouping information of the corresponding chip in a correlation mode, so that the mapping relation between the position information and the grouping information of each chip to be sorted is obtained.

It should be understood that the execution process of S601 to S603 may refer to the description of S501 to S503 in the embodiment of fig. 5, and is not described herein again.

S604, the sorter picks up the current chip from the first position of the feeding tray a and obtains position information of the first position.

And S605, the sorting machine inquires the mapping relation according to the position information of the first position to obtain the grouping information of the current chip.

S606, the sorting machine determines the sorting position A corresponding to the grouping information of the current chip in the sorting position corresponding to the feeding tray A.

And S607, putting the current chip into the blanking tray on the corresponding sorting position A by the sorting machine.

And S608, the sorting machine stores the position information of each chip in the blanking tray on the sorting position A in a correlated manner with the grouping information of the chip.

And S609, taking the blanking tray on the sorting position A as a feeding tray A by the sorting machine, and returning to execute S604 to S607 to place the current chip into the corresponding blanking tray on the sorting position B.

In the disclosed embodiment, since the number of sorting bits of the sorter is smaller than the number of groups of chips, the chips must be sorted multiple times. In the process of sorting for many times, the sorting machine can determine the grouping information of the chips according to the positions of the chips on the feeding tray, and then the chips are placed into the corresponding discharging tray, repeated tests on the chips are not needed, the sorting of the grouped chips can be completed, and the testing efficiency is improved. Furthermore, the sorting machine can place the chips to be sorted into the feeding trays of different groups, so that the chips can be parallelly sorted on one or more sorting positions corresponding to the feeding trays of different groups, the sorting speed is greatly increased, and the testing efficiency is improved.

Based on the same inventive concept, the embodiment of the present disclosure further provides a chip sorting apparatus, which may be a chip or a system on a chip in a sorting machine, or a functional module in a sorting device for implementing the method according to any embodiment of the present disclosure. The chip sorting device can realize the functions executed by the sorting machine in any embodiment of the disclosure, and the functions can be realized by executing corresponding software through hardware. The hardware or software includes one or more modules corresponding to the above functions. Fig. 7 is a schematic structural diagram of a chip sorting apparatus according to an embodiment of the disclosure, and referring to fig. 7, a chip sorting apparatus 700 includes: an obtaining module 701, configured to obtain position information of a current chip in a first feeding tray; a determining module 702, configured to determine grouping information of a current chip according to a mapping relationship between position information of the chip to be sorted in the first feeding tray and the grouping information of the chip to be sorted; the control module 703 is configured to put the current chip into a blanking tray on the first sorting bit corresponding to the grouping information of the current chip, where the blanking tray is configured to put one or more grouped chips.

In some possible embodiments, still referring to fig. 7, the apparatus 700 further includes: the identifying module 704 is used for identifying coordinate information of the chips to be sorted in the first feeding tray and/or tray information of the first feeding tray.

In some possible embodiments, the obtaining module is further configured to obtain the number of groups of chips to be sorted and the number of sorting bits corresponding to the first feeding tray before obtaining the position information of the current chip in the first feeding tray; the determining module is further used for determining whether multiple sorting is needed according to the grouping number and the number of the sorting bits; the control module is also used for placing the chips to be sorted into at least a first feeding tray and a second feeding tray if the chips need to be sorted for multiple times; and if the chips do not need to be sorted for multiple times, putting the chips to be sorted into a first feeding tray.

Based on the same inventive concept, embodiments of the present disclosure provide a sorter, consistent with the sorter described in one or more of the above embodiments, which may include: a processor, and a memory for storing processor-executable instructions; wherein the processor is configured to: when the executable instructions are executed, the chip sorting method according to one or more of the embodiments is realized.

Based on the same inventive concept, the disclosed embodiments provide a computer-readable storage medium, which stores an executable program, wherein the executable program, when executed by a processor, implements the chip sorting method according to one or more of the above embodiments.

Those of skill in the art will appreciate that the functions described in connection with the various illustrative logical blocks, modules, and algorithm steps described in the disclosure herein may be implemented as hardware, software, firmware, or any combination thereof. If implemented in software, the functions described in the various illustrative logical blocks, modules, and steps may be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. The computer-readable medium may include a computer-readable storage medium, which corresponds to a tangible medium, such as a data storage medium, or any communication medium including a medium that facilitates transfer of a computer program from one place to another (e.g., according to a communication protocol). In this manner, a computer-readable medium may generally correspond to (1) a non-transitory tangible computer-readable storage medium, or (2) a communication medium, such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementing the techniques described in this disclosure. The computer program product may include a computer-readable medium.

By way of example, and not limitation, such computer-readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that the computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are instead directed to non-transitory tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The instructions may be executed by one or more processors, such as one or more Digital Signal Processors (DSPs), general purpose microprocessors, Application Specific Integrated Circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Thus, the term "processor," as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Additionally, in some aspects, the functions described by the various illustrative logical blocks, modules, and steps described herein may be provided within dedicated hardware and/or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques may be fully implemented in one or more circuits or logic elements.

The techniques of this disclosure may be implemented in a variety of described devices or apparatuses, including a wireless handset, an Integrated Circuit (IC), or a set of ICs (e.g., a chipset). Various components, modules, or units are described in this disclosure to emphasize functional aspects of means for performing the disclosed techniques, but do not necessarily require realization by different hardware units. Indeed, as described above, the various units may be combined in a codec hardware unit, in conjunction with suitable software and/or firmware, or provided by an interoperating hardware unit (including one or more processors as described above).

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The above description is only an exemplary embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of chip sorting, comprising:

obtaining the position information of the current chip in the first feeding tray;

determining grouping information of the current chip according to the mapping relation between the position information of the chip to be sorted in the first feeding tray and the grouping information of the chip to be sorted;

and putting the current chip into a blanking tray on a first sorting position corresponding to the grouping information of the current chip, wherein the blanking tray is configured to put one or more grouped chips.

2. The method of claim 1, wherein the position information of the current chip in the first feeding tray comprises: coordinate information of the current chip in the first feeding tray; or the coordinate information of the current chip in the first feeding tray and the tray information of the first feeding tray are used for uniquely identifying the first feeding tray.

3. The method according to claim 1, wherein before the determining the grouping information of the current chip according to the mapping relationship between the position information of the chips to be sorted in the first feeding tray and the grouping information of the chips to be sorted, the method further comprises:

obtaining grouping information of the chips to be sorted;

after the chips to be sorted are placed in the first feeding tray, position information of the chips to be sorted in the first feeding tray is obtained;

and storing the position information of the chips to be sorted in the first feeding tray in association with the grouping information of the chips to be sorted.

4. The method of claim 3, wherein the obtaining the grouping information of the chips to be sorted comprises:

performing packaging test on the chips to be sorted to obtain grouping information of the chips to be sorted; or the like, or, alternatively,

and receiving grouping information of the chips to be sorted from the testing machine.

5. The method of claim 1, wherein the placing the current chip into a blanking tray on a first sorting bit corresponding to grouping information of the current chip comprises:

judging whether the first sorting position exists in each sorting position corresponding to the first feeding tray or not according to the grouping information of the current chip;

if so, putting the current chip into a blanking tray on the first sorting position;

after determining whether the first sorting bit exists on each sorting bit according to the grouping information of the current chip, the method further includes:

and if not, acquiring the position information of the next chip in the first feeding tray.

6. The method of claim 1, wherein prior to said obtaining position information of the current chip in the first feeder tray, the method further comprises:

obtaining the grouping number of the chips to be sorted and the number of sorting positions corresponding to the first feeding tray;

determining whether multiple sorting is needed or not according to the grouping number and the number of the sorting bits;

if multiple sorting is needed, the chips to be sorted are at least placed into the first feeding tray and the second feeding tray;

and if the chips do not need to be sorted for multiple times, putting the chips to be sorted into the first feeding tray.

7. The method of claim 6, wherein determining whether multiple sortings are required based on the number of packets and the number of sortation bits comprises:

judging whether the packet number is less than or equal to the number of the sorting bits; if yes, multiple sorting is not needed; if not, the sorting needs to be carried out for multiple times.

8. The method according to claim 1, wherein when a plurality of grouped chips are placed in the blanking tray on the first sorting location, after the current chip is placed in the blanking tray on the first sorting location corresponding to the grouping information of the current chip, the method further comprises:

storing the position information of the current chip in the blanking tray on the first sorting position in a correlated manner with the grouping information of the current chip;

and taking the blanking tray on the first sorting position as the first feeding tray, and returning to the step of obtaining the position information of the current chip in the first feeding tray.

9. A chip sorting apparatus, comprising:

the acquisition module is used for acquiring the position information of the current chip in the first feeding tray;

the determining module is used for determining the grouping information of the current chip according to the mapping relation between the position information of the chip to be sorted in the first feeding tray and the grouping information of the chip to be sorted;

and the control module is used for placing the current chip into a blanking tray on a first sorting position corresponding to the grouping information of the current chip, wherein the blanking tray is configured to be placed with one or more grouped chips.

10. The apparatus of claim 9, wherein the position information of the current chip in the first feeding tray comprises: coordinate information of the current chip in the first feeding tray; or the coordinate information of the current chip in the first feeding tray and the tray information of the first feeding tray are used for uniquely identifying the first feeding tray.

11. The apparatus of claim 10, further comprising: and the identification module is used for identifying the coordinate information of the chips to be sorted in the first feeding tray and/or the tray information of the first feeding tray.

12. The apparatus according to claim 9, wherein the obtaining module is further configured to obtain grouping information of the chips to be sorted; after the control module puts the chips to be sorted into the first feeding tray, the position information of the chips to be sorted in the first feeding tray is obtained; storing the position information of the chips to be sorted in the first feeding tray and the grouping information of the chips to be sorted in a correlated manner; the control module is also used for placing the chips to be sorted into the first feeding tray.

13. The apparatus according to claim 12, wherein the obtaining module is further configured to perform a package test on the chips to be sorted, so as to obtain grouping information of the chips to be sorted; or, receiving grouping information of the chips to be sorted from the tester.

14. The apparatus according to claim 9, wherein the control module is configured to determine whether the first sorting location exists in the sorting locations corresponding to the first feeding tray according to the grouping information of the current chip; if so, putting the current chip into a blanking tray on the first sorting position;

the obtaining module is further configured to obtain position information of a next chip in the first feeding tray if the chip is not located in the first feeding tray.

15. The apparatus of claim 9, wherein the obtaining module is further configured to obtain the number of groups of the chips to be sorted and the number of sorting bits corresponding to the first feeding tray before obtaining the position information of the current chip in the first feeding tray; the determining module is further configured to determine whether multiple sorting is required according to the number of the packets and the number of the sorting bits; the control module is also used for placing the chips to be sorted into at least the first feeding tray and the second feeding tray if the chips need to be sorted for multiple times; and if the chips do not need to be sorted for multiple times, putting the chips to be sorted into the first feeding tray.

16. The apparatus of claim 15, wherein the determining module is further configured to determine whether the number of packets is less than or equal to the number of sorting bits; if yes, multiple sorting is not needed; if not, the sorting needs to be carried out for multiple times.

17. The apparatus according to claim 9, wherein when a plurality of grouped chips are placed in the blanking tray at the first sorting location, the obtaining module is further configured to store the position information of the current chip in the blanking tray at the first sorting location in association with the grouping information of the current chip after the control module places the current chip in the blanking tray at the first sorting location corresponding to the grouping information of the current chip; and taking the blanking tray on the first sorting position as the first feeding tray, and returning to the step of obtaining the position information of the current chip in the first feeding tray.

18. A test sorting system, comprising: the chip sorting device comprises a feeding tray for placing chips to be sorted, at least one sorting machine and a discharging tray for placing sorted chips; wherein the at least one sorter is configured to perform the chip sorting method of any of claims 1 to 8.

19. The system of claim 18, wherein the test sorting system further comprises: and the tester is used for carrying out packaging test on the chips to be sorted so as to obtain the grouping information of the chips to be sorted.

20. A sorter, comprising: a processor, and a memory for storing processor-executable instructions; wherein the processor is configured to: for implementing the chip sorting method according to any one of claims 1 to 8 when executing the executable instructions.

21. A computer-readable storage medium, characterized in that the readable storage medium stores an executable program, wherein the executable program, when executed by a processor, implements the chip sorting method according to any one of claims 1 to 8.