CN105467256A - Chip testing and sorting method - Google Patents

Chip testing and sorting method Download PDF

Info

Publication number
CN105467256A
CN105467256A CN201510246093.0A CN201510246093A CN105467256A CN 105467256 A CN105467256 A CN 105467256A CN 201510246093 A CN201510246093 A CN 201510246093A CN 105467256 A CN105467256 A CN 105467256A
Authority
CN
China
Prior art keywords
test
chip
separator
tester
station
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510246093.0A
Other languages
Chinese (zh)
Inventor
顾汉玉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semicon Microelectronics Shenzhen Co Ltd
Original Assignee
Semicon Microelectronics Shenzhen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semicon Microelectronics Shenzhen Co Ltd filed Critical Semicon Microelectronics Shenzhen Co Ltd
Priority to CN201510246093.0A priority Critical patent/CN105467256A/en
Publication of CN105467256A publication Critical patent/CN105467256A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)

Abstract

The present invention relates to a chip testing and sorting method which comprises the steps of (S1) providing a tester and a multi-station sorter, (S2) connecting the tester and the communication interface of the sorter through a cable, and connecting the test port of the tester and the station of the sorter, (S3) reserving a station which does not pass a test of the sorter and closing other stations of the sorter, (S4) testing whether the cable connection relation of the currently reserved station is correct or not, showing that the currently reserved station passes the test if the connection relation is correct, repeating the step (S3) until all stations pass the test, adjusting the cable connection relation of the currently reserved station if the connection relation is wrong, and repeating the step (S4), and (S5) starting all stations of the sorter, and carrying out batch test sorting of chips. According to the chip testing and sorting method, the wrong classification problem caused by the wrong cable connection of multiple stations can be effectively avoided.

Description

Chip testing method for separating
Technical field
The present invention relates to field of semiconductor device test, particularly relate to a kind of multistation semiconductor packaging chip testing and sorting method.
Background technology
Along with the development of semiconductor fabrication and characterization processes, separator is widely used in the testing process of semiconductor devices, to carry out quality test to semiconductor packaging chip (IC), sub-elects test passes and underproof finished product.And constantly promote along with the production capacity of semiconductor packaging chip, in order to improve the efficiency of testing, sorting, separator has multiple station usually, to test and sorting multiple semiconductor packaging chip simultaneously.
Fig. 1 illustrates the electrical connection of existing multistation separator and tester (ATE).Separator comprise four communication interfaces 1,2,3,4 and with these four communication interfaces four stations (in the present embodiment, four stations are four mechanical arms: mechanical arm 1, mechanical arm 2, mechanical arm 3, mechanical arm 4) one to one, tester comprise four communication interfaces 1,2,3,4 and with these four communication interfaces four test ports one to one: TEST1, TEST2, TEST3, TEST4.
When using separator and tester to carry out chip testing sorting, the TEST1 of tester will be connected to mechanical arm 1 by test cable, TEST2 will be connected to mechanical arm 2 by test cable, TEST3 will be connected to mechanical arm 3 by test cable, TEST4 will be connected to mechanical arm by test cable, and four communication interfaces of separator and four communication interfaces of tester are also connected one to one by telecommunication cable.The connection of above-mentioned cable is by manually completing, and mechanical arm, TESTS and communication interface are all artificial cognition simultaneously, and therefore the annexation of test cable and telecommunication cable is easily made mistakes, and causes test result mistake.
Such as shown in Fig. 2, the annexation that four communication interfaces of separator are connected by four telecommunication cables with four communication interfaces of tester is correct, and the test cable annexation wrong of four test ports and four mechanical arms.Wherein, the first station mechanical arm 1 linked TEST2, the second station mechanical arm 2 linked TEST1.If TEST1 test is by (PASS), and TEST2 test is not by (FAIL), separator can be assigned in PASS class the chip of the first station mechanical arm 1, the chip of the second station mechanical arm 2 is assigned in FAIL class, but what in fact TEST2 surveyed is chip on the first station mechanical arm 1, will cause the product having FAIL in PASS class like this.Equally, if telecommunication cable wrong and connect mechanical arm and be connected with the test cable of test port and correctly also can produce this misclassification result.
Summary of the invention
Based on this, be necessary, for the above-mentioned misclassification problem caused because of multistation separator cabling error, to provide a kind of chip testing method for separating avoiding misclassification.
A kind of chip testing method for separating, comprises step:
S1., the tester with multiple test port and multiple communication interface and the separator with multiple station and multiple communication interface are provided;
S2. by telecommunication cable, the communication interface of tester is connected one to one with the communication interface of separator, and by test cable, multiple test port of tester is connected one to one with multiple stations of separator;
S3. retain the station not yet passing test of separator and close other stations of separator;
Whether the telecommunication cable annexation of S4. testing between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and current reservation and corresponding tester communication interface is correct,
If it is correct to test out annexation, the station of current reservation, by test, carries out S3 step again, until all stations all pass through test;
If it is incorrect to test out annexation, adjusts the telecommunication cable annexation between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and/or current reservation and corresponding tester communication interface, then continue to repeat S4 step;
S5. open all stations of separator, multiple stations of separator carry out the batch testing sorting of chip simultaneously.
Make mistakes because cable connects, only just can there will be when multistation separator is tested, and connect the cable of mechanical arm in single station separator and telecommunication cable annexation is all unique, have uniqueness, therefore single station there will not be the misclassification problem caused because of cabling error.
Said chip testing and sorting method, when multistation test starts, first utilize the cable annexation uniqueness of single station, single station chip testing is carried out successively to each station of separator, check the correctness of cable annexation, after guaranteeing that cable annexation that all stations of separator are corresponding is correct, then utilize multiple station to carry out formal chip detection sorting simultaneously, effectively avoid the misclassification problem caused because of multistation separator cabling error.
Wherein in an embodiment, described S2 step is by the test port of artificial cognition tester and the station of communication interface and separator and communication interface, and by manually the communication interface of connecting test instrument being connected with multiple stations of separator one to one with the communication interface of separator and multiple test port of tester.
Wherein in an embodiment, described S4 step by test on the station of current reservation survey intact chip judge the station of current reservation and the test cable annexation of tester test port and the telecommunication cable annexation between separator communication interface corresponding to the station of current reservation and corresponding tester communication interface whether correct, if described intact chip is by test, then the station of current reservation is by test, all stations again carry out S3 step, until can make intact chip by carrying out S5 step again after test; If described intact chip is not by test, then check and adjust the telecommunication cable annexation between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and/or current reservation and corresponding tester communication interface, then continuing to repeat S4 step.
Wherein in an embodiment, described S4 step by test on the station of current reservation predetermined quantity do not survey chip judge the station of current reservation and the test cable annexation of tester test port and the telecommunication cable annexation between separator communication interface corresponding to the station of current reservation and corresponding tester communication interface whether correct, if there is chip to pass through test in the chip of described predetermined quantity, then the station of current reservation is by test, again carry out S3 step, until carry out S5 step again after all stations having chip pass through test; If do not have chip to pass through test in the chip of described predetermined quantity, then check and adjust the telecommunication cable annexation between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and/or current reservation and corresponding tester communication interface, then continuing to repeat S4 step.
Wherein in an embodiment, described S4 step comprises step when testing each chip: on the station of current reservation, place chip to be measured, separator sends commencing signal by telecommunication cable to tester, be connected to the chip to be measured of test port after tester receives commencing signal by test cable test, test result is sent to separator by telecommunication cable by tester.
Wherein in an embodiment, after test result is sent to separator by telecommunication cable by instrument to be tested, according to the test result that tester sends, described separator judges that whether this chip to be measured is by test.
Wherein in an embodiment, each station of described separator is a mechanical arm, this mechanical arm is for capturing chip to be measured, and this mechanical arm is connected to the test port of tester to reach the electrical connection between crawled chip to be measured and tester test port by test cable.
Wherein in an embodiment, described S5 step comprises step when carrying out the batch testing sorting of chip on multiple stations of separator simultaneously: on each station, place a chip to be measured, separator sends commencing signal by telecommunication cable to tester, be connected to the chip each to be measured of each test port after tester receives commencing signal by test cable test, the test result of each chip to be measured is sent to separator by telecommunication cable by tester.
Wherein in an embodiment, after the test result of each chip to be measured is sent to separator by telecommunication cable by instrument to be tested, according to the test result that tester sends, described separator judges that whether each chip to be measured is by test.
Wherein in an embodiment, after according to the test result that tester sends, separator judges whether each chip to be measured passes through test, whether described separator is placed each sorting chips to be measured by testing according to each chip to be measured.
Accompanying drawing explanation
Fig. 1 is the electrical connection figure of existing multistation separator and tester.
Fig. 2 is the wrong electrical connection figure of existing multistation separator and tester.
Fig. 3 is the process flow diagram of a kind of chip testing method for separating provided by the invention.
Fig. 4 is a kind of separator of chip testing method for separating provided by the invention and the electrical connection figure of tester.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 3 is the process flow diagram of a kind of chip testing method for separating provided by the invention, and this chip testing method for separating comprises following S1-S5 step.
S1., the tester with multiple test port and multiple communication interface and the separator with multiple station and multiple communication interface are provided.
Please also refer to Fig. 4, in the present embodiment, the tester 10 that S1 provides comprises four test ports TEST1, TEST2, TEST3, TEST4 and multiple communication interface 101,102,103,104; The separator 20 that S1 provides comprises four communication interfaces, 201,202,203,204 and four stations.In the present embodiment, each station of separator 20 is that a mechanical arm is for crawl chip to be measured, four stations of separator 20 and mechanical arm 1, mechanical arm 2, mechanical arm 3, mechanical arm 4.
S2. by telecommunication cable, the communication interface of tester is connected one to one with the communication interface of separator, and by test cable, multiple test port of tester is connected one to one with multiple stations of separator.
In the present embodiment, by the test port of artificial cognition tester and the station of communication interface and separator and communication interface, and by manually the communication interface of connecting test instrument being connected with multiple stations of separator one to one with the communication interface of separator and multiple test port of tester.Concrete, the communication interface 101,102,103,104 of tester 10 is connected with the communication interface 201,202,203,204 of separator 20 by telecommunication cable 30 respectively one to one as shown in Figure 4, test cable 40 by test port TEST1, TEST2, TEST3, TEST4 of tester 10 respectively with the mechanical arm 1 of separator 20, mechanical arm 2, mechanical arm 3, mechanical arm 4 be connected one to one.Thus described mechanical arm is connected to the test port of tester 10 to reach the electrical connection between crawled chip to be measured and tester test port by test cable 40.
S3. retain the station not yet passing test of separator and close other stations of separator.
In the present embodiment, any one mechanical arm not yet passing test can be selected from four of separator 20 station and close the mechanical arm of other stations of separator.
Whether the telecommunication cable annexation of S4. testing between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and current reservation and corresponding tester communication interface is correct,
If it is correct to test out annexation, the station of current reservation, by test, carries out S3 again, until all stations carry out S5 after all passing through test again;
If it is incorrect to test out annexation, adjusts the telecommunication cable annexation between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and/or current reservation and corresponding tester communication interface, then continue to repeat S4.
In the present embodiment, S4 step can by test on the station of current reservation in advance through the intact chip of test judge the station of current reservation and the test cable annexation of tester test port and the telecommunication cable annexation between separator communication interface corresponding to the station of current reservation and corresponding tester communication interface whether correct.
Must by test owing to surveying intact chip, if the telecommunication cable annexation between the separator communication interface that the mechanical arm that is wrong and/or this reservation station of the test cable annexation between the mechanical arm of this reservation station to its corresponding tester port is corresponding and corresponding tester communication interface is wrong, then will inevitably cause intact chip cannot by test on the station of current reservation, so can judge that whether test cable and telecommunication cable whether annexation is wrong according to the test result of this intact chip on current reservation station.
If described intact chip is by test, the station that then can judge current reservation is by test (test cable that namely current reservation station is corresponding and telecommunication cable annexation correct), and then carry out S3 step, until all stations (i.e. mechanical arm) of separator 20 can make intact chip by carrying out S5 step again after test; If described intact chip is not by test, then check and adjust the telecommunication cable annexation between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and/or current reservation and corresponding tester communication interface, then continuing to repeat S4 step.
Certainly, in another embodiment of this case, S4 step can not surveyed by (in this enforcement, can be 20 or 30 or more) of testing predetermined quantity on the station of current reservation chip to judge the station of current reservation and the test cable annexation of tester test port and the telecommunication cable annexation between separator communication interface corresponding to the station of current reservation and corresponding tester communication interface whether correct.
Due to predetermined quantity do not survey in chip must have can by test intact chip, if the telecommunication cable annexation between the separator communication interface that the mechanical arm that is wrong and/or this reservation station of the test cable annexation between the mechanical arm of this reservation station to its corresponding tester port is corresponding and corresponding tester communication interface is wrong, any chip then will inevitably be caused all cannot to pass through test on the station of current reservation, so can judge that whether test cable and telecommunication cable whether annexation is wrong according to having on current reservation station chipless by test.
If there is chip to pass through test in the chip of described predetermined quantity, then the station of current reservation, by test, carries out S3 step again, until carry out S5 step again after all stations having chip pass through test; If do not have chip to pass through test in the chip of described predetermined quantity, then check and adjust the telecommunication cable annexation between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and/or current reservation and corresponding tester communication interface, then continuing to repeat S4 step.
S5. open all stations of separator, multiple stations of separator carry out the batch testing sorting of chip simultaneously.
All pass through after test until all stations (being mechanical arm in the present embodiment) on separator 20, then can judge that the annexation of all test cables and telecommunication cable is correct, all stations that then just can start separator 20 carry out batch testing sorting to chip to be measured, to raise the efficiency under the prerequisite guaranteeing accuracy rate.
It should be noted that, S4 step may further include step when testing each chip: on the station of current reservation, place chip to be measured, separator 20 sends commencing signal by telecommunication cable 30 to tester 10, be connected to the chip to be measured of test port after tester 10 receives commencing signal by test cable 40 test, test result is sent to separator by telecommunication cable 30 by tester 10.Further, after test result is sent to separator by telecommunication cable by instrument to be tested, according to the test result that tester 10 sends, described separator 20 judges that whether this chip to be measured is by test.
In addition, step is comprised: on each station, place a chip to be measured when multiple stations of S5 step separator carrying out simultaneously the batch testing sorting of chip, separator 20 sends commencing signal by telecommunication cable 30 to tester 10, be connected to the chip each to be measured of each test port after tester 10 receives commencing signal by test cable 40 test, the test result of each chip to be measured is sent to separator 20 by telecommunication cable 30 by tester 10.Further, after the test result of each chip to be measured is sent to separator 20 by telecommunication cable 30 by instrument 10 to be tested, according to the test result that tester 10 sends, described separator 20 judges that whether each chip to be measured is by test.Further, after according to the test result that tester 10 sends, separator 20 judges whether each chip to be measured passes through test, whether described separator 20 is placed sorting chips to be measured by test according to each chip to be measured.
Because cable between separator with tester is connected the phenomenon of makeing mistakes, only just can there will be when multistation separator is tested, and connect the cable of mechanical arm in single station separator and telecommunication cable annexation is all unique, have uniqueness, therefore single station there will not be the misclassification problem caused because of cabling error.Said chip testing and sorting method, when multistation test starts, first utilize the cable annexation uniqueness of single station, single station chip testing is carried out successively to each station of separator, check the correctness of cable annexation, after guaranteeing that cable annexation that all stations of separator are corresponding is correct, then utilize multiple station to carry out formal chip detection sorting simultaneously, effectively avoid the misclassification problem caused because of multistation separator cabling error.
Each technical characteristic of the above embodiment can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, be all considered to be the scope that this instructions is recorded.
The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.

Claims (10)

1. a chip testing method for separating, comprises step:
S1., the tester with multiple test port and multiple communication interface and the separator with multiple station and multiple communication interface are provided;
S2. by telecommunication cable, the communication interface of tester is connected one to one with the communication interface of separator, and by test cable, multiple test port of tester is connected one to one with multiple stations of separator;
S3. retain the station not yet passing test of separator and close other stations of separator;
Whether the telecommunication cable annexation of S4. testing between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and current reservation and corresponding tester communication interface is correct,
If it is correct to test out annexation, the station of current reservation, by test, carries out S3 step again, until all stations all pass through test;
If it is incorrect to test out annexation, adjusts the telecommunication cable annexation between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and/or current reservation and corresponding tester communication interface, then continue to repeat S4 step;
S5. open all stations of separator, multiple stations of separator carry out the batch testing sorting of chip simultaneously.
2. chip testing method for separating according to claim 1, it is characterized in that, described S2 step is by the test port of artificial cognition tester and the station of communication interface and separator and communication interface, and by manually the communication interface of connecting test instrument being connected with multiple stations of separator one to one with the communication interface of separator and multiple test port of tester.
3. chip testing method for separating according to claim 1, it is characterized in that, described S4 step by test on the station of current reservation survey intact chip judge the station of current reservation and the test cable annexation of tester test port and the telecommunication cable annexation between separator communication interface corresponding to the station of current reservation and corresponding tester communication interface whether correct
If described intact chip is by test, then the station of current reservation, by test, carries out S3 step again, until all stations can make intact chip by carrying out S5 step again after test;
If described intact chip is not by test, then check and adjust the telecommunication cable annexation between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and/or current reservation and corresponding tester communication interface, then continuing to repeat S4 step.
4. chip testing method for separating according to claim 1, it is characterized in that, described S4 step by test on the station of current reservation predetermined quantity do not survey chip judge the station of current reservation and the test cable annexation of tester test port and the telecommunication cable annexation between separator communication interface corresponding to the station of current reservation and corresponding tester communication interface whether correct
If there is chip to pass through test in the chip of described predetermined quantity, then the station of current reservation, by test, carries out S3 step again, until carry out S5 step again after all stations having chip pass through test;
If do not have chip to pass through test in the chip of described predetermined quantity, then check and adjust the telecommunication cable annexation between separator communication interface corresponding to the station of the station of current reservation and the test cable annexation of tester test port and/or current reservation and corresponding tester communication interface, then continuing to repeat S4 step.
5. the chip testing method for separating according to claim 3 or 4, it is characterized in that, described S4 step comprises step when testing each chip: on the station of current reservation, place chip to be measured, separator sends commencing signal by telecommunication cable to tester, be connected to the chip to be measured of test port after tester receives commencing signal by test cable test, test result is sent to separator by telecommunication cable by tester.
6. chip testing method for separating according to claim 5, is characterized in that, after test result is sent to separator by telecommunication cable by instrument to be tested, according to the test result that tester sends, described separator judges that whether this chip to be measured is by test.
7. chip testing method for separating according to claim 1, it is characterized in that, each station of described separator is a mechanical arm, this mechanical arm is for capturing chip to be measured, and this mechanical arm is connected to the test port of tester to reach the electrical connection between crawled chip to be measured and tester test port by test cable.
8. chip testing method for separating according to claim 1, it is characterized in that, described S5 step comprises step when carrying out the batch testing sorting of chip on multiple stations of separator simultaneously: on each station, place a chip to be measured, separator sends commencing signal by telecommunication cable to tester, be connected to the chip each to be measured of each test port after tester receives commencing signal by test cable test, the test result of each chip to be measured is sent to separator by telecommunication cable by tester.
9. chip testing method for separating according to claim 8, it is characterized in that, after the test result of each chip to be measured is sent to separator by telecommunication cable by instrument to be tested, according to the test result that tester sends, described separator judges that whether each chip to be measured is by test.
10. chip testing method for separating according to claim 8, it is characterized in that, after according to the test result that tester sends, separator judges whether each chip to be measured passes through test, whether described separator is placed each sorting chips to be measured by testing according to each chip to be measured.
CN201510246093.0A 2015-05-14 2015-05-14 Chip testing and sorting method Pending CN105467256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510246093.0A CN105467256A (en) 2015-05-14 2015-05-14 Chip testing and sorting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510246093.0A CN105467256A (en) 2015-05-14 2015-05-14 Chip testing and sorting method

Publications (1)

Publication Number Publication Date
CN105467256A true CN105467256A (en) 2016-04-06

Family

ID=55605174

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510246093.0A Pending CN105467256A (en) 2015-05-14 2015-05-14 Chip testing and sorting method

Country Status (1)

Country Link
CN (1) CN105467256A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108829080A (en) * 2018-05-18 2018-11-16 广州益为科技有限公司 A kind of high-end environment-protecting clean robot
CN110314864A (en) * 2018-03-28 2019-10-11 北京君正集成电路股份有限公司 Chip detecting method and device based on manipulator
CN110320427A (en) * 2018-03-28 2019-10-11 北京君正集成电路股份有限公司 Chip detecting method and device
CN110320457A (en) * 2018-03-28 2019-10-11 北京君正集成电路股份有限公司 Chip grabs control method and device
CN110320459A (en) * 2018-03-28 2019-10-11 北京君正集成电路股份有限公司 Chip automated testing method and device
CN110320458A (en) * 2018-03-28 2019-10-11 北京君正集成电路股份有限公司 Automate chip test system
CN111871865A (en) * 2020-06-30 2020-11-03 绍兴网策科技有限公司 Integrated circuit testing device and testing method
CN112444730A (en) * 2020-10-15 2021-03-05 绍兴网策科技有限公司 Fool-proof method for multi-Site mode testing device and fool-proof method for testing machine
CN113578781A (en) * 2021-07-26 2021-11-02 北京比特大陆科技有限公司 Chip sorting method, device, equipment and storage medium
CN113828548A (en) * 2021-11-26 2021-12-24 南京派格测控科技有限公司 Radio frequency chip testing device and method
CN114247664A (en) * 2021-12-27 2022-03-29 厦门科塔电子有限公司 Chip FT test system and method integrating sorting and testing

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020183954A1 (en) * 2001-05-30 2002-12-05 Sumitomo Wiring Systems, Ltd. Processing system for a wiring harness, a method for testing an electrical connection of a wiring harness, computer-readable storage medium and a wire connection assisting system
CN101030159A (en) * 2006-02-28 2007-09-05 环达电脑(上海)有限公司 Apparatus and system for testing host slot
CN102172107A (en) * 2008-10-09 2011-08-31 株式会社爱德万测试 Circuit board, circuit board assembly and misinsertion detecting device
CN102854455A (en) * 2012-09-21 2013-01-02 成都市中州半导体科技有限公司 Integrated circuit testing system and control method for same
CN202893706U (en) * 2012-11-17 2013-04-24 吴华 Test sorter for minimal type semiconductor devices
CN103376340A (en) * 2013-07-04 2013-10-30 曙光信息产业(北京)有限公司 Adapter plate, a multi-platform serial test system and method
CN103558543A (en) * 2013-11-20 2014-02-05 太仓思比科微电子技术有限公司 Mass production testing method of CIS chip
CN203965471U (en) * 2014-05-14 2014-11-26 深圳安博电子有限公司 Testing apparatus and communication device thereof
CN104198868A (en) * 2014-09-23 2014-12-10 厦门雅迅网络股份有限公司 Intelligent tool capable of being flexibly expanded and dynamically configured

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020183954A1 (en) * 2001-05-30 2002-12-05 Sumitomo Wiring Systems, Ltd. Processing system for a wiring harness, a method for testing an electrical connection of a wiring harness, computer-readable storage medium and a wire connection assisting system
CN101030159A (en) * 2006-02-28 2007-09-05 环达电脑(上海)有限公司 Apparatus and system for testing host slot
CN102172107A (en) * 2008-10-09 2011-08-31 株式会社爱德万测试 Circuit board, circuit board assembly and misinsertion detecting device
CN102854455A (en) * 2012-09-21 2013-01-02 成都市中州半导体科技有限公司 Integrated circuit testing system and control method for same
CN202893706U (en) * 2012-11-17 2013-04-24 吴华 Test sorter for minimal type semiconductor devices
CN103376340A (en) * 2013-07-04 2013-10-30 曙光信息产业(北京)有限公司 Adapter plate, a multi-platform serial test system and method
CN103558543A (en) * 2013-11-20 2014-02-05 太仓思比科微电子技术有限公司 Mass production testing method of CIS chip
CN203965471U (en) * 2014-05-14 2014-11-26 深圳安博电子有限公司 Testing apparatus and communication device thereof
CN104198868A (en) * 2014-09-23 2014-12-10 厦门雅迅网络股份有限公司 Intelligent tool capable of being flexibly expanded and dynamically configured

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110314864A (en) * 2018-03-28 2019-10-11 北京君正集成电路股份有限公司 Chip detecting method and device based on manipulator
CN110320427A (en) * 2018-03-28 2019-10-11 北京君正集成电路股份有限公司 Chip detecting method and device
CN110320457A (en) * 2018-03-28 2019-10-11 北京君正集成电路股份有限公司 Chip grabs control method and device
CN110320459A (en) * 2018-03-28 2019-10-11 北京君正集成电路股份有限公司 Chip automated testing method and device
CN110320458A (en) * 2018-03-28 2019-10-11 北京君正集成电路股份有限公司 Automate chip test system
CN108829080A (en) * 2018-05-18 2018-11-16 广州益为科技有限公司 A kind of high-end environment-protecting clean robot
CN111871865A (en) * 2020-06-30 2020-11-03 绍兴网策科技有限公司 Integrated circuit testing device and testing method
CN111871865B (en) * 2020-06-30 2021-08-13 绍兴网策科技有限公司 Integrated circuit testing device and testing method
CN112444730A (en) * 2020-10-15 2021-03-05 绍兴网策科技有限公司 Fool-proof method for multi-Site mode testing device and fool-proof method for testing machine
CN113578781A (en) * 2021-07-26 2021-11-02 北京比特大陆科技有限公司 Chip sorting method, device, equipment and storage medium
CN113578781B (en) * 2021-07-26 2023-07-25 北京比特大陆科技有限公司 Chip sorting method, device, equipment and storage medium
CN113828548A (en) * 2021-11-26 2021-12-24 南京派格测控科技有限公司 Radio frequency chip testing device and method
CN114247664A (en) * 2021-12-27 2022-03-29 厦门科塔电子有限公司 Chip FT test system and method integrating sorting and testing

Similar Documents

Publication Publication Date Title
CN105467256A (en) Chip testing and sorting method
CN105717439B (en) Chip detecting method and system
CN101949990B (en) IC pin open short circuit test method
CN105116317A (en) Integrated circuit test system and method
CN106888060B (en) Anti-interference test method and system for wireless communication module
US10782348B2 (en) Automatic device detection and connection verification
CN108181570B (en) Chip grounding pin connectivity test method and device and readable storage medium
CN112444730A (en) Fool-proof method for multi-Site mode testing device and fool-proof method for testing machine
CN103777131A (en) Integrated circuit testing system and integrated circuit testing method
CN105866654A (en) Wafer test control method
CN104678289A (en) Method for calibrating setting values and measurement values in shmoo test
CN111293048A (en) Wafer test system and method thereof
CN109633417A (en) Multi-chip is the same as geodesic structure and method
CN103888885A (en) Miniature microphone capacitance test method
TW200404161A (en) Method and apparatus for characterizing board test coverage
CN104124235B (en) Testing structure and testing method implemented by same
US10393790B2 (en) Method for testing connectivity
WO2021088735A1 (en) Link detection method and apparatus, electronic device, and computer-readable medium
CN109013402B (en) Semiconductor test system, test sorting machine and test machine
CN106449464A (en) Wafer testing method
US6594797B1 (en) Methods and circuits for precise edge placement of test signals
CN105118795A (en) Wafer test method
CN104869580A (en) Radio frequency automation test system and method
CN103592613B (en) Test rectifier, test system and method for testing
CN113539350A (en) ATE equipment self-checking based method and system

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20160406