CN110320458A - Automate chip test system - Google Patents
Automate chip test system Download PDFInfo
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- CN110320458A CN110320458A CN201810262985.3A CN201810262985A CN110320458A CN 110320458 A CN110320458 A CN 110320458A CN 201810262985 A CN201810262985 A CN 201810262985A CN 110320458 A CN110320458 A CN 110320458A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
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Abstract
The present invention provides a kind of automation chip test systems, comprising: grabbing device, test device, controller, wherein chip under test is placed in the test device, for testing chip under test；The grabbing device, for putting according to test result information to target position after the completion of chip under test test；The controller is connected with the grabbing device and the test device, for controlling the grabbing device and the test device.It solves the technical problem that testing efficiency in the presence of existing chip testing mode is low, test result accuracy is low through the above scheme, has reached the technical effect for effectively improving testing efficiency and test accuracy.
Description
Technical field
The present invention relates to equipment control technology field, in particular to a kind of automation chip test system.
Background technique
Chip after packaging is accomplished, generally can all test it, to separate non-defective unit and defective products.Existing core
The mode of manual testing is usually used in chip test method.2~3 tests of setting usually in face of each tester
Platform, the information (such as: indicator light green represents non-defective unit, and red represents defective products) of the indicator light by manually checking testboard into
Row test, to judge whether chip under test is non-defective unit.
This test mode not only inefficiency, but also manually in taking and placing chip it is also possible to chip is misplaced, it causes
Non-defective unit and defective products are obscured, and testing cost is higher.
The low problem of inefficiency present in mode for existing manual testing's chip, accuracy rate, at present not yet
It puts forward effective solutions.
Summary of the invention
The embodiment of the invention provides a kind of automation chip test systems, to reach the chip testing of efficient high-accuracy
Purpose, which includes: grabbing device, test device, controller, wherein
It is placed with chip under test in the test device, for testing chip under test；
The grabbing device, for putting according to test result information to target position after the completion of chip under test test
It sets；
The controller is connected with the grabbing device and the test device, for the grabbing device and described
Test device is controlled.
In one embodiment, the grabbing device is manipulator.
In one embodiment, above system further include: status latch, with the test device and the controller
It is connected, test is tied for receiving the test result information from the test device, and in response to the control of the controller
Fruit information is latched.
In one embodiment, above system further include: level translator is connected with the test device, for pair
Level conversion is carried out from the grabbing device or the signal for being sent to the grabbing device.
In one embodiment, the level translator is used to be converted to the signal of TTL_3.3V the letter of TTL_5V
Number, alternatively, the signal of TTL_5V to be converted to the signal of TTL_3.3V.
In one embodiment, the target position is classification box.
In one embodiment, the classification box includes: the first classification box and the second classification box, wherein described first
Classification box is used to place the chip that test passes through, and second classification box tests unsanctioned chip for placing.
In embodiments of the present invention, chip testing process is initiated by manipulator, and after completion of testing, manipulator is logical
Cross test result by chip under test put to need put to position, to complete chip automatic test.It solves through the above scheme
The technical problem that testing efficiency in the presence of existing chip testing mode of having determined is low, test result accuracy is low, reaches
Effectively improve the technical effect of testing efficiency and test accuracy.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, not
Constitute limitation of the invention.In the accompanying drawings:
Fig. 1 is the structural block diagram of automation chip test system according to an embodiment of the present invention；
Fig. 2 is another structural block diagram of automation chip test system according to an embodiment of the present invention；
Fig. 3 is chip automated testing method flow chart according to an embodiment of the present invention；
Fig. 4 is transport stream signal schematic diagram according to an embodiment of the present invention；
Fig. 5 is signal level timing diagram according to an embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, right below with reference to embodiment and attached drawing
The present invention is described in further details.Here, exemplary embodiment and its explanation of the invention is used to explain the present invention, but simultaneously
It is not as a limitation of the invention.
In view of existing chip detecting method there are the testing efficiencies not high technical problem of low, accuracy rate, in this example
A kind of automation chip test system is provided, improves the accurate of testing efficiency and test result by automating chip testing
Property.As shown in Figure 1, the automation chip test system may include: grabbing device 101, test device 102, controller 103,
Wherein:
It is placed with chip under test in test device 102, for testing chip under test 10；
Grabbing device 101, for putting according to test result information to target position after the completion of chip under test test
It sets；
Controller 103 is connected with grabbing device 101 and test device 102, for grabbing device 101 and test device
102 are controlled.
Specifically, above-mentioned test device 102 can be plate of a station or a placement thing etc. all
It can be with as long as chip under test 10 can be placed.
In one embodiment, above-mentioned grabbing device 101 can be manipulator, that is, can with the manipulator of grab chips,
By control, it can control 101 grab chips of grabbing device, put to target position.
In order to realize the latch of data, that is, latched to the test result of chip under test, above-mentioned test macro can be with
Include: status latch, be connected with test device 102 and controller 103, for receiving the test knot for carrying out self-test device 102
Fruit information, and test result information is latched in response to the control of the controller 103.Wherein, for specifically testing
As a result it can be the test result that chip selftest obtains, which can be sent to status latch.
In view of realize when because the signal generally sent out from manipulator be it is low level, it is also only possible to connect
It receives low level.Therefore, a level shifting circuit can be set, so that the conversion of signal level is realized, to guarantee manipulator
The effective data transmission between other parts of appliance.It is and described that is, above-mentioned test macro can also include: level translator
Test device (or chip under test) is connected, for from the grabbing device or be sent to the signal of the grabbing device into
Line level conversion.
Specifically, above-mentioned level translator can be used for being converted to the signal of TTL_3.3V the signal of TTL_5V, alternatively,
The signal of TTL_5V is converted to the signal of TTL_3.3V.
Above-mentioned target position can be classification box, for example, can be as shown in Fig. 2, the classification box may include: first point
Class box 201 and the second classification box 202, wherein the chip that first classification box 201 passes through for placing test, described second
Classification box 202 tests unsanctioned chip for placing.
Based on above-mentioned test macro, a kind of test method is additionally provided, as shown in figure 3, may include steps of:
S301: manipulator sends test commencing signal to controller (or control logic)；
S302: commencing signal is sent to chip under test by controller, is tested with triggering chip under test；
S303: chip under test sends testing end signal after the completion of test, to controller；
S304: controller sends testing end signal in response to testing end signal, to manipulator；
S305: manipulator obtains the test result information of the chip under test in response to testing end signal；
S306: manipulator puts chip under test into sorter according to the test result information.
Specifically, for device processed in response to testing end signal, sending test to manipulator terminates letter in above-mentioned steps S304
Number may include:
S1: the testing end signal of controller reception TTL_3.3V；
S2: the testing end signal of the TTL_3.3V is converted to the testing end signal of TTL_5V by controller；
S3: the testing end signal of the TTL_5V is sent to the manipulator by controller.
That is, controller first carries out level conversion to testing end signal, it is converted into manipulator acceptable signal,
Then manipulator is sent to, again to inform that manipulator test is completed.
In above-mentioned steps S306, the chip under test is put to classification and is filled according to the test result information by manipulator
In setting, may include:
S1: manipulator judges whether the chip under test passes through test according to the test result information；
S2: in the case where determining through test, the chip under test is put to point for being used to place test by chip
Class device；
S3: determine not by test in the case where, by the chip under test put to be used to place test do not pass through chip
Sorter.
That is, two specification areas of setting, a specification area is used to place the chip that test passes through, a classification
Unsanctioned chip is tested for placing in region.In this way by a set of testing process, test the chip passed through will be put to
In holding in the device that test passes through chip, testing unsanctioned chip will be put to for holding test not by chip
In device.The technical issues of eliminating the classification error as caused by human factor by this mode classification has reached simple
It efficiently realizes sorting chips, improves the technical effect of classification results accuracy.
In one embodiment, the test result of chip can be sent to manipulator by status latch.Specifically,
In chip under test after the completion of test, after sending testing end signal to controller, chip under test can believe test result
Breath is sent to status latch；Then, status latch latches test result information, and test result information is sent
To manipulator.
Specifically, test result information be sent to manipulator may include:
S1: status latch, by the test result information of TTL_3.3V, is converted to TTL_5V's by level shifting circuit
Test result information；
S2: the test result information of TTL_5V is sent to manipulator.
For said chip test macro, may include: based on the description of controller side
S1: controller receives chip under test after the completion of test, the testing end signal of return；
S2: controller sends lower electric enable signal to the chip under test；
S3: controller sends testing end signal to manipulator, wherein the testing end signal is for controlling the machine
Tool hand places the chip under test according to the test result information of the chip under test.
Specifically, chip under test is received after the completion of test in controller, it, can be with after the testing end signal of return
Latch signal is sent to status latch, wherein the latch signal is for controlling the status latch to the tested core
The test result information that piece issues is latched.
May include: based on the description of chip under test side
S1: it receives and powers on enable signal from controller；
S2: it is tested in response to the enable signal chip under test that powers on；
S3: after the completion of test, chip under test sends testing end signal and test result information to the controller；
S4: the lower electric enable signal that the controller is issued in response to the testing end signal is received.
Above-mentioned steps S4 receive lower electric enable signal that the controller is issued in response to the testing end signal it
Afterwards, chip under test will be placed into sorter corresponding with test result information.
Wherein, above-mentioned test result information may include following one: test passes through, tests and do not pass through.
The above-mentioned signal for powering on the TTL_5V that enable signal can be issued with manipulator, but level translator can be first passed through and turned
It is changed to the signal of TTL_3.3V, is then transferred into chip under test again.
Above-mentioned chip under test can be the chip after encapsulation.
May include: based on manipulator side description
S1: manipulator sends test commencing signal；
S2: the testing end signal that chip under test is returned in response to the test commencing signal is received；
S3: manipulator transfers test result information in response to the testing end signal, and is believed according to the test result
Breath puts the chip under test to target position.
It can wrap specifically, manipulator puts the chip under test to the target position according to the test result information
Include: manipulator obtains the test result information, judges whether the chip under test passes through test according to test result information；?
In the case where determining through test, the chip under test is put into the sorter passed through corresponding to test；Do not lead in determination
In the case where crossing test, the chip under test is put into corresponding to the unsanctioned sorter of test.
Above-mentioned test commencing signal is the signal of TTL_5V.Chip under test is put to the target position and be can wrap by manipulator
Include: manipulator picks up the chip under test, and chip under test is put to the target position.Manipulator transfers test result information can
The test result information is read from status latch to include: manipulator.
Above-mentioned chip test system and method are illustrated below with reference to a specific embodiment, however, being worth note
Meaning, the specific embodiment do not constitute an undue limitation on the present application merely to the application is better described.
In this example, provide a kind of automatic method of test chip, for example, can by mechanical arm grab chips with
It is tested.Based on this, it can establish the method that a set of pair of mechanical arm is controlled, allow mechanical arm according to correct
Testing process grab chips and tested, to reach raising testing efficiency, improve test accuracy, reduce testing cost
Effect.
As shown in figure 4, when chip testing starts, manipulator can issue " beginning " signal (can be one it is low
Level signal), for example, it may be TTL_5V fiduciary level signal.In view of the signal and tested core for needing to issue on manipulator
The level of piece is matched, and " beginning " signal can be reduced to TTL_3.3V level standard.
In order to which signal is reduced to TTL_3.3V level standard by TTL_5V fiduciary level signal, a level can be increased
Conversion circuit.Level signal after conversion enters control logic, and control logic after receipt of the signal, can be to tested core
Piece issues one and powers on enable signal, and chip under test starts to be tested after receiving and powering on enable signal.
After the completion of test, chip under test returns to test mode information, and returns to testing end signal to control logic.Control
After logic processed receives testing end signal, latch signal is issued to status latch, lower electricity can be issued to chip under test later
Enable signal.After status latch receives the latch signal of control logic sending, by the test mode information of chip under test sending
It is latched, and test mode information is changed into TTL_5V level by level shifting circuit and is sent to manipulator.At the same time,
Control logic issues the testing end signal of TTL_3.3V level, and the test of TTL_5V level is converted by level shifting circuit
End signal is sent to manipulator.Manipulator is inquired test mode information, will be tested later after receiving testing end signal
Chip is picked up, and classifies chip under test according to test mode information.As shown in figure 5, being signal level timing diagram.
It can be seen from the above description that the embodiment of the present invention realizes following technical effect: being initiated by manipulator
Chip testing process, and after completion of testing, manipulator by test result by chip under test put to need to put to position,
To complete chip automatic test.Solves the testing efficiency in the presence of existing chip testing mode through the above scheme
Technical problem low, test result accuracy is low has reached the technical effect for effectively improving testing efficiency and test accuracy.
In the present specification, such as adjective as first and second can be only used for by an element or movement with it is another
One element or movement distinguish, without requiring or implying any actual this relationship or sequence.In the feelings that environment allows
Under condition, one in only element, component or step should not be interpreted as limited to referring to element or component or step (s), and can
To be the one or more etc. in element, component or step.
Obviously, those skilled in the art should be understood that each module of the above-mentioned embodiment of the present invention or each step can be with
It is realized with general computing device, they can be concentrated on a single computing device, or be distributed in multiple computing devices
On composed network, optionally, they can be realized with the program code that computing device can perform, it is thus possible to by it
Store and be performed by computing device in the storage device, and in some cases, can be held with the sequence for being different from herein
The shown or described step of row, perhaps they are fabricated to each integrated circuit modules or will be multiple in them
Module or step are fabricated to single integrated circuit module to realize.In this way, the embodiment of the present invention be not limited to it is any specific hard
Part and software combine.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the embodiment of the present invention can have various modifications and variations.All within the spirits and principles of the present invention, made
Any modification, equivalent substitution, improvement and etc. should all be included in the protection scope of the present invention.
Claims (7)
1. a kind of automation chip test system characterized by comprising grabbing device, test device, controller, wherein
It is placed with chip under test in the test device, for testing chip under test；
The grabbing device, for putting according to test result information to target position after the completion of chip under test test；
The controller is connected with the grabbing device and the test device, for the grabbing device and the test
Device is controlled.
2. system according to claim 1, which is characterized in that the grabbing device is manipulator.
3. system according to claim 1, which is characterized in that further include: status latch, with the test device and institute
It states controller to be connected, for receiving the test result information from the test device, and in response to the control of the controller
Test result information is latched.
4. system according to claim 1, which is characterized in that further include: level translator, with the test device phase
Even, for from the grabbing device or be sent to the grabbing device signal carry out level conversion.
5. system according to claim 4, which is characterized in that the level translator is used to turn the signal of TTL_3.3V
It is changed to the signal of TTL_5V, alternatively, the signal of TTL_5V to be converted to the signal of TTL_3.3V.
6. system according to claim 1, which is characterized in that the target position is classification box.
7. system according to claim 6, which is characterized in that the classification box includes: the first classification box and the second classification
Box, wherein first classification box is used to place the chip that test passes through, and second classification box does not pass through for placing test
Chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810262985.3A CN110320458A (en) | 2018-03-28 | 2018-03-28 | Automate chip test system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810262985.3A CN110320458A (en) | 2018-03-28 | 2018-03-28 | Automate chip test system |
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| CN110320458A true CN110320458A (en) | 2019-10-11 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103341452A (en) * | 2013-07-25 | 2013-10-09 | 肇庆爱晟电子科技有限公司 | Test separator for NTC (negative temperature coefficient) heat-sensitive chips |
| CN104459518A (en) * | 2014-11-27 | 2015-03-25 | 北京时代民芯科技有限公司 | Function automation testing system and testing method based on SoPC chip |
| CN105467256A (en) * | 2015-05-14 | 2016-04-06 | 华润赛美科微电子(深圳)有限公司 | Chip testing and sorting method |
| CN205199969U (en) * | 2015-10-30 | 2016-05-04 | 广东利扬芯片测试股份有限公司 | Can realize automatic classification's after chip testing test equipment |
| CN206804822U (en) * | 2017-03-21 | 2017-12-26 | 深圳市华宇半导体有限公司 | Bank safety chip automatization test system |
-
2018
- 2018-03-28 CN CN201810262985.3A patent/CN110320458A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103341452A (en) * | 2013-07-25 | 2013-10-09 | 肇庆爱晟电子科技有限公司 | Test separator for NTC (negative temperature coefficient) heat-sensitive chips |
| CN104459518A (en) * | 2014-11-27 | 2015-03-25 | 北京时代民芯科技有限公司 | Function automation testing system and testing method based on SoPC chip |
| CN105467256A (en) * | 2015-05-14 | 2016-04-06 | 华润赛美科微电子(深圳)有限公司 | Chip testing and sorting method |
| CN205199969U (en) * | 2015-10-30 | 2016-05-04 | 广东利扬芯片测试股份有限公司 | Can realize automatic classification's after chip testing test equipment |
| CN206804822U (en) * | 2017-03-21 | 2017-12-26 | 深圳市华宇半导体有限公司 | Bank safety chip automatization test system |
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