CN110314864A - Chip detecting method and device based on manipulator - Google Patents
Chip detecting method and device based on manipulator Download PDFInfo
- Publication number
- CN110314864A CN110314864A CN201810263221.6A CN201810263221A CN110314864A CN 110314864 A CN110314864 A CN 110314864A CN 201810263221 A CN201810263221 A CN 201810263221A CN 110314864 A CN110314864 A CN 110314864A
- Authority
- CN
- China
- Prior art keywords
- test
- manipulator
- chip under
- chip
- under test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
- B07C5/02—Measures preceding sorting, e.g. arranging articles in a stream orientating
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
- B07C5/34—Sorting according to other particular properties
- B07C5/344—Sorting according to other particular properties according to electric or electromagnetic properties
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
- B07C5/36—Sorting apparatus characterised by the means used for distribution
- B07C5/361—Processing or control devices therefor, e.g. escort memory
- B07C5/362—Separating or distributor mechanisms
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The present invention provides a kind of chip detecting method and device based on manipulator, wherein this method comprises: manipulator sends test commencing signal；Receive the testing end signal that chip under test is returned in response to the test commencing signal；The manipulator transfers test result information in response to the testing end signal, and is put the chip under test to target position according to the test result information.It solves the technical problem that testing efficiency in the presence of existing chip testing mode is low, test result accuracy is low through the above scheme, has reached the technical effect for effectively improving testing efficiency and test accuracy.
Description
Technical field
The present invention relates to equipment control technology field, in particular to a kind of chip detecting method and dress based on manipulator
It sets.
Background technique
Chip after packaging is accomplished, generally can all test it, to separate non-defective unit and defective products.Existing core
The mode of manual testing is usually used in chip test method.2~3 tests of setting usually in face of each tester
Platform, the information (such as: indicator light green represents non-defective unit, and red represents defective products) of the indicator light by manually checking testboard into
Row test, to judge whether chip under test is non-defective unit.
This test mode not only inefficiency, but also manually in taking and placing chip it is also possible to chip is misplaced, it causes
Non-defective unit and defective products are obscured, and testing cost is higher.
The low problem of inefficiency present in mode for existing manual testing's chip, accuracy rate, at present not yet
It puts forward effective solutions.
Summary of the invention
The embodiment of the invention provides a kind of chip detecting methods based on manipulator, to reach the core of efficient high-accuracy
The purpose of built-in testing, this method comprises:
Manipulator sends test commencing signal；
Receive the testing end signal that chip under test is returned in response to the test commencing signal；
The manipulator transfers test result information in response to the testing end signal, and according to the test result
Information puts the chip under test to target position.
In one embodiment, the manipulator puts the chip under test to described according to the test result information
Target position includes:
The manipulator obtains the test result information；
Judge whether the chip under test passes through test according to the test result information；
In the case where determining through test, the chip under test is put into the sorter passed through corresponding to test；
In the case where determining not through test, the chip under test is put to corresponding to the unsanctioned sorter of test
In.
In one embodiment, the signal that the test commencing signal is TTL_5V.
In one embodiment, the manipulator, which puts the chip under test to the target position, includes:
The manipulator picks up the chip under test；
The chip under test is put to the target position.
In one embodiment, the manipulator transfers test result information and includes:
The manipulator reads the test result information from status latch.
The embodiment of the invention also provides a kind of apparatus for testing chip based on manipulator, are located in manipulator, to reach
The purpose of the chip testing of efficient high-accuracy, the device include:
Sending module, for sending test commencing signal；
Receiving module, the testing end signal returned for receiving chip under test in response to the test commencing signal；
Processing module for transferring test result information in response to the testing end signal, and is tied according to the test
Fruit information puts the chip under test to target position.
In one embodiment, the processing module includes:
Acquiring unit, for obtaining the test result information；
Judging unit, for judging whether the chip under test passes through test according to the test result information；
First processing units, in the case where determining through test, the chip under test to be put to corresponding to test
By sorter in；
The second processing unit is used to put the chip under test to corresponding to survey in the case where determining not through test
It tries in unsanctioned sorter.
In one embodiment, the signal that the test commencing signal is TTL_5V.
In one embodiment, the processing module is specifically used for picking up the chip under test, by the chip under test
It puts to the target position.
In one embodiment, the processing module is specifically used for reading the test result letter from status latch
Breath.
In embodiments of the present invention, chip testing process is initiated by manipulator, and after completion of testing, manipulator is logical
Cross test result by chip under test put to need put to position, to complete chip automatic test.It solves through the above scheme
The technical problem that testing efficiency in the presence of existing chip testing mode of having determined is low, test result accuracy is low, reaches
Effectively improve the technical effect of testing efficiency and test accuracy.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, not
Constitute limitation of the invention.In the accompanying drawings:
Fig. 1 is the structural block diagram of automation chip test system according to an embodiment of the present invention；
Fig. 2 is another structural block diagram of automation chip test system according to an embodiment of the present invention；
Fig. 3 is chip automated testing method flow chart according to an embodiment of the present invention；
Fig. 4 is transport stream signal schematic diagram according to an embodiment of the present invention；
Fig. 5 is signal level timing diagram according to an embodiment of the present invention；
Fig. 6 is the structural block diagram of the apparatus for testing chip according to an embodiment of the present invention based on manipulator.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, right below with reference to embodiment and attached drawing
The present invention is described in further details.Here, exemplary embodiment and its explanation of the invention is used to explain the present invention, but simultaneously
It is not as a limitation of the invention.
In view of existing chip detecting method there are the testing efficiencies not high technical problem of low, accuracy rate, in this example
A kind of automation chip test system is provided, improves the accurate of testing efficiency and test result by automating chip testing
Property.As shown in Figure 1, the automation chip test system may include: grabbing device 101, test device 102, controller 103,
Wherein:
It is placed with chip under test in test device 102, for testing chip under test 10；
Grabbing device 101, for putting according to test result information to target position after the completion of chip under test test
It sets；
Controller 103 is connected with grabbing device 101 and test device 102, for grabbing device 101 and test device
102 are controlled.
Specifically, above-mentioned test device 102 can be plate of a station or a placement thing etc. all
It can be with as long as chip under test 10 can be placed.
In one embodiment, above-mentioned grabbing device 101 can be manipulator, that is, can with the manipulator of grab chips,
By control, it can control 101 grab chips of grabbing device, put to target position.
In order to realize the latch of data, that is, latched to the test result of chip under test, above-mentioned test macro can be with
Include: status latch, be connected with test device 102 and controller 103, for receiving the test knot for carrying out self-test device 102
Fruit information, and test result information is latched in response to the control of the controller 103.Wherein, for specifically testing
As a result it can be the test result that chip selftest obtains, which can be sent to status latch.
In view of realize when because the signal generally sent out from manipulator be it is low level, it is also only possible to connect
It receives low level.Therefore, a level shifting circuit can be set, so that the conversion of signal level is realized, to guarantee manipulator
The effective data transmission between other parts of appliance.It is and described that is, above-mentioned test macro can also include: level translator
Test device (or chip under test) is connected, for from the grabbing device or be sent to the signal of the grabbing device into
Line level conversion.
Specifically, above-mentioned level translator can be used for being converted to the signal of TTL_3.3V the signal of TTL_5V, alternatively,
The signal of TTL_5V is converted to the signal of TTL_3.3V.
Above-mentioned target position can be classification box, for example, can be as shown in Fig. 2, the classification box may include: first point
Class box 201 and the second classification box 202, wherein the chip that first classification box 201 passes through for placing test, described second
Classification box 202 tests unsanctioned chip for placing.
Based on above-mentioned test macro, a kind of test method is additionally provided, as shown in figure 3, may include steps of:
S301: manipulator sends test commencing signal to controller (or control logic)；
S302: commencing signal is sent to chip under test by controller, is tested with triggering chip under test；
S303: chip under test sends testing end signal after the completion of test, to controller；
S304: controller sends testing end signal in response to testing end signal, to manipulator；
S305: manipulator obtains the test result information of the chip under test in response to testing end signal；
S306: manipulator puts chip under test into sorter according to the test result information.
Specifically, in response to testing end signal, send test to manipulator terminates controller in above-mentioned steps S304
Signal may include:
S1: the testing end signal of controller reception TTL_3.3V；
S2: the testing end signal of the TTL_3.3V is converted to the testing end signal of TTL_5V by controller；
S3: the testing end signal of the TTL_5V is sent to the manipulator by controller.
That is, controller first carries out level conversion to testing end signal, it is converted into manipulator acceptable signal,
Then manipulator is sent to, again to inform that manipulator test is completed.
In above-mentioned steps S306, the chip under test is put to classification and is filled according to the test result information by manipulator
In setting, may include:
S1: manipulator judges whether the chip under test passes through test according to the test result information；
S2: in the case where determining through test, the chip under test is put to point for being used to place test by chip
Class device；
S3: determine not by test in the case where, by the chip under test put to be used to place test do not pass through chip
Sorter.
That is, two specification areas of setting, a specification area is used to place the chip that test passes through, a classification
Unsanctioned chip is tested for placing in region.In this way by a set of testing process, test the chip passed through will be put to
In holding in the device that test passes through chip, testing unsanctioned chip will be put to for holding test not by chip
In device.The technical issues of eliminating the classification error as caused by human factor by this mode classification has reached simple
It efficiently realizes sorting chips, improves the technical effect of classification results accuracy.
In one embodiment, the test result of chip can be sent to manipulator by status latch.Specifically,
In chip under test after the completion of test, after sending testing end signal to controller, chip under test can believe test result
Breath is sent to status latch；Then, status latch latches test result information, and test result information is sent
To manipulator.
Specifically, test result information be sent to manipulator may include:
S1: status latch, by the test result information of TTL_3.3V, is converted to TTL_5V's by level shifting circuit
Test result information；
S2: the test result information of TTL_5V is sent to manipulator.
For said chip test macro, may include: based on the description of controller side
S1: controller receives chip under test after the completion of test, the testing end signal of return；
S2: controller sends lower electric enable signal to the chip under test；
S3: controller sends testing end signal to manipulator, wherein the testing end signal is for controlling the machine
Tool hand places the chip under test according to the test result information of the chip under test.
Specifically, chip under test is received after the completion of test in controller, it, can be with after the testing end signal of return
Latch signal is sent to status latch, wherein the latch signal is for controlling the status latch to the tested core
The test result information that piece issues is latched.
May include: based on the description of chip under test side
S1: it receives and powers on enable signal from controller；
S2: it is tested in response to the enable signal chip under test that powers on；
S3: after the completion of test, chip under test sends testing end signal and test result information to the controller；
S4: the lower electric enable signal that the controller is issued in response to the testing end signal is received.
Above-mentioned steps S4 receive lower electric enable signal that the controller is issued in response to the testing end signal it
Afterwards, chip under test will be placed into sorter corresponding with test result information.
Wherein, above-mentioned test result information may include following one: test passes through, tests and do not pass through.
The above-mentioned signal for powering on enable signal and can be the TTL_5V of manipulator sending, but level translator can be first passed through
The signal for being converted to TTL_3.3V, is then transferred into chip under test again.
Above-mentioned chip under test can be the chip after encapsulation.
May include: based on manipulator side description
S1: manipulator sends test commencing signal；
S2: the testing end signal that chip under test is returned in response to the test commencing signal is received；
S3: manipulator transfers test result information in response to the testing end signal, and is believed according to the test result
Breath puts the chip under test to target position.
It can wrap specifically, manipulator puts the chip under test to the target position according to the test result information
Include: manipulator obtains the test result information, judges whether the chip under test passes through test according to test result information；?
In the case where determining through test, the chip under test is put into the sorter passed through corresponding to test；Do not lead in determination
In the case where crossing test, the chip under test is put into corresponding to the unsanctioned sorter of test.
Above-mentioned test commencing signal is the signal of TTL_5V.Chip under test is put to the target position and be can wrap by manipulator
Include: manipulator picks up the chip under test, and chip under test is put to the target position.Manipulator transfers test result information can
The test result information is read from status latch to include: manipulator.
Above-mentioned chip test system and method are illustrated below with reference to a specific embodiment, however, being worth note
Meaning, the specific embodiment do not constitute an undue limitation on the present application merely to the application is better described.
In this example, provide a kind of automatic method of test chip, for example, can by mechanical arm grab chips with
It is tested.Based on this, it can establish the method that a set of pair of mechanical arm is controlled, allow mechanical arm according to correct
Testing process grab chips and tested, to reach raising testing efficiency, improve test accuracy, reduce testing cost
Effect.
When chip testing starts, manipulator can issue " beginning " signal (can be a low level signal),
For example, it may be TTL_5V fiduciary level signal.In view of need by manipulator issue signal and chip under test level into
Row matching, can be reduced to TTL_3.3V level standard for " beginning " signal.
In order to which signal is reduced to TTL_3.3V level standard by TTL_5V fiduciary level signal, a level can be increased
Conversion circuit.Level signal after conversion enters control logic, and control logic after receipt of the signal, can be to tested core
Piece issues one and powers on enable signal, and chip under test starts to be tested after receiving and powering on enable signal.
After the completion of test, chip under test returns to test mode information, and returns to testing end signal to control logic.Control
After logic processed receives testing end signal, latch signal is issued to status latch, lower electricity can be issued to chip under test later
Enable signal.After status latch receives the latch signal of control logic sending, by the test mode information of chip under test sending
It is latched, and test mode information is changed into TTL_5V level by level shifting circuit and is sent to manipulator.At the same time,
Control logic issues the testing end signal of TTL_3.3V level, and the test of TTL_5V level is converted by level shifting circuit
End signal is sent to manipulator.Manipulator is inquired test mode information, will be tested later after receiving testing end signal
Chip is picked up, and classifies chip under test according to test mode information.
Based on the same inventive concept, a kind of apparatus for testing chip based on manipulator is additionally provided in the embodiment of the present invention,
As described in the following examples.The principle solved the problems, such as due to the apparatus for testing chip based on manipulator with based on the core of manipulator
Chip test method is similar, therefore the implementation of the apparatus for testing chip based on manipulator may refer to the chip testing based on manipulator
The implementation of method, overlaps will not be repeated.Used below, predetermined function may be implemented in term " unit " or " module "
Software and/or hardware combination.Although device described in following embodiment is preferably realized with software, hardware,
Or the realization of the combination of software and hardware is also that may and be contemplated.Fig. 6 is the embodiment of the present invention based on manipulator
A kind of structural block diagram of apparatus for testing chip is located in manipulator, as shown in fig. 6, may include: sending module 601, receiving mould
Block 602 and processing module 603, are below illustrated the structure.
Sending module 601, for sending test commencing signal；
Receiving module 602, the testing end signal returned for receiving chip under test in response to the test commencing signal；
Processing module 603, for transferring test result information, and according to the survey in response to the testing end signal
Test result information puts the chip under test to target position.
In one embodiment, processing module 603 may include: acquiring unit, for obtaining the test result letter
Breath；Judging unit, for judging whether the chip under test passes through test according to the test result information；First processing is single
Member, in the case where determining through test, the chip under test to be put into the sorter passed through corresponding to test；The
Two processing units, in the case where determining not through test, the chip under test to be put to unsanctioned corresponding to testing
In sorter.
In one embodiment, the signal that test commencing signal is TTL_5V.
In one embodiment, processing module 603 specifically can be used for picking up the chip under test, by the tested core
Piece is put to the target position.
In one embodiment, processing module 603 specifically can be used for reading the test result from status latch
Information.
In another embodiment, a kind of software is additionally provided, the software is for executing above-described embodiment and preferred reality
Apply technical solution described in mode.
In another embodiment, a kind of storage medium is additionally provided, above-mentioned software is stored in the storage medium, it should
Storage medium includes but is not limited to: CD, floppy disk, hard disk, scratch pad memory etc..
It can be seen from the above description that the embodiment of the present invention realizes following technical effect: being initiated by manipulator
Chip testing process, and after completion of testing, manipulator by test result by chip under test put to need to put to position,
To complete chip automatic test.Solves the testing efficiency in the presence of existing chip testing mode through the above scheme
Technical problem low, test result accuracy is low has reached the technical effect for effectively improving testing efficiency and test accuracy.
In the present specification, such as adjective as first and second can be only used for by an element or movement with it is another
One element or movement distinguish, without requiring or implying any actual this relationship or sequence.In the feelings that environment allows
Under condition, one in only element, component or step should not be interpreted as limited to referring to element or component or step (s), and can
To be the one or more etc. in element, component or step.
Obviously, those skilled in the art should be understood that each module of the above-mentioned embodiment of the present invention or each step can be with
It is realized with general computing device, they can be concentrated on a single computing device, or be distributed in multiple computing devices
On composed network, optionally, they can be realized with the program code that computing device can perform, it is thus possible to by it
Store and be performed by computing device in the storage device, and in some cases, can be held with the sequence for being different from herein
The shown or described step of row, perhaps they are fabricated to each integrated circuit modules or will be multiple in them
Module or step are fabricated to single integrated circuit module to realize.In this way, the embodiment of the present invention be not limited to it is any specific hard
Part and software combine.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the embodiment of the present invention can have various modifications and variations.All within the spirits and principles of the present invention, made
Any modification, equivalent substitution, improvement and etc. should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of chip detecting method based on manipulator characterized by comprising
Manipulator sends test commencing signal；
Receive the testing end signal that chip under test is returned in response to the test commencing signal；
The manipulator transfers test result information in response to the testing end signal, and according to the test result information
The chip under test is put to target position.
2. the method according to claim 1, wherein the manipulator will be described according to the test result information
Chip under test is put to the target position
The manipulator obtains the test result information；
Judge whether the chip under test passes through test according to the test result information；
In the case where determining through test, the chip under test is put into the sorter passed through corresponding to test；
In the case where determining not through test, the chip under test is put into corresponding to the unsanctioned sorter of test.
3. the method according to claim 1, wherein the signal that the test commencing signal is TTL_5V.
4. the method according to claim 1, wherein the manipulator puts the chip under test to the target
Position includes:
The manipulator picks up the chip under test；
The chip under test is put to the target position.
5. the method according to claim 1, wherein the manipulator transfers test result information includes:
The manipulator reads the test result information from status latch.
6. a kind of apparatus for testing chip based on manipulator is located in manipulator characterized by comprising
Sending module, for sending test commencing signal；
Receiving module, the testing end signal returned for receiving chip under test in response to the test commencing signal；
Processing module for transferring test result information in response to the testing end signal, and is believed according to the test result
Breath puts the chip under test to target position.
7. device according to claim 6, which is characterized in that the processing module includes:
Acquiring unit, for obtaining the test result information；
Judging unit, for judging whether the chip under test passes through test according to the test result information；
First processing units, for the chip under test being put to corresponding to test and is passed through in the case where determining through test
Sorter in；
The second processing unit, for determine not by test in the case where, by the chip under test put to correspond to test not
By sorter in.
8. device according to claim 6, which is characterized in that the signal that the test commencing signal is TTL_5V.
9. device according to claim 6, which is characterized in that the processing module is specifically used for picking up the tested core
Piece puts the chip under test to the target position.
10. device according to claim 6, which is characterized in that the processing module is specifically used for reading from status latch
Take the test result information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810263221.6A CN110314864A (en) | 2018-03-28 | 2018-03-28 | Chip detecting method and device based on manipulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810263221.6A CN110314864A (en) | 2018-03-28 | 2018-03-28 | Chip detecting method and device based on manipulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110314864A true CN110314864A (en) | 2019-10-11 |
Family
ID=68109743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810263221.6A Pending CN110314864A (en) | 2018-03-28 | 2018-03-28 | Chip detecting method and device based on manipulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110314864A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111495770A (en) * | 2020-04-22 | 2020-08-07 | 长沙南道电子科技有限公司 | Chip detection device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06293434A (en) * | 1993-04-08 | 1994-10-21 | Seiko Epson Corp | Ic carrying method |
| CN102183726A (en) * | 2011-03-16 | 2011-09-14 | 建荣集成电路科技(珠海)有限公司 | Field programmable gate array (FPGA)-based integrated circuit chip testing system and method |
| CN105467256A (en) * | 2015-05-14 | 2016-04-06 | 华润赛美科微电子(深圳)有限公司 | Chip testing and sorting method |
| CN106205735A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | Embedded chip method of testing and system |
| CN206804822U (en) * | 2017-03-21 | 2017-12-26 | 深圳市华宇半导体有限公司 | Bank safety chip automatization test system |
-
2018
- 2018-03-28 CN CN201810263221.6A patent/CN110314864A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06293434A (en) * | 1993-04-08 | 1994-10-21 | Seiko Epson Corp | Ic carrying method |
| CN102183726A (en) * | 2011-03-16 | 2011-09-14 | 建荣集成电路科技(珠海)有限公司 | Field programmable gate array (FPGA)-based integrated circuit chip testing system and method |
| CN106205735A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | Embedded chip method of testing and system |
| CN105467256A (en) * | 2015-05-14 | 2016-04-06 | 华润赛美科微电子(深圳)有限公司 | Chip testing and sorting method |
| CN206804822U (en) * | 2017-03-21 | 2017-12-26 | 深圳市华宇半导体有限公司 | Bank safety chip automatization test system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111495770A (en) * | 2020-04-22 | 2020-08-07 | 长沙南道电子科技有限公司 | Chip detection device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI266196B (en) | Apparatus and method for testing motherboard having PCI express devices | |
| CN104569794B (en) | A kind of FPGA In-circiut testers and method of testing based on boundary-scan architecture | |
| CN102549443B (en) | Programmable protocol generator | |
| CN105717439A (en) | Chip test method and system | |
| EP2053515A1 (en) | A boundary scan method, system and device | |
| CN204884160U (en) | Ammeter data collection station detecting system | |
| CN102305907A (en) | Test method and system for multichip encapsulating structure | |
| CN109507464A (en) | A kind of electric energy meter power loss event real-time report function automated detection method and device | |
| US20030159124A1 (en) | System and method for generating integrated circuit boundary register description data | |
| CN113578781B (en) | Chip sorting method, device, equipment and storage medium | |
| CN107331421A (en) | A kind of SD card test system and method based on FPGA | |
| US20070136631A1 (en) | Method and system for testing backplanes utilizing a boundary scan protocol | |
| CN101114249A (en) | I2C bus testing apparatus of mainboard and method thereof | |
| CN109470974A (en) | A kind of testing lines system and method based on wireless technology | |
| CN101458305B (en) | Embedded module test and maintenance bus system | |
| CN110314864A (en) | Chip detecting method and device based on manipulator | |
| CN103064011B (en) | Examining system and method in a kind of rfid interrogator chip | |
| CN107340467A (en) | Test system | |
| CN110320427A (en) | Chip detecting method and device | |
| CN110320459A (en) | Chip automated testing method and device | |
| CN106501705B (en) | Draw integrated system protection CPU board automatic checkout system and its detection method | |
| CN110320457A (en) | Chip grabs control method and device | |
| CN110320458A (en) | Automate chip test system | |
| CN207281247U (en) | Circuit board detection equipment | |
| CN114505257B (en) | Material distribution method, material distribution device, terminal equipment and computer readable storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191011 |