CN113539350A - ATE equipment self-checking based method and system - Google Patents
ATE equipment self-checking based method and system Download PDFInfo
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- CN113539350A CN113539350A CN202110673638.1A CN202110673638A CN113539350A CN 113539350 A CN113539350 A CN 113539350A CN 202110673638 A CN202110673638 A CN 202110673638A CN 113539350 A CN113539350 A CN 113539350A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
Abstract
The invention relates to the field of ATE (automatic test equipment), and discloses a method and a system based on ATE self-checking, wherein the method comprises a PC (personal computer) end and a device end to be tested, and the method comprises the steps of generating a test file and generating the test file by the PC end; the PC end executes the test of the equipment end to be tested according to the test case table; testing and checking, wherein the PC side checks the relevant information tested by the equipment side to be tested; judging the test result, judging the test result after verification by the PC side, judging the test case if the test result passes, otherwise, failing the test; and judging the test case, if the test case of the equipment end to be tested is completed by the PC side, the test is successful, otherwise, the test verification of the equipment end to be tested is carried out again. By carrying out self-checking on the ATE equipment, the correctness of an output waveform can be ensured, and the performance meets the test requirement; therefore, the method is beneficial to the stability of the ATE equipment, the automation rate of performance test and the test efficiency.
Description
Technical Field
The invention relates to the field of ATE (automatic test equipment), in particular to a method and a system based on self-checking of ATE.
Background
For ATE (Automatic Test Equipment): a large number of hardware components are integrated, a TMU component can replace an oscilloscope, and a PMU component can replace a multimeter and the like; compatible with a high-level language, and can realize automatic control through programming; any desired stimulus can be easily transmitted.
In ATE digital devices, a multi-channel arbitrary digital waveform generator (DIO) is a functional block of one core. The module can select any channel through software, and the number and the combination form of the digital channels are various. Each channel can independently send any digital waveform meeting the chip test requirement according to the test vector set. And receiving any response waveform of the external chip of the storage device as a basis for identifying whether the tested chip reaches the standard or not.
For example, the patent name, an ATE digital test system and its self-checking method, patent application No.: 201610867908.1, application date: 2016-09-29, an ATE digital test system and its self-checking method, the ATE digital test system, including address generator, graphic memory, instruction memory, self-checking memory and driver, the address generator connects with graphic memory, instruction memory and self-checking memory, the self-checking memory connects with bus, the graphic memory connects with driver.
The prior art can not well verify whether the digital waveform function of any shape generated by ATE equipment is correct or not, can not carry out self-adaptive calibration on the difference of external delay characteristics of the ATE equipment, and can not dynamically adjust verified channel combination; whether the Vector generating the waveform is correct or not; thereby influencing the functions and the performances of the equipment and testing the automation rate.
Disclosure of Invention
Aiming at the problem that the prior art can not well verify whether the function of a digital waveform with any shape generated by ATE equipment per se is correct or not and whether the performance reaches the standard or not; therefore, the defects of equipment function, performance test automation rate and test efficiency are influenced, and the method and the system based on ATE equipment self-checking are provided.
In order to solve the technical problem, the invention is solved by the following technical scheme:
the ATE equipment self-checking method comprises a PC end and an equipment end to be tested,
generating a test file, and generating the test file by the PC terminal;
the PC end executes the test of the equipment end to be tested according to the test case table;
testing and checking, wherein the PC side checks the relevant information tested by the equipment side to be tested;
judging the test result, judging the test result after verification by the PC side, judging the test case if the test result passes, otherwise, failing the test;
and judging the test case, if the test case of the equipment end to be tested is completed by the PC side, the test is successful, otherwise, the test verification of the equipment end to be tested is carried out again.
By carrying out self-checking on the ATE equipment, the correctness of an output waveform can be ensured, and the performance meets the test requirement; therefore, the automation rate and the test efficiency of the ATE equipment function and performance test are improved.
Preferably, channel delay is required before test execution; and the PC side measures the channel delay of the equipment end to be tested, thereby ensuring the synchronism of the channel of the equipment end to be tested. The channel at the end of the equipment to be tested is delayed, so that the synchronism of the data transmission process is ensured.
Preferably, the channel of the device under test end includes a receiving channel and a transmitting channel.
Preferably, the channel is delayed, the PC measures the transmission channel and the reception channel of the device testing end for delay, the reception channel reserves a measurement threshold without level comparison, when the device testing end finishes testing, the transmission channel reserves the same measurement threshold without level comparison, and the measurement threshold is DelayValue/T, where the DelayValue delay value is a T waveform period.
Preferably, the test related information includes data of the test, the number of waveforms tested, and expected error waveforms.
Preferably, the test result judgment includes an execution result judgment, an operation judgment and a failure judgment,
judging the execution result, wherein actual waveform data are acquired by a sampling data channel of the equipment, and are compared and judged with expected waveform data one by one;
judging the operation, namely comparing and judging the number of actually operated vectors of the equipment with the expected number of vectors;
and (4) failure judgment, wherein the number of failed vectors actually operated by the equipment is compared with the expected number of victor failure.
Preferably, the test file includes a pin resource mapping file, a signal group file to be tested, and a waveform definition file.
The ATE equipment self-checking system comprises a PC end, an equipment end to be tested, a test file generation module, a test execution module, a test verification module, a test result judgment module and a test case judgment module;
the test file generation module is used for generating a test file to pass through the PC terminal;
the test execution module is used for executing the test of the equipment terminal to be tested according to the test case table through the PC terminal;
the test checking module is used for checking the relevant information tested by the equipment end to be tested and passing through the PC end;
the test result judging module is used for judging that the verified test result passes through the PC terminal, judging a test case if the test result passes through the PC terminal, and otherwise, failing the test;
and judging the test case, wherein the test is successful when the test case of the equipment end to be tested is completed, and otherwise, the test verification of the equipment end to be tested is carried out again.
Preferably, the system also comprises a channel delay module; the method is used for measuring the PC end by the channel delay of the equipment end to be measured, thereby ensuring the synchronism of the channel of the equipment end to be measured.
Due to the adoption of the technical scheme, the invention has the remarkable technical effects that:
by carrying out self-checking on the ATE equipment, the correctness of an output waveform can be ensured, and the performance meets the test requirement; this is beneficial to improving the function, performance, stability and testing efficiency of ATE equipment.
The invention adjusts the time delay of the receiving channel of the equipment end to be tested, thereby ensuring the synchronism of the data receiving and sending process.
Drawings
FIG. 1 is a system diagram of the present invention.
Fig. 2 is a channel delay diagram of the present invention.
Fig. 3 is a flow chart of the present invention.
Fig. 4 is a diagram of the elements of the waveform generator of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings 1 to 3 and the embodiments.
Example 1
The ATE equipment self-checking method comprises a PC terminal and an equipment terminal to be tested, and the method comprises the steps of generating a test file and generating the test file by the PC terminal; the PC end executes the test of the equipment end to be tested according to the test case table; testing and checking, wherein the PC side checks the relevant information tested by the equipment side to be tested; judging the test result, judging the test result after verification by the PC side, judging the test case if the test result passes, otherwise, failing the test; and judging the test case, if the test case of the equipment end to be tested is completed by the PC side, the test is successful, otherwise, the test verification of the equipment end to be tested is carried out again.
By carrying out self-checking on the ATE equipment, the correctness of an output waveform can be ensured, and the performance meets the test requirement; therefore, the automation rate and the test efficiency of the ATE equipment function and performance test are improved.
The test related information includes the data of the test, the number of waveforms tested and the expected error waveforms.
The test result judgment comprises execution result judgment, operation judgment and failure judgment, the execution result judgment is carried out, actual waveform data are collected by a sampling data channel of the equipment, and the actual waveform data and the expected waveform data are compared and judged one by one; judging the operation, namely comparing and judging the number of actually operated vectors of the equipment with the expected number of vectors; and (4) failure judgment, wherein the number of failed vectors actually operated by the equipment is compared with the expected number of victor failure.
The test files comprise a pin resource mapping file, a signal group file to be tested and a waveform definition file.
Example 2
On the basis of embodiment 1, the channel delay is required before the test is executed in the embodiment; and the PC side measures the channel delay of the equipment end to be tested, thereby ensuring the synchronism of the channel of the equipment end to be tested. The channel at the end of the equipment to be tested is delayed, so that the synchronism of the data transmission process is ensured.
The channel of the device to be tested comprises a receiving channel and a sending channel. And (2) delaying a channel, wherein the PC end measures a sending channel and a receiving channel of the equipment testing end to delay, a reserved measuring threshold of the receiving channel is not compared with the level, when the equipment testing end is tested, the same reserved measuring threshold of the sending channel is not compared with the level, and the measuring threshold is DelayValue/T, wherein the DelayValue delay value is T waveform period.
Example 3
The ATE equipment self-checking system comprises a PC end, an equipment end to be tested, a test file generation module, a test execution module, a test verification module, a test result judgment module and a test case judgment module;
the test file generation module is used for generating a test file to pass through the PC terminal;
the test execution module is used for executing the test of the equipment terminal to be tested according to the test case table through the PC terminal;
the test checking module is used for checking the relevant information tested by the equipment end to be tested and passing through the PC end;
the test result judging module is used for judging that the verified test result passes through the PC terminal, judging a test case if the test result passes through the PC terminal, and otherwise, failing the test;
and judging the test case, wherein the test is successful when the test case of the equipment end to be tested is completed, and otherwise, the test verification of the equipment end to be tested is carried out again.
A channel delay module; the method is used for measuring the PC end by the channel delay of the equipment end to be measured, thereby ensuring the synchronism of the channel of the equipment end to be measured.
Example 4
Sig is made from the above embodiment, and this file maps all DIO resources on the board to this file. Create a resource group file chmap. This file may bind certain resources into a group;
making a waveform time sequence file timing.tim and testing a time sequence file timing.sig corresponding to the graph; the waveform for the test consists of a plurality of identical/or different wavetiming; manufacturing a test case file pat.csv, wherein the file defines digital waveforms to be transmitted and waveforms expected to be acquired;
csv is made as a test case file list, which needs to set the pat related file expected to run and the expected number of failed/successful sampling pat. And simultaneously generating theoretically expected execution vector numbers of each case, expected failure vector numbers and expected waveform data by the testing tool while generating the testing cases. Acquiring actual waveform data by a sampling data channel of the equipment, and determining the correctness of an execution result item by item with expected waveform data; comparing the number of actually operated vectors with the expected number of vectors; comparing the number of failed vectors actually operated by the equipment with the number of expected failure vectors; and (4) the expected number of the executed vector of each case, the expected number of failed vector, and the expected waveform data all meet the conditions, the test item passes, otherwise, the test item does not pass.
As can be seen from fig. 3, Real Tx represents the digital waveform output by the ATE device transmit channel; '0/1' indicates the high and low levels of the transmission.
ExpRx represents the digital waveform expected to be received by the ATE equipment receiving channel; 'X' denotes a level of no concern about reception. 'H' indicates a desired high level and 'L' indicates a desired low level.
Real Rx represents the digital waveform actually received by the receiving channel of the ATE equipment; 'X' denotes a level of no concern about reception. 'H' indicates that a high level is received, and 'L' indicates that a low level is received.
Deal represents the physical delay existing from the sending channel to the receiving channel of the ATE device. The equipment sends digital waveform and receives level and starts at the same time, because there is time delay directly in sending and receiving, so the receiving end reserves certain calculated digital waveform number and does not do level comparison, the last waveform of the sending end does not do level comparison at the end of the same principle.
The specific delay value DelayValue is obtained from the PCB layout, and the number of waveforms which are not compared in the early stage is DelayValue/T according to the waveform period T of the sending end.
Err indicates that the digital signal received by the ATE equipment receive channel does not match the expected one; fail cnt is incremented by 1 when there is a reception mismatch with the expectation.
Claims (9)
1. The ATE equipment self-checking method comprises a PC end and an equipment end to be tested,
generating a test file, and generating the test file by the PC terminal;
the PC end executes the test of the equipment end to be tested according to the test case table; testing and checking, wherein the PC side checks the relevant information tested by the equipment side to be tested;
judging the test result, judging the test result after verification by the PC side, judging the test case if the test result passes, otherwise, failing the test;
and judging the test case, if the test case of the equipment end to be tested is completed by the PC side, the test is successful, otherwise, the test verification of the equipment end to be tested is carried out again.
2. The ATE equipment self-test based method according to claim 1, wherein a channel delay is required before a test is performed; and the PC side measures the channel delay of the equipment end to be tested, thereby ensuring the synchronism of the channel of the equipment end to be tested.
3. The ATE equipment self-test-based method of claim 2, wherein the channels of the equipment end to be tested comprise a receiving channel and a sending channel.
4. The ATE equipment self-test based method according to claim 3, wherein the channel delay is performed, a transmitting channel and a receiving channel of a PC end measuring equipment testing end are delayed, a receiving channel reservation measuring threshold is not compared with a level, when the equipment testing end tests, the same measuring threshold reserved for the transmitting channel is not compared with the level, the measuring threshold is DelayValue/T, wherein, the DelayValue delay value is T waveform period.
5. The ATE equipment self-test-based method of claim 1, wherein the test-related information comprises data for testing, a number of waveforms tested, and expected error waveforms.
6. The ATE equipment self-test-based method of claim 1, wherein the test result determination comprises performing a result determination, an operation determination, and a failure determination,
judging the execution result, wherein actual waveform data are acquired by a sampling data channel of the equipment, and are compared and judged with expected waveform data one by one;
judging the operation, namely comparing and judging the number of actually operated vectors of the equipment with the expected number of vectors;
and (4) failure judgment, wherein the number of failed vectors actually operated by the equipment is compared with the expected number of victor failure.
7. The ATE equipment self-test based method according to claim 1, wherein the test files comprise a pin resource mapping file, a set of signals to be tested file, and a waveform definition file.
8. The ATE equipment self-checking system comprises a PC end and an equipment end to be tested, and is characterized by also comprising a test file generation module, a test execution module, a test verification module, a test result judgment module and a test case judgment module;
the test file generation module is used for generating a test file to pass through the PC terminal;
the test execution module is used for executing the test of the equipment terminal to be tested according to the test case table through the PC terminal;
the test checking module is used for checking the relevant information tested by the equipment end to be tested and passing through the PC end;
the test result judging module is used for judging that the verified test result passes through the PC terminal, judging a test case if the test result passes through the PC terminal, and otherwise, failing the test;
and judging the test case, wherein the test is successful when the test case of the equipment end to be tested is completed, and otherwise, the test verification of the equipment end to be tested is carried out again.
9. The ATE equipment self-test based system of claim 8, further comprising a channel delay module; the method is used for measuring the PC end by the channel delay of the equipment end to be measured, thereby ensuring the synchronism of the channel of the equipment end to be measured.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114325547A (en) * | 2021-12-24 | 2022-04-12 | 上海御渡半导体科技有限公司 | Detection device and method for ATE test channel |
| CN114325547B (en) * | 2021-12-24 | 2024-05-03 | 上海御渡半导体科技有限公司 | Detection device and method for ATE (automatic test equipment) test channel |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040119487A1 (en) * | 2002-12-13 | 2004-06-24 | Yoon-Gyu Song | Test board for testing IC package and tester calibration method using the same |
| US20050057257A1 (en) * | 2003-09-15 | 2005-03-17 | International Business Machines Corporation | Apparatus and method for automatic elimination of round-trip delay errors induced by automatic test equipment calibration |
| CN102788951A (en) * | 2012-09-05 | 2012-11-21 | 无锡江南计算技术研究所 | Automatic test equipment (ATE) test result judging method and ATE test method |
| CN104639400A (en) * | 2015-02-13 | 2015-05-20 | 盛科网络（苏州）有限公司 | Automatic detection method and device of network packet processing chip |
| US20180095129A1 (en) * | 2014-04-30 | 2018-04-05 | Duke University | Software-based self-test and diagnosis using on-chip memory |
| CN108427632A (en) * | 2017-02-14 | 2018-08-21 | 腾讯科技（深圳）有限公司 | Automatic test approach and device |
| CN109524055A (en) * | 2018-12-24 | 2019-03-26 | 上海华力集成电路制造有限公司 | Method and test macro based on SOC ATE positioning memory fail bit |
| CN109885433A (en) * | 2018-12-29 | 2019-06-14 | 芯海科技（深圳）股份有限公司 | A kind of method of quick test SPI communication module |
| CN110716120A (en) * | 2018-07-12 | 2020-01-21 | 澜起科技股份有限公司 | Calibration method for channel delay deviation of automatic chip test equipment |
| CN110855523A (en) * | 2019-11-15 | 2020-02-28 | 北京广利核系统工程有限公司 | Multi-channel response time automatic testing device and method |
| CN111965530A (en) * | 2020-04-30 | 2020-11-20 | 京微齐力(北京)科技有限公司 | JTAG-based FPGA chip automatic test method |
| CN112821885A (en) * | 2020-12-30 | 2021-05-18 | 杭州加速科技有限公司 | Relative time delay measurement calibration method and device for chips of each channel of ATE (automatic test equipment) |
-
2021
- 2021-06-17 CN CN202110673638.1A patent/CN113539350B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040119487A1 (en) * | 2002-12-13 | 2004-06-24 | Yoon-Gyu Song | Test board for testing IC package and tester calibration method using the same |
| US20050057257A1 (en) * | 2003-09-15 | 2005-03-17 | International Business Machines Corporation | Apparatus and method for automatic elimination of round-trip delay errors induced by automatic test equipment calibration |
| CN102788951A (en) * | 2012-09-05 | 2012-11-21 | 无锡江南计算技术研究所 | Automatic test equipment (ATE) test result judging method and ATE test method |
| US20180095129A1 (en) * | 2014-04-30 | 2018-04-05 | Duke University | Software-based self-test and diagnosis using on-chip memory |
| CN104639400A (en) * | 2015-02-13 | 2015-05-20 | 盛科网络（苏州）有限公司 | Automatic detection method and device of network packet processing chip |
| CN108427632A (en) * | 2017-02-14 | 2018-08-21 | 腾讯科技（深圳）有限公司 | Automatic test approach and device |
| CN110716120A (en) * | 2018-07-12 | 2020-01-21 | 澜起科技股份有限公司 | Calibration method for channel delay deviation of automatic chip test equipment |
| CN109524055A (en) * | 2018-12-24 | 2019-03-26 | 上海华力集成电路制造有限公司 | Method and test macro based on SOC ATE positioning memory fail bit |
| CN109885433A (en) * | 2018-12-29 | 2019-06-14 | 芯海科技（深圳）股份有限公司 | A kind of method of quick test SPI communication module |
| CN110855523A (en) * | 2019-11-15 | 2020-02-28 | 北京广利核系统工程有限公司 | Multi-channel response time automatic testing device and method |
| CN111965530A (en) * | 2020-04-30 | 2020-11-20 | 京微齐力(北京)科技有限公司 | JTAG-based FPGA chip automatic test method |
| CN112821885A (en) * | 2020-12-30 | 2021-05-18 | 杭州加速科技有限公司 | Relative time delay measurement calibration method and device for chips of each channel of ATE (automatic test equipment) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114325547A (en) * | 2021-12-24 | 2022-04-12 | 上海御渡半导体科技有限公司 | Detection device and method for ATE test channel |
| CN114325547B (en) * | 2021-12-24 | 2024-05-03 | 上海御渡半导体科技有限公司 | Detection device and method for ATE (automatic test equipment) test channel |
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|---|---|
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