CN116629195A - Integrated circuit simulation verification platform - Google Patents
Integrated circuit simulation verification platform Download PDFInfo
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- CN116629195A CN116629195A CN202310342722.4A CN202310342722A CN116629195A CN 116629195 A CN116629195 A CN 116629195A CN 202310342722 A CN202310342722 A CN 202310342722A CN 116629195 A CN116629195 A CN 116629195A
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- 238000012795 verification Methods 0.000 title claims abstract description 42
- 238000004088 simulation Methods 0.000 title claims abstract description 34
- 238000012360 testing method Methods 0.000 claims abstract description 184
- 230000005284 excitation Effects 0.000 claims abstract description 59
- 238000012544 monitoring process Methods 0.000 claims abstract description 18
- 238000004891 communication Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 22
- 238000013461 design Methods 0.000 claims description 8
- 238000005259 measurement Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 15
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 230000000638 stimulation Effects 0.000 abstract 1
- 238000012827 research and development Methods 0.000 description 3
- 210000001503 joint Anatomy 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/06—Structured ASICs
Abstract
The invention relates to the technical field of integrated circuit testing, in particular to an integrated circuit simulation verification platform, which comprises: the port configuration module analyzes the test parameters to obtain pin data to be tested and pin data to be tested; the excitation generating module is used for applying excitation to the device to be tested according to the pin data to be tested and applying excitation to the accompanying test pin according to the accompanying test pin data; the monitoring module is respectively connected with the device to be tested and the accompanying device, and respectively acquires and outputs the test data of the device to be tested and the accompanying device. The beneficial effects are that: the device to be tested and the accompanying test device can be stimulated according to specific time sequences and corresponding pins by analyzing the pin data to be tested and the accompanying test pin data before testing, so that the stimulation generation module can conveniently test a plurality of pins of the device to be tested and verify the communication function between the device to be tested and the accompanying test device, and a good test effect is achieved.
Description
Technical Field
The invention relates to the technical field of integrated circuit testing, in particular to an integrated circuit simulation verification platform.
Background
An integrated circuit (Integrated Circuit, IC) is a microelectronic device or component that uses a process to interconnect components and wiring of transistors, diodes, resistors, capacitors, inductors, etc. required in a circuit, fabricated on a small or several small semiconductor die or dielectric substrate, and then packaged in a package to provide a microstructure having the desired circuit function. In the research and development stage of the integrated circuit chip, the method mainly comprises logic code design, front-end logic function simulation verification, FPGA physical prototype verification, back-end time sequence simulation verification and the like. For the design research and development of each chip, a verification engineer needs to perform full simulation verification on the functional time sequence and the like of the chip so as to ensure the stability and reliability of the chip, so that the workload of the simulation verification work along with the whole stage of the design research and development of the chip reaches more than 70%, and therefore, how to accelerate the simulation verification and improve the accuracy of the simulation verification are particularly important.
In the prior art, simulation verification work for integrated circuit chips is usually performed by relying on a simulation verification platform. In the simulation verification platform, corresponding test cases are designed according to the integrated circuit prototype designed by the user, and corresponding excitation is applied to the integrated circuit chip based on the test cases, so that the function verification process of the integrated circuit is realized.
However, in practical implementation, the inventor finds that the simulation verification platform in the prior art generally performs verification only on a single design logic to be tested, that is, performs verification on functions of an integrated circuit only through a single or multiple test cases executed in series, and does not consider specific timing problems of the integrated circuit in the test process. This results in that the simulation verification platform cannot well realize verification of the corresponding function when verifying the integrated circuit chip with the corresponding communication function and the chip interaction function.
Disclosure of Invention
Aiming at the problems in the prior art, an integrated circuit simulation verification platform is provided.
The specific technical scheme is as follows:
an integrated circuit emulation verification platform comprising:
the port configuration module receives externally input test parameters and analyzes the test parameters to obtain to-be-tested pin data and to-be-tested pin data which need to be stimulated by a to-be-tested device and a to-be-tested device respectively;
the excitation generation module receives the pin data to be tested, the test accompanying pin data and the externally input test case, applies excitation to the device to be tested according to the pin data to be tested, applies excitation to the accompanying device according to the test accompanying pin data, and simultaneously tests the device to be tested and the accompanying device by adopting the test case;
the monitoring module is respectively connected with the device to be tested and the accompanying device, and respectively acquires and outputs the test data of the device to be tested and the accompanying device.
On the other hand, the device also comprises a parameter configuration module which is respectively connected with the port configuration module, the excitation generation module and the monitoring module;
the parameter configuration module comprises:
the port selection module receives an external test requirement, and adds a port to be tested into the test parameter according to the test requirement;
the type selection module receives the test requirement, and adds a test device parameter into the test parameter according to the test requirement;
and the output selection module receives the test requirement and adds an output file parameter into the test parameter according to the test requirement.
In another aspect, the port configuration module includes:
the port database module is used for storing port parameters corresponding to the device to be tested and the device to be tested in advance;
the software port configuration module is connected with the port database module and generates a use case port according to the port to be tested and the port parameter;
the hardware port configuration module is connected with the port database module and respectively generates the pin data to be tested and the accompanied pin data according to the port to be tested and the port parameters.
On the other hand, the system also comprises a use case compiling module, wherein the use case compiling module is connected with the port configuration module, and the use case compiling module comprises:
a first test code storage module, in which a first test code suitable for the device under test is stored;
a second test code storage module, in which a second test code suitable for the accompanying device is stored;
the use case generation module is respectively connected with the first test code storage module and the second test code storage module;
the use case generation module receives the use case port, and the use case generation module processes the first test code and the second test code according to the use case port to generate the test use case.
In another aspect, the excitation generation module includes:
and the pin configuration module is used for respectively configuring pins of the device to be tested and the accompanying device according to parameters of the tested device.
In another aspect, the monitoring module includes:
the output type setting module receives the output file parameters and adjusts the file types of the output files according to the output file parameters.
On the other hand, the system also comprises a parameter input module, wherein the parameter input module is connected with the parameter configuration module, responds to an external input instruction, automatically generates the design requirement according to the input instruction and inputs the parameter configuration module.
In another aspect, the excitation generation module further comprises:
the interconnection module is respectively connected with the device to be tested and the accompanying device and is used for establishing communication connection between the device to be tested and the accompanying device;
the excitation module is respectively connected with the device to be detected and the accompanying device, a hardware excitation code is prestored in the excitation module, and the excitation module calls the hardware excitation code to apply excitation to the device to be detected and/or the accompanying device according to the pin data to be detected and the accompanying pin data.
In another aspect, the monitoring module includes:
the first acquisition module acquires first output data of the device to be tested;
the second acquisition module acquires second output data of the accompanying measurement device;
the output module is respectively connected with the output type setting module, the first acquisition module and the second acquisition module, and the output module acquires the first output data and the second output data and generates a test report according to the file type.
The technical scheme has the following advantages or beneficial effects:
aiming at the problem that the test effect is poor because the simulation verification platform in the prior art cannot effectively test the time sequence of the chip, in the embodiment, the to-be-tested pin data and the to-be-tested pin data of the to-be-tested device and the to-be-tested device are analyzed before the test, so that the excitation generation module can apply excitation to the to-be-tested device and the to-be-tested device according to the specific time sequence and the corresponding pins, the to-be-tested device and the to-be-tested device can test according to the specific time sequence and excitation when the test case is executed, the test of a plurality of pins of the to-be-tested device is facilitated, and the communication function between the to-be-tested device and the to-be-tested device is verified, so that the good test effect is realized.
Drawings
Embodiments of the present invention will now be described more fully with reference to the accompanying drawings. The drawings, however, are for illustration and description only and are not intended as a definition of the limits of the invention.
FIG. 1 is an overall schematic of an embodiment of the present invention;
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
The invention comprises the following steps:
an integrated circuit simulation verification platform, as shown in fig. 1, comprising:
the port configuration module 1 is used for receiving externally input test parameters, and analyzing the test parameters to obtain to-be-tested pin data and to-be-tested pin data which need to be stimulated by the to-be-tested device and the to-be-tested device respectively in the test case;
the excitation generation module 2 is used for receiving the pin data to be tested, the test accompanying pin data and the externally input test cases, applying excitation to the device to be tested according to the pin data to be tested, applying excitation to the test accompanying device according to the test accompanying pin data, and simultaneously testing the device to be tested and the test accompanying device by adopting the test cases;
the monitoring module 3 is respectively connected with the device to be tested and the accompanying device, and the monitoring module 3 respectively acquires and outputs the test data of the device to be tested and the accompanying device.
Specifically, for the simulation verification platform in the prior art, only the test case is generally considered to test the device, but the problem of excitation and time sequence actually applied by the device is not concerned, in this embodiment, the port configuration module 1 is set to parse the received test parameters, so as to obtain the to-be-tested pin data and the accompanying-test pin data, which need to be excited respectively, in the test process, including the time sequence needing to be excited, the to-be-tested pins or accompanying-test pins needing to be excited sequentially, and the like. By analyzing the pin data to be tested and the test accompanying pin data, the excitation generation module 2 can determine the pins and the time sequences for applying excitation to the device to be tested and the test accompanying device according to the received pin data to be tested and the received test accompanying pin data, and further apply correct excitation to the device to be tested and the test accompanying device in the process of executing the test case, so that a good verification effect is achieved.
In one embodiment, the system further comprises a parameter configuration module 4, wherein the parameter configuration module is respectively connected with the port configuration module 1, the excitation generation module 2 and the monitoring module 3;
the parameter configuration module 4 includes:
the port selection module 41, the port selection module 41 receives the external test requirement, and the port selection module 41 adds a port to be tested in the test parameter according to the test requirement;
the type selection module 42, the type selection module 42 receives the test requirement, the type selection module 42 adds the test device parameter in the test parameter according to the test requirement;
the output selection module 43, the output selection module 43 receives the test requirement, and the output selection module 43 adds the output file parameter in the test parameter according to the test requirement.
Specifically, in order to achieve a better test effect on a device to be tested, in this embodiment, by respectively constructing the port selection module 41, the type selection module 42 and the output selection module 43 in the parameter configuration module 4, the simulation test platform can configure the port to be tested, the parameters of the device to be tested and the parameters of the output file in the actual test process according to the test requirements, thereby achieving a better test effect.
In one embodiment, port configuration module 1 comprises:
the port database module 11, the port database module 11 stores the port parameters corresponding to the device to be tested and the device to be tested in advance;
the software port configuration module 12, the software port configuration module 12 is connected with the port database module 11, and the software port configuration module 12 generates a use case port according to the port to be tested and the port parameters;
the hardware port configuration module 13, the hardware port configuration module 13 is connected with the port database module 11, and the hardware port configuration module 13 generates the pin data to be tested and the accompanying pin data according to the port to be tested and the port parameters respectively.
Specifically, for the simulation verification platform in the prior art, only testing of the device by using the test case is generally considered, and the problem of stimulus and timing actually applied by the device is not concerned. Subsequently, after receiving the test parameters input by the parameter configuration module 4, the software port configuration module 12 and the hardware port configuration module 13 respectively analyze the test parameters to obtain the ports to be tested. In the software port configuration module 12, the port parameters are searched based on the port to be tested, so that pins which need to be tested on the device to be tested and the device to be tested in the process of compiling the test case are determined, and the time sequence information recorded in the port parameters is combined to generate the case port, so that the generation process of the test case can be more in line with the time sequence and the pins which apply excitation on the device to be tested and the device to be tested, and the method is mainly used for configuring the behavior of multiplexing configuration of software registers of the DUT and the VIP; in the hardware port configuration module 13, the port parameters are searched based on the port to be tested, so that pins which need to be excited by the device to be tested and the accompanying device in the actual test process are determined, the hardware connection mode selection for inputting the DUT and the VIP is configured and selected, the sending end and the receiving end can be arranged for the port of the communication class in a butt joint interconnection mode, the receiving end and the sending end are arranged for the butt joint interconnection mode, and the time sequence information recorded in the port parameters is combined for respectively generating the pin data to be tested and the pin data to be accompanying tested. Through the arrangement, a good test effect is achieved.
In one embodiment, the system further includes a use case compiling module 5, the use case compiling module 5 is connected to the port configuration module 1, and the use case compiling module 5 includes:
a first test code storage module 51 in which a first test code suitable for a device under test is stored;
a second test code storage module 52 in which a second test code suitable for a device under test is stored;
the use case generating module 53 is connected with the first test code storage module and the second test code storage module respectively;
the case generation module 53 receives the case port, and the case generation module processes the first test code and the second test code according to the case port to generate a test case.
Specifically, in the present embodiment, the first test code storage module 51, the second test code storage module 52 and the use case generation module 53 are respectively provided in the use case compiling module 5, so that the device is usually only tested by using the test case, and the problem of stimulus and timing actually applied by the device is not concerned. The first test code storage module 51 and the second test code storage module 52 are respectively configured to store a first test code applicable to a device to be tested and a second test code applicable to a device to be tested, and the use case generation module 53 is configured to process the first test code and the second test code according to the received use case port to generate a test case, so that the generated test case can better match with an excitation actually applied by the excitation generation module 2 to the device to be tested and the device to be tested, and a better test effect is achieved.
In the implementation process, the test cases include a first test case dut. Bin applicable to the device under test and a second test case vip. Bin applicable to the device under test.
In one embodiment, the stimulus generation module 2 comprises:
the pin configuration module 21, the pin configuration module 21 configures the pins of the device to be tested and the accompanying device according to the parameters of the tested device.
Specifically, for the simulation verification platform in the prior art, only the test case is generally considered to test the device, but the problem of excitation and timing actually applied by the device is not concerned, in this embodiment, by setting the pin configuration module 21 in the excitation generation module 2, the pin configuration module 21 can obtain the pin information of the device to be tested and the device to be tested according to the input test device parameters, and configure the pins, so that the excitation generation module can apply correct excitation to the device to be tested and the device to be tested in the test process, thereby realizing a better test effect.
In one embodiment, the monitoring module 3 comprises:
the output type setting module 31, the output type setting module 31 receives the output file parameter, and the output type setting module 31 adjusts the file type of the output file according to the output file parameter.
Specifically, in order to achieve a better test effect, in this embodiment, an output type setting module 31 is set in the monitoring module 3, and the output type setting module 31 can adjust the file type actually output by the monitoring module 3 according to the received output file parameters, so as to facilitate the user to conduct research, reading and analysis.
In one embodiment, the system further comprises a parameter input module 6, wherein the parameter input module 6 is connected with the parameter configuration module 4, and the parameter input module 6 responds to an external input instruction, automatically generates design requirements according to the input instruction and inputs the parameter configuration module 4.
Specifically, aiming at the problems that a user is usually required to manually configure related parameters, write codes and the like in the test process and the operation is relatively complicated in the simulation verification platform in the prior art, in the embodiment, the parameter input module 6 is set to respond to the input instruction, so that the control of the parameter configuration module 4 is realized by automatically generating the design requirement according to the input instruction, the better automatic flow process is realized, and the complicated degree of the operation is reduced.
In the implementation process, the input instruction can be a shell script, and the first parameter (RTL, NETLIST, SDF file selection), the second parameter (DUT, VIP, CASE selection) and the third parameter (rtl _log, net_log and sdf_log selection) are subjected to parameter transmission judgment and are loaded to a simulation tool NCsim compiling and file generation entry through a shell selection statement structure. And the automatic loading operation of the use case can be realized by adding the information of the multi-call execution script into an automatic operation script.
In one embodiment, the excitation generation module 2 further comprises:
the interconnection module 22 is respectively connected with the device to be tested and the device to be tested, and the interconnection module 22 is used for establishing communication connection between the device to be tested and the device to be tested;
the excitation module 23 is respectively connected with the device to be detected and the accompanying device, a hardware excitation code is prestored in the excitation module, and the excitation module calls the hardware excitation code to apply excitation to the device to be detected and/or the accompanying device according to the pin data to be detected and the accompanying pin data.
Specifically, for the simulation verification platform in the prior art, only the test case is generally considered to test the device, but the problem of excitation and timing actually applied by the device is not concerned, in this embodiment, the interconnection module 22 is arranged in the excitation generation module 2, so that the device to be tested and the accompanying test device can be mutually communicated according to the test requirement. Then, excitation is applied by the set excitation module 23 according to the pin data to be tested and the accompanying test pin data by using the hardware excitation code, so that the device to be tested and the accompanying test device can receive correct excitation signals in the test process, and a better test effect is realized.
In one embodiment, the monitoring module 3 comprises:
the first acquisition module 32, the first acquisition module 32 obtains the first output data of the device to be tested;
the second acquisition module 33, the second acquisition module 33 obtains the second output data of the accompanying measuring device;
the output module 34, the output module 34 is connected with the output type setting module 31, the first acquisition module 32 and the second acquisition module 33 respectively, and the output module obtains the first output data and the second output data and generates a test report according to the file type.
Specifically, in order to achieve a better test effect, in this embodiment, the monitoring module 3 is respectively provided with the first acquisition module 32, the second acquisition module 33 and the output module 34, so that the monitoring module 3 can respectively obtain the first output data of the device to be tested and the second output data of the accompanying device, respectively compare the first output data with the second output data, generate a test report according to a preset file type after a comparison result is obtained, and output the test report, thereby achieving a better report output effect.
In the implementation process, normal_Exit marks can be printed out in the result file to indicate that the test is correct, abnormal_Exit marks can be printed out to indicate that the test is wrong, and then the result is selected according to the output parameters transmitted by the upper layer and is output to the corresponding test result file, and a verifier can search through characters in the file to check the test results of all verification items.
The beneficial effects are that:
aiming at the problem that the test effect is poor because the simulation verification platform in the prior art cannot effectively test the time sequence of the chip, in the embodiment, the to-be-tested pin data and the to-be-tested pin data of the to-be-tested device and the to-be-tested device are analyzed before the test, so that the excitation generation module can apply excitation to the to-be-tested device and the to-be-tested device according to the specific time sequence and the corresponding pins, the to-be-tested device and the to-be-tested device can test according to the specific time sequence and excitation when the test case is executed, the test of a plurality of pins of the to-be-tested device is facilitated, and the communication function between the to-be-tested device and the to-be-tested device is verified, so that the good test effect is realized.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included in the scope of the present invention.
Claims (9)
1. An integrated circuit simulation verification platform, comprising:
the port configuration module receives externally input test parameters and analyzes the test parameters to obtain to-be-tested pin data and to-be-tested pin data which need to be stimulated by a to-be-tested device and a to-be-tested device respectively;
the excitation generation module receives the pin data to be tested, the test accompanying pin data and the externally input test case, applies excitation to the device to be tested according to the pin data to be tested, applies excitation to the accompanying device according to the test accompanying pin data, and simultaneously tests the device to be tested and the accompanying device by adopting the test case;
the monitoring module is respectively connected with the device to be tested and the accompanying device, and respectively acquires and outputs the test data of the device to be tested and the accompanying device.
2. The integrated circuit simulation verification platform of claim 1, further comprising a parameter configuration module, the parameter configuration module being connected to the port configuration module, the stimulus generation module, and the monitoring module, respectively;
the parameter configuration module comprises:
the port selection module receives an external test requirement, and adds a port to be tested into the test parameter according to the test requirement;
the type selection module receives the test requirement, and adds a test device parameter into the test parameter according to the test requirement;
and the output selection module receives the test requirement and adds an output file parameter into the test parameter according to the test requirement.
3. The integrated circuit emulation verification platform of claim 3 wherein the port configuration module comprises:
the port database module is used for storing port parameters corresponding to the device to be tested and the device to be tested in advance;
the software port configuration module is connected with the port database module and generates a use case port according to the port to be tested and the port parameter;
the hardware port configuration module is connected with the port database module and respectively generates the pin data to be tested and the accompanied pin data according to the port to be tested and the port parameters.
4. The integrated circuit simulation verification platform of claim 3, further comprising a use case compilation module coupled to the port configuration module, the use case compilation module comprising:
a first test code storage module, in which a first test code suitable for the device under test is stored;
a second test code storage module, in which a second test code suitable for the accompanying device is stored;
the use case generation module is respectively connected with the first test code storage module and the second test code storage module;
the use case generation module receives the use case port, and the use case generation module processes the first test code and the second test code according to the use case port to generate the test use case.
5. The integrated circuit simulation verification platform of claim 2, wherein the stimulus generation module comprises:
and the pin configuration module is used for respectively configuring pins of the device to be tested and the accompanying device according to parameters of the tested device.
6. The integrated circuit simulation verification platform of claim 2, wherein the monitoring module comprises:
the output type setting module receives the output file parameters and adjusts the file types of the output files according to the output file parameters.
7. The integrated circuit simulation verification platform of claim 2, further comprising a parameter input module, the parameter input module coupled to the parameter configuration module, the parameter input module responsive to an external input indication, the parameter input module automatically generating the design requirements and inputting the parameter configuration module based on the input indication.
8. The integrated circuit simulation verification platform of claim 1, wherein the stimulus generation module further comprises:
the interconnection module is respectively connected with the device to be tested and the accompanying device and is used for establishing communication connection between the device to be tested and the accompanying device;
the excitation module is respectively connected with the device to be detected and the accompanying device, a hardware excitation code is prestored in the excitation module, and the excitation module calls the hardware excitation code to apply excitation to the device to be detected and/or the accompanying device according to the pin data to be detected and the accompanying pin data.
9. The integrated circuit simulation verification platform of claim 6, wherein the monitoring module comprises:
the first acquisition module acquires first output data of the device to be tested;
the second acquisition module acquires second output data of the accompanying measurement device;
the output module is respectively connected with the output type setting module, the first acquisition module and the second acquisition module, and the output module acquires the first output data and the second output data and generates a test report according to the file type.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116796701A (en) * | 2023-08-28 | 2023-09-22 | 宁波联方电子科技有限公司 | Device test unit structure automation realization device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116796701A (en) * | 2023-08-28 | 2023-09-22 | 宁波联方电子科技有限公司 | Device test unit structure automation realization device and method |
| CN116796701B (en) * | 2023-08-28 | 2023-12-19 | 宁波联方电子科技有限公司 | Device test unit structure automation realization device and method |
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