CN108122583B - Method and apparatus for executing storage type flash memory command - Google Patents
Method and apparatus for executing storage type flash memory command Download PDFInfo
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- CN108122583B CN108122583B CN201611090092.2A CN201611090092A CN108122583B CN 108122583 B CN108122583 B CN 108122583B CN 201611090092 A CN201611090092 A CN 201611090092A CN 108122583 B CN108122583 B CN 108122583B
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
Abstract
The invention relates to a method and a device for executing storage type flash memory commands. The invention discloses a method and a device for executing nandflash commands, and belongs to the technical field of computers. Executing a management command, a control sub-command of a data reading command and a control sub-command of a data writing command through a programmable processor included in the nandflash controller, and executing a data sub-command of the data reading command and a data sub-command of the data writing command through a data reading and writing logic circuit included in the nandflash controller; the switching between the programmable embedded processor and the data read-write logic circuit is controlled by the programmable embedded processor, and the advantages of flexible programming of the programmable processor and efficient concurrent processing of the data read-write logic circuit are compatible, so that the nandflash controller is efficient and compatible with nandflash commands of nandflash memories of different manufacturers and different models, and the compatibility of the nandflash controller is improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method and an apparatus for executing nandflash (storage flash memory) commands.
Background
The nandflash memory is one of the most widely applied memories at present, and is associated with a nandflash controller; when operating the nandflash memory, sending a nandflash command to a controller associated with the nandflash memory, and executing the nandflash command by the nandflash controller. The nandflash command may be a management command, a read data command, or a write data command. For example, when data is stored in the nandflash memory, a data writing command is sent to the nandflash controller, and the data writing command carries data to be written; and the nandflash controller receives the data writing command and stores the data to be written into the nandflash memory according to the data writing command.
At present, when a nandflash controller executes a nandflash command, an interface time sequence is output through a data read-write logic circuit in the nandflash controller, wherein the interface time sequence comprises the time for executing the nandflash command, and the nandflash command is executed when the time for executing the nandflash command is reached according to the interface time sequence.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
because the nandflash memories of different manufacturers have different particles (also called granularity), interface time sequences required by the nandflash memories of different manufacturers are different, however, a data read-write logic circuit in the nandflash controller cannot be modified, so that the nandflash controller cannot be compatible with the nandflash memories of different manufacturers, namely the nandflash controller has poor compatibility.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present invention provide a method and an apparatus for executing a nandflash command. The technical scheme is as follows:
the embodiment of the invention provides a method for executing nandflash commands, which is applied to a nandflash controller of a storage type flash memory, wherein the nandflash controller comprises a programmable processor and a data read-write logic circuit, and the method comprises the following steps:
receiving, by the programmable processor, a nandflash command, the nandflash command being for operating a nandflash memory associated with the nandflash controller;
if the nandflash command is a management command, simulating a cycle through the programmable processor to output a first interface time sequence, and executing the nandflash command on the nandflash memory according to the first interface time sequence;
if the nandflash command is a read data command or a write data command, acquiring a control sub-command and a data sub-command which are included in the nandflash command through the programmable processor, outputting a second interface time sequence by a simulation cycle, executing the control sub-command on the nandflash memory according to the second interface time sequence, outputting a third interface time sequence through the data read-write logic circuit, and executing the data sub-command on the nandflash memory according to the third interface time sequence.
In the embodiment of the invention, a programmable processor included in the nandflash controller executes a management command, a control sub-command of a read data command and a control sub-command of a write data command, and a data read-write logic circuit included in the nandflash controller executes a data sub-command of the read data command and a data sub-command of the write data command; because the programmable processor is added in the nandflash controller, the programmable processor can simulate the cycle to output the first interface time sequence and the second interface time sequence, so that the advantages of flexible programming of the programmable processor and efficient concurrent processing of the data read-write logic circuit are compatible, the nandflash controller can be compatible with nandflash commands of nandflash memories of different manufacturers and different models, and the compatibility of the nandflash controller is improved.
In one possible design, before receiving, by the programmable processor, a nandflash command, the method further includes:
acquiring the operation authority of the nandflash memory from the nandflash memory through the programmable processor;
correspondingly, before the obtaining, by the programmable processor, the control subcommand and the data subcommand included in the nandflash command, the method further includes:
and starting the data read-write logic circuit, and transferring the operation authority to the data read-write logic circuit through the programmable processor.
In the embodiment of the invention, after the programmable processor and the data read-write logic circuit are authorized, the programmable processor and the data read-write logic circuit can operate the nandflash memory, so that the safety is improved.
In one possible design, the outputting, by the programmable processor simulation cycle, the first interface timing comprises:
and acquiring a first time sequence parameter of a management command of the nandflash memory according to the identifier of the nandflash memory through the programmable processor, and simulating a cycle to output a first interface time sequence according to the first time sequence parameter.
In the embodiment of the invention, the programmable processor simulates the cycle to output the first interface time sequence according to the first time sequence parameter, so that the programmable processor outputs the first interface time sequence matched with the nandflash memory, and the compatibility is improved.
In one possible design, the outputting, by the programmable processor emulation cycle, the second interface timing comprises:
and acquiring a second time sequence parameter of a control subcommand of the nandflash memory by the programmable processor according to the identifier of the nandflash memory, and simulating a cycle to output a second interface time sequence according to the second time sequence parameter.
In the embodiment of the invention, the programmable processor simulates the cycle to output the second interface time sequence according to the second time sequence parameter, so that the programmable processor outputs the second interface time sequence matched with the nandflash memory, and the compatibility is improved.
In one possible design, the executing, by the programmable processor, the control subcommand on the nandflash memory according to the second interface timing comprises:
if the nandflash command is the data reading command, analyzing the data reading command through the programmable processor according to the second interface time sequence, and acquiring a first storage address and a data identifier of data to be read from a control sub-command of the data reading command;
and if the nandflash command is the data writing command, analyzing the data writing command through the programmable processor according to the second interface time sequence, and acquiring a second storage address and data to be written from a control sub-command of the data writing command.
In the embodiment of the invention, the programmable processor executes the control sub-command, so that the compatibility is improved.
In one possible design, the executing, by the data read/write logic circuit, the data subcommand included in the nandflash command on the nandflash memory according to the third interface timing includes:
if the nandflash command is the data reading command, the data reading command carries a data identifier and a first storage address, and data to be read corresponding to the data identifier is read from a storage space corresponding to the first storage address of the nandflash memory through the data reading and writing logic circuit according to the third interface timing sequence and a data sub-command of the data reading command;
and if the nandflash command is the data writing command, the data writing command carries a second storage address and data to be stored, and the data to be stored is stored into a storage space corresponding to the second storage address of the nandflash memory through the data reading and writing logic circuit according to the third interface time sequence and the data subcommand of the data writing command.
In the embodiment of the invention, the data sub-command is executed through the data read-write logic circuit, so that the processing efficiency is improved.
In a second aspect, an embodiment of the present invention provides an apparatus for executing a nandflash command, where the apparatus includes: a programmable processor and a data read/write logic circuit, configured to implement the method for executing a nandflash command provided in the first aspect or any one of the possible implementation manners of the first aspect.
The technical effect obtained by the second aspect of the embodiment of the present invention is similar to the technical effect obtained by the corresponding technical means in the first aspect, and is not described herein again.
In summary, the technical solution provided by the embodiment of the present invention has the following beneficial effects:
in the embodiment of the invention, a programmable processor included in the nandflash controller executes a management command, a control sub-command of a read data command and a control sub-command of a write data command, and a data read-write logic circuit included in the nandflash controller executes a data sub-command of the read data command and a data sub-command of the write data command; because the programmable processor is added in the nandflash controller, the programmable processor can simulate the cycle to output the first interface time sequence and the second interface time sequence, so that the advantages of flexible programming of the programmable processor and efficient concurrent processing of the data read-write logic circuit are compatible, the nandflash controller can be compatible with nandflash commands of nandflash memories of different manufacturers and different models, and the compatibility of the nandflash controller is improved.
Drawings
FIG. 1 is a schematic illustration of an implementation environment provided by an embodiment of the invention;
fig. 2 is a block diagram of a nandflash controller according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for executing a nandflash command according to an embodiment of the present invention;
fig. 4 is a block diagram of an apparatus for executing a nandflash command according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Interface time sequences of nandflash memories of different manufacturers are not completely the same, and interface time sequences of nandflash memories of different models of the same manufacturer are not completely the same; therefore, the nandflash controller associated with the nandflash memory cannot be compatible with nandflash memories of different manufacturers and different models. The embodiment of the invention provides a method for executing nandflash commands, wherein an execution main body of the method can be a nandflash controller, the nandflash controller comprises a programmable processor and a data read-write logic circuit, and nandflash memories of different manufacturers and different models can be controlled through the cooperation of the programmable processor and the data read-write logic circuit.
The nandflash command comprises a management command and a data read-write command; the data read and write commands include read data commands and write data commands. The management command may be a Reset command, an Identification command, a Configuration command, a Debug command. Management commands of nandflash memories of different models of different manufacturers are easy to change, and the management commands have the characteristics of various types, incomplete identical management commands of the nandflash memories of different models, small data processing amount, no special requirement on processing speed, serial processing of the management commands of a single nandflash memory and the like. The management commands are therefore suitable for being processed by the programmable processor.
The data read-write command relates to parallel and massive data operation of a plurality of nandflash commands; the data read-write command comprises a control sub-command and a data sub-command, the control sub-command comprises a keyword and an address part, and the data sub-command comprises a data part. The control subcommands of the nandflash memories of different models of different manufacturers are easy to change, and the control subcommands are not completely the same for the nandflash memories of different models, and have low requirements on the read-write speed. Therefore, the control subcommands of the data read/write commands are suitable for being processed by the programmable processor.
Because the data subcommands of the data read-write command are completely the same for nandflash memories of different models, the requirement on the read-write speed is high, and the interface time sequence is single and fixed, the data subcommands of the data read-write command are suitable for being handed over to a data read-write logic circuit for processing.
Therefore, in the embodiment of the present invention, the programmable processor included in the nandflash controller executes the management command, the control subcommand of the read data command, and the control subcommand of the write data command, and the data read/write logic circuit included in the nandflash controller executes the data subcommand of the read data command and the data subcommand of the write data command; the switching between the programmable embedded processor and the data read-write logic circuit is controlled by the programmable embedded processor, and the programmable processor is added in the nandflash controller and can simulate a cycle to output a first interface time sequence and a second interface time sequence, so that the advantages of flexible programming of the programmable processor and efficient concurrent processing of the data read-write logic circuit are compatible, the nandflash controller is efficient and compatible with nandflash memories of different manufacturers and different models, and the compatibility of the nandflash controller is improved.
Referring to fig. 1, an embodiment of the present invention provides an implementation environment, where the implementation environment includes a nandflash memory 1 and a nandflash controller 2; the nandflash controller 2 is configured to receive a nandflash command for operating the nandflash memory 1, and execute the nandflash command on the nandflash memory 1.
Referring to fig. 2, the nandflash controller 2 includes a programmable processor 21 and a data read/write logic circuit 22. The programmable processor 21 is configured to execute a nandflash command as a management command, a control subcommand of a read data command, and a control subcommand of a write data command on the nandflash memory, and the data read/write logic circuit 22 is configured to execute a nandflash command as a data subcommand of a read data command and a data subcommand of a write data command on the nandflash memory.
The nandflash controller 2 further includes an XBAR (switching matrix) module and a MUX (Multiplexer) module; programmable processor 21 and data read-write logic circuit 22 are connected to XBAR block 23, and XBAR block 23 is connected to MUX block 24. The XBAR module 23 is used for data transmission, and the MUX is used for acquiring the operation authority of the nandflash memory.
When the nandflash controller 2 is powered on, the programmable processor 21 acquires the operation authority of the nandflash memory through the MUX module 24. When the data read/write logic circuit 22 executes the data subcommand of the read data command and the data subcommand of the write data command on the nandflash memory, the programmable processor 21 transfers the operation authority of the nandflash memory to the data read/write logic circuit 22 through the XBAR module 23.
The embodiment of the invention provides a method for executing a nandflash command. Referring to fig. 3, the method includes:
step 201: receiving a nandflash command through a programmable processor, wherein the nandflash command is used for operating a nandflash memory associated with the nandflash controller, executing step 202 if the nandflash command is a management command, and executing step 203 if the nandflash command is a read data command or a write data command.
When the host operates the nandflash memory, the host sends a nandflash command to a nandflash controller associated with the nandflash memory; a programmable processor in the nandflash controller receives the nandflash command sent by a host, and judges whether the nandflash command is a management command or a data read-write command, wherein the data read-write command comprises a read data command and a write data command; if the command is a management command, executing step 202; if the command is a data read/write command, step 203 is executed.
The step of judging whether the nandflash command is a management command or a data read-write command by the programmable processor can be as follows:
the programmable processor analyzes the nandflash command and obtains the type code of the nandflash command; and judging whether the nandflash command is a management command or a data read-write command according to the type code of the nandflash command.
If the type code of the nandflash command is the type code corresponding to the management command, the programmable processor determines that the nandflash command is the management command; if the type code of the nandflash command is the type code corresponding to the data reading command, the programmable processor determines that the nandflash command is the data reading command; and if the type code of the nandflash command is the type code corresponding to the write data command, the programmable processor determines that the nandflash command is the write data command.
Step 202: if the nandflash command is a management command, a programmable processor simulation cycle outputs a first interface time sequence, and the nandflash memory executes the nandflash command according to the first interface time sequence.
This step can be realized by the following steps 2021-2023, including:
2021: and if the nandflash command is a management command, the programmable processor acquires a first time sequence parameter of the management command of the nandflash memory according to the identifier of the nandflash memory.
And when the nandflash controller is powered on, the programmable processor acquires the operation authority of the nandflash memory through the MUX module. When the operation right of the nandflash memory is acquired, the programmable processor sends an acquisition request to the nandflash memory, wherein the acquisition request is used for reading the configuration information of the nandflash memory. And the nandflash memory receives the acquisition request sent by the programmable processor, and sends configuration information of the nandflash memory to the programmable processor, wherein the configuration information at least comprises a first time sequence parameter of a management command of the nandflash memory and a second time sequence parameter of a control sub-command of the nandflash memory. The configuration information may further include the data length of the nandflash memory read-write data and the command type supported by the nandflash memory. The first timing parameter may be a first timing interval for the nandflash controller to execute a management command, and the second timing parameter may be a second timing interval for the nandflash controller to execute a control subcommand.
Because the nandflash controller may be associated with a plurality of nandflash memories, when the programmable processor receives the configuration information sent by the nandflash memories, the programmable processor establishes a corresponding relationship between the identifier of the nandflash memory and the configuration information; correspondingly, the step of acquiring, by the programmable processor, the first timing parameter of the management command of the nandflash memory according to the identifier of the nandflash memory may be:
and the programmable processor acquires the configuration information of the nandflash memory according to the identifier of the nandflash memory, and acquires the first time sequence parameter of the management command of the nandflash memory from the configuration information.
The first timing parameter may be a first timing interval for the nandflash controller to execute the nandflash command; the identifier of the nandflash memory can be the model of the nandflash memory, and the like.
Because the configuration information of the nandflash memory also comprises the command type supported by the nandflash memory, the programmable processor can also acquire the command type supported by the nandflash memory from the configuration information and determine whether the command type comprises the command type of the nandflash command; if yes, determining that the nandflash memory supports the nandflash command, and executing simulation cycle output of a first interface timing sequence through a programmable processor; if not, determining that the nandflash memory does not support the nandflash command, and prompting; for example, a first prompt message is displayed, and the first prompt message is used for prompting the user that the nandflash memory does not support the nandflash command.
2022: the programmable processor outputs a first interface timing by the simulation cycle according to the first timing parameter.
The programmable processor simulates the cycle output timing parameter as the first interface timing of the first timing parameter according to the first timing parameter. That is, the programmable processor simulates the cycle output time interval as the first interface time sequence of the first time interval according to the first time interval; the first interface timing includes a time to execute the nandflash command.
The programmable processor may be a Central Processing Unit (CPU), and the programmable processor outputs the first interface timing by an assembly language mode cycle.
2023: and the programmable processor executes the nandflash command to the nandflash memory according to the first interface time sequence.
If the first interface timing sequence includes the time for executing the nandflash command, this step may be: and when the time for executing the nandflash command is reached, the programmable processor executes the nandflash command on the nandflash memory.
And if the nandflash command is a management command and the management command is a Reset command, the programmable processor executes the Reset command to the nandflash memory according to the first interface timing sequence.
Step 203: if the nandflash command is a read data command or a write data command, a control sub-command and a data sub-command included in the nandflash command are obtained through the programmable processor, the simulation cycle outputs a second interface time sequence, the control sub-command is executed on the nandflash memory according to the second interface time sequence, a third interface time sequence is output through the data read-write logic circuit, and the data sub-command is executed on the nandflash memory according to the third interface time sequence.
This step can be achieved by the following steps 2031-2034, including:
2031: and if the nandflash command is a read data command or a write data command, acquiring a control sub-command and a data sub-command which are included in the nandflash command through a programmable processor.
If the nandflash command is a data reading command, the programmable processor analyzes the data reading command and acquires a control sub-command and a data sub-command of the data reading command; or if the nandflash command is a write data command, the programmable processor analyzes the write data command to obtain a control subcommand and a data subcommand of the write data command.
2032: and the programmable processor acquires a second time sequence parameter of a control subcommand of the nandflash memory according to the identifier of the nandflash memory, and simulates a cycle to output a second interface time sequence according to the second time sequence parameter.
And the programmable processor acquires the configuration information of the nandflash memory according to the identifier of the nandflash memory, and acquires a second time sequence parameter of the control subcommand of the nandflash memory from the configuration information. And according to the second time sequence parameter, the simulation cycle outputs a second interface time sequence with the time sequence parameter as the second time sequence parameter. If the second timing parameter may be a second timing interval, the step of the programmable processor outputting the second interface timing by the simulation cycle according to the second timing parameter may be:
and the programmable processor simulates the cycle output time interval to be the second interface timing of the second timing interval according to the second timing interval, wherein the second interface timing comprises the time for executing the control subcommand.
The programmable processor outputs the second interface timing via an assembly language mode cycle.
2033: and the programmable processor executes the control sub-command to the nandflash memory according to the second interface timing sequence.
If the nandflash command is a read data command, the step can be realized in the following first mode; if the nandflash command is a write data command, this step may be implemented in the following second manner.
For the first implementation, the step may be:
if the nandflash command is a data reading command, the programmable processor analyzes the data reading command according to the time sequence of the second interface when the time for executing the control subcommand of the data reading command is reached, and acquires a first storage address and a data identifier of data to be read from the control subcommand of the data reading command.
The first storage address is a storage address of data to be read; the control subcommands of the read data command are read command code, address, read command code, inquiry status register and data ready; the programmable processor executes the read command code, the address, the read command code, the query status register and the data ready according to the second interface timing, and continues to execute the query status register until the data is ready if the data is not ready.
For the second implementation, the step may be:
if the nandflash command is a data writing command, the programmable processor analyzes the data writing command according to the time sequence of the second interface when the time for executing the control subcommand of the data writing command is reached, and acquires a second storage address and data to be written from the control subcommand of the data writing command.
The second storage address is a storage address of data to be written; the control subcommands of the write data command are "program command code", "address" and "program command code", and the programmable processor executes "program command code", "address" and "program command code" according to the second interface timing sequence.
2024: and outputting a third interface time sequence through the data read-write logic circuit, and executing the data subcommand included in the nandflash command to the nandflash memory according to the third interface time sequence.
If the nandflash command is a read data command, the step can be realized in the following first mode; if the nandflash command is a write data command, this step may be implemented in the following second manner.
For the first implementation, the step may be:
and if the nandflash command is a data reading command, the data reading command carries a data identifier and a first storage address, and the data reading and writing logic circuit reads data to be read corresponding to the data identifier from a storage space corresponding to the first storage address of the nandflash memory when the time for executing the data subcommand of the data reading command is reached according to the third interface time sequence and the data subcommand of the data reading command.
After the programmable processor acquires the configuration information of the nandflash memory, the configuration information is transmitted to a data read-write logic circuit through the XBAR module; the configuration information of the nandflash memory comprises the data length of read-write data of the nandflash memory, when a data read-write logic circuit reads the data to be read corresponding to the data identifier from a storage space corresponding to a first storage address of the nandflash memory, the data to be read are divided into a plurality of first data blocks according to the data length of the read-write data of the nandflash memory, the length of each first data block is not greater than the data length of the read-write data, and one first data block is read from the storage space corresponding to the first storage address of the nandflash memory each time until a plurality of first data blocks are read completely.
After the data to be read corresponding to the data identifier is read from the storage space corresponding to the first storage address of the nandflash memory by the data read-write logic circuit, the data read-write logic circuit can directly transmit the read data to the host, and can also transmit the read data to the host through the programmable processor.
It should be noted that, before the data read-write logic circuit outputs the third interface timing sequence, the programmable processor starts the data read-write logic circuit, and transfers the operation authority for operating the nandflash memory to the data read-write logic circuit. And after the data to be read corresponding to the data identifier is read from the storage space corresponding to the first storage address stored in the nandflash by the data read-write logic circuit, the programmable processor withdraws the operation permission.
If the data read-write logic circuit directly transmits the read data to the host, the data read-write logic circuit sends a first notification message to the programmable processor for notifying the programmable processor that the data read-write logic circuit has completed the data read operation. And the programmable processor receives a first notification message sent by the data read-write logic circuit and recovers the operation authority.
If the data read-write logic circuit transmits the read data to the host through the programmable processor, the programmable processor receives the read data transmitted by the data read-write logic circuit and recovers the operation authority.
For the second implementation, the step may be:
and if the nandflash command is a data writing command, the data writing command carries a second storage address and data to be stored, and the data to be stored is stored into a storage space corresponding to the second storage address of the nandflash memory through a data reading and writing logic circuit according to the third interface time sequence and the data subcommand of the data writing command when the time for executing the data subcommand of the data writing command is reached.
The configuration information of the nandflash memory comprises the data length of read-write data of the nandflash memory, when the data read-write logic circuit stores the data to be stored into a storage space corresponding to the second storage address of the nandflash memory, the data to be stored are divided into a plurality of second data blocks according to the data length of the data read by the nandflash memory, the length of each second data block is not more than the data length of the read-write data, and one second data block is sent to the nandflash memory each time until a plurality of second data blocks are sent; and the nandflash memory receives the second data block sent by the data read-write logic circuit, stores the second data block in the storage space corresponding to the second storage address until a plurality of second data blocks are all stored in the storage space corresponding to the second storage address.
It should be noted that, before the data read-write logic circuit outputs the third interface timing sequence, the programmable processor starts the data read-write logic circuit, and transfers the operation authority for operating the nandflash memory to the data read-write logic circuit. And after the data read-write logic circuit stores the data to be stored into the storage space corresponding to the second storage address of the nandflash memory, the programmable processor recovers the operation authority.
And after the data read-write logic circuit stores the data to be stored into the storage space corresponding to the second storage address of the nandflash memory, sending a second notification message to the programmable processor for notifying the programmable processor that the data read-write logic circuit has completed data write-in operation. And the programmable processor receives a second notification message sent by the data read-write logic circuit and recovers the operation authority.
In one possible design, after the data read-write logic circuit writes the data into the storage space corresponding to the second storage address (i.e. after receiving the second notification message sent by the data read-write logic circuit), the programmable processor continues to execute the "program command code", "query status register", and "whether the command is finished"; if the command is not finished, "query status register" continues until the command is finished.
It should be noted that, for any nandflash memory associated with the nandflash controller, the nandflash command is executed on any nandflash memory according to the method. The nandflash controller takes the programmable processor as a control center, cooperates with the programmable processor and the data read-write logic circuit, works in a cooperation manner to efficiently complete nandflash commands of the nandflash memory, has an excellent upgradable characteristic, and is compatible with the nandflash memory in the future. The nandflash controller may also be integrated in an SSD (Solid State drive) controller.
In the embodiment of the invention, a programmable processor included in the nandflash controller executes a management command, a control sub-command of a read data command and a control sub-command of a write data command, and a data read-write logic circuit included in the nandflash controller executes a data sub-command of the read data command and a data sub-command of the write data command; because the programmable processor is added in the nandflash controller, the programmable processor can simulate the cycle to output the first interface time sequence and the second interface time sequence, so that the advantages of flexible programming of the programmable processor and efficient concurrent processing of the data read-write logic circuit are compatible, the nandflash controller can be compatible with nandflash commands of nandflash memories of different manufacturers and different models, and the compatibility of the nandflash controller is improved.
Referring to fig. 4, an embodiment of the present invention provides an apparatus for executing nandflash commands, which includes a programmable processor 301 and a data read/write logic circuit 302.
The programmable processor 301 is configured to execute the control subcommand and the data subcommand included in the nandflash command in steps 201, 202, and 203 in the foregoing embodiment, the simulation cycle outputs a second interface timing, and executes the control subcommand and an alternative option thereof for the nandflash memory according to the second interface timing.
The data read/write logic circuit 302 is configured to execute the output third interface timing in step 203 in the foregoing embodiment, and execute the data subcommand and its optional options for the nandflash memory according to the third interface timing.
In the embodiment of the invention, a programmable processor included in the nandflash controller executes a management command, a control sub-command of a read data command and a control sub-command of a write data command, and a data read-write logic circuit included in the nandflash controller executes a data sub-command of the read data command and a data sub-command of the write data command; because the programmable processor is added in the nandflash controller, the programmable processor can simulate the cycle to output the first interface time sequence and the second interface time sequence, so that the advantages of flexible programming of the programmable processor and efficient concurrent processing of the data read-write logic circuit are compatible, the nandflash controller can be compatible with nandflash commands of nandflash memories of different manufacturers and different models, and the compatibility of the nandflash controller is improved.
It should be noted that: in the nandflash command executing device provided in the above embodiment, when the nandflash command is executed, only the division of the functional modules is taken as an example, and in practical applications, the function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the apparatus for executing a nandflash command and the method embodiment for executing a nandflash command provided by the above embodiments belong to the same concept, and specific implementation processes thereof are detailed in the method embodiment and are not described herein again.
The term "and/or" in the embodiment of the present invention is only one kind of association relationship describing an associated object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A method for executing a storage type flash memory command, wherein the method is applied to a nandflash controller of a storage type flash memory, the nandflash controller comprises a programmable processor and a data read-write logic circuit, and the method comprises the following steps:
receiving, by the programmable processor, a nandflash command, the nandflash command being for operating a nandflash memory associated with the nandflash controller;
if the nandflash command is a management command, simulating a cycle through the programmable processor to output a first interface time sequence, and executing the nandflash command on the nandflash memory according to the first interface time sequence;
if the nandflash command is a read data command or a write data command, acquiring a control sub-command and a data sub-command which are included by the nandflash command through the programmable processor, outputting a second interface time sequence by a simulation cycle, executing the control sub-command on the nandflash memory according to the second interface time sequence, starting the data read-write logic circuit, transferring the operation authority of the nandflash memory to the data read-write logic circuit through the programmable processor, outputting a third interface time sequence through the data read-write logic circuit, and executing the data sub-command on the nandflash memory according to the third interface time sequence;
if the execution of the data subcommand is completed, the programmable processor withdraws the operation authority;
the outputting, by the programmable processor emulation cycle, a first interface timing sequence includes: acquiring a first time sequence parameter of a management command from the associated nandflash memory through the programmable processor according to the identifier of the nandflash memory, simulating a cycle to output a first interface time sequence according to the first time sequence parameter, and associating at least one nandflash memory with the nandflash controller.
2. The method of claim 1, wherein prior to receiving a nandflash command by the programmable processor, the method further comprises:
obtaining, by the programmable processor, operating permissions of the nandflash memory from the nandflash memory.
3. The method of claim 1, wherein said outputting, by said programmable processor emulation cycle, a second interface timing comprises:
and acquiring a second time sequence parameter of a control subcommand of the nandflash memory by the programmable processor according to the identifier of the nandflash memory, and simulating a cycle to output a second interface time sequence according to the second time sequence parameter.
4. The method of claim 1, wherein the executing, by the programmable processor, the control subcommand on the nandflash memory according to the second interface timing comprises:
if the nandflash command is the data reading command, analyzing the data reading command through the programmable processor according to the second interface time sequence, and acquiring a first storage address and a data identifier of data to be read from a control sub-command of the data reading command;
and if the nandflash command is the data writing command, analyzing the data writing command through the programmable processor according to the second interface time sequence, and acquiring a second storage address and a data identifier of data to be written from a control sub-command of the data writing command.
5. The method of claim 1, wherein the executing, by the data read/write logic circuit, the data subcommand included in the nandflash command on the nandflash memory according to the third interface timing comprises:
if the nandflash command is the data reading command, the data reading command carries a data identifier and a first storage address, and data to be read corresponding to the data identifier is read from a storage space corresponding to the first storage address of the nandflash memory through the data reading and writing logic circuit according to the third interface timing sequence and a data sub-command of the data reading command;
and if the nandflash command is the data writing command, the data writing command carries a second storage address and data to be stored, and the data to be stored is stored into a storage space corresponding to the second storage address of the nandflash memory through the data reading and writing logic circuit according to the third interface time sequence and the data subcommand of the data writing command.
6. An apparatus for executing a storage flash memory command, the apparatus comprising:
the nandflash controller comprises a programmable processor and a nandflash controller, wherein the programmable processor is used for receiving a nandflash command, and the nandflash command is used for operating a nandflash memory associated with the nandflash controller;
if the nandflash command is a management command, the programmable processor is also used for simulating a cycle to output a first interface time sequence, and executing the nandflash command on the nandflash memory according to the first interface time sequence;
if the nandflash command is a read data command or a write data command, the programmable processor is further configured to acquire a control subcommand and a data subcommand included in the nandflash command, simulate a cycle to output a second interface timing sequence, and execute the control subcommand on the nandflash memory according to the second interface timing sequence;
the programmable processor is also used for starting a data read-write logic circuit and transferring the operation authority of the nandflash memory to the data read-write logic circuit;
the data read-write logic circuit is used for outputting a third interface time sequence and executing the data subcommand on the nandflash memory according to the third interface time sequence;
the programmable processor is further used for recovering the operation authority if the execution of the data subcommand is completed;
the programmable processor is further configured to acquire a first timing parameter of the management command from the associated nandflash memory according to the identifier of the nandflash memory, simulate a cycle to output a first interface timing according to the first timing parameter, and associate the nandflash controller with at least one nandflash memory.
7. The apparatus of claim 6,
the programmable processor is also used for acquiring the operation authority of the nandflash memory from the nandflash memory.
8. The apparatus of claim 6,
the programmable processor is further configured to acquire a second timing parameter of a control subcommand of the nandflash memory according to the identifier of the nandflash memory, and simulate a cycle to output a second interface timing according to the second timing parameter.
9. The apparatus of claim 6,
if the nandflash command is the read data command, the programmable processor is further configured to analyze the read data command according to the second interface timing sequence, and obtain a first memory address and a data identifier of data to be read from a control sub-command of the read data command;
if the nandflash command is the write data command, the programmable processor is further configured to analyze the write data command according to the second interface timing sequence, and obtain a second storage address and a data identifier of data to be written from a control subcommand of the write data command.
10. The apparatus of claim 6,
if the nandflash command is the read data command, the read data command carries a data identifier and a first storage address, and the data read-write logic circuit is further configured to read data to be read corresponding to the data identifier from a storage space corresponding to the first storage address of the nandflash memory according to the third interface timing sequence and a data sub-command of the read data command;
and if the nandflash command is the data writing command, the data writing command carries a second storage address and data to be stored, and the data reading and writing logic circuit is further configured to store the data to be stored into a storage space corresponding to the second storage address of the nandflash memory according to the third interface timing sequence and a data sub-command of the data writing command.
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| CN101162449B (en) * | 2007-10-08 | 2010-06-02 | 福州瑞芯微电子有限公司 | NAND FLASH controller and data interactive method with NAND FLASH chip |
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