CN113485882A - Chip verification method and device and computer readable storage medium - Google Patents
Chip verification method and device and computer readable storage medium Download PDFInfo
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Abstract
The invention discloses a chip verification method, a chip verification device and a computer readable storage medium, which are used for initializing environmental parameters of a module to be verified after a verification instruction is received; analyzing and extracting configuration information in the first electronic form from a preset directory according to the script, and verifying according to the configuration information to obtain a corresponding verification result; and mapping the verification result to a preset second electronic form so as to judge whether the verification is passed. The invention can realize full-automatic verification.
Description
Technical Field
The present invention relates to the field of vehicle technologies, and in particular, to a chip verification method and apparatus, and a computer-readable storage medium.
Background
With the improvement of the technological level, the integrated circuit industry has been rapidly developed. The chip scale is getting larger and the design integration level is also getting more and more complex, which further leads to the workload of chip verification getting larger and larger.
At present, the verification test of the chip also needs a verification engineer to manually construct a test case, which is time-consuming.
Disclosure of Invention
The invention mainly aims to provide a chip verification method, a chip verification device and a computer-readable storage medium, and aims to realize automatic verification.
In order to achieve the above object, the present invention provides a chip verification method, which comprises the following steps:
after receiving a verification instruction, initializing the environment parameters of the module to be verified;
analyzing and extracting configuration information in the first electronic form from a preset directory according to the script, and verifying according to the configuration information to obtain a corresponding verification result;
and mapping the verification result to a preset second electronic form so as to judge whether the verification is passed.
Optionally, the step of mapping the verification result to a preset second electronic form to determine whether the verification passes includes:
analyzing the verification result to obtain a corresponding record file;
and calculating the running time according to the starting and ending time of the record file, and mapping the record file to a second electronic form corresponding to the module to be verified through python to judge whether the verification is passed.
Optionally, after receiving the verification instruction, the initializing the environment parameter of the module to be verified includes:
and controlling the reset of each module to be verified, and determining that the initialization of each module to be verified is completed when detecting that the reset completion signal of each module to be verified is at a high level.
Optionally, the analyzing and extracting configuration information of the first electronic form in the preset directory according to the script, and verifying according to the configuration information to obtain a corresponding verification result includes:
analyzing the configuration information of the first electronic form to obtain the name of the corresponding module to be tested;
and executing corresponding verification codes for the modules to be verified according to the test module names so as to complete the verification of the modules to be verified.
Optionally, the step of executing a corresponding verification code on each module to be verified according to the test module name to complete verification of the module to be verified further includes:
configuring a verification environment, and analyzing parameters of a corresponding module according to the name of the test module;
and assigning the module parameters obtained by analysis to the global variables of the corresponding modules, and verifying the module to be verified by adopting the simulation mode corresponding to the modules.
Optionally, mapping the verification result to a preset second electronic form to determine whether the verification passes includes:
extracting the verification result of each module to be verified, and counting;
and sending the statistical data to the corresponding mailbox according to the preset format.
Optionally, the chip verification method further includes:
receiving a verification progress checking instruction triggered by a user;
and obtaining and displaying corresponding statistical data according to the verification progress checking instruction.
Optionally, the step of obtaining and displaying corresponding statistical data according to the progress viewing instruction includes:
verifying the user authority corresponding to the verification progress checking instruction;
and after the user authority passes, acquiring and displaying corresponding statistical data.
In addition, to achieve the above object, the present invention also provides a chip verification apparatus, including: a memory, a processor and a chip verification program stored on the memory and executable on the processor, the chip verification program when executed by the processor implementing the steps of the chip verification method as described above.
Further, to achieve the above object, the present invention also provides a computer readable storage medium having stored thereon a chip authentication program, which when executed by a processor, implements the steps of the chip authentication method as described above.
According to the chip verification method, the chip verification device and the computer-readable storage medium, after the verification instruction is received, the environment parameters of the module to be verified are initialized; analyzing and extracting configuration information of a first electronic form in a preset directory according to the script, and verifying according to the configuration information to obtain a corresponding verification result; and mapping the verification result to a preset second electronic form so as to judge whether the verification is passed. Through the mode, the information such as the test cases used for verification is stored in the preset directory as the configuration information, and during verification, the configuration information can be directly obtained from the preset directory, so that the verification can be performed on each module, and a user does not need to additionally manufacture the test cases during verification every time, so that the automatic verification is completely realized.
Further, single or multiple automated verifications may be made based on module names in the configuration information.
Furthermore, the module parameters obtained by analysis are assigned to the global variables of the corresponding modules, so that assignment is uniformly performed in a global variable mode, and uniform management and data maintenance are facilitated.
Drawings
FIG. 1 is a schematic diagram of an apparatus in a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a first embodiment of a chip verification method according to the present invention;
FIG. 3 is a schematic diagram of a user data display interface according to an embodiment of the chip verification method of the invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The scale of the chip is larger and larger, the design integration level is more and more complex, and the latest chip design and manufacturing process reaches a 5nm process technology. At present, in emerging fields such as artificial intelligence and the internet of things, the workload of chip verification is increasing due to the fact that a single-core or multi-core processor, a complex on-chip interconnection bus, low-speed and high-speed interfaces, a memory and various IPs are integrated by an SOC (system on chip) chip with more applications.
Although some verification techniques are proposed and applied at present, the existing verification techniques only focus on a certain pain point in the verification process to propose an improvement scheme, and can also accelerate development speed and improve verification efficiency in practical application, but engineering is required to additionally manufacture verification scripts when different modules are verified each time.
According to the chip verification method, the chip verification device and the computer-readable storage medium, after the verification instruction is received, the environment parameters of the module to be verified are initialized; analyzing and extracting configuration information of a first electronic form in a preset directory according to the script, and verifying according to the configuration information to obtain a corresponding verification result; and mapping the verification result to a preset second electronic form so as to judge whether the verification is passed. Through the mode, the information such as the test cases used for verification is stored in the preset directory as the configuration information, and during verification, the configuration information can be directly obtained from the preset directory, so that the verification can be performed on each module, and a user does not need to additionally manufacture the test cases during verification every time, so that the automatic verification is completely realized.
Further, single or multiple automated verifications may be made based on module names in the configuration information.
Furthermore, the module parameters obtained by analysis are assigned to the global variables of the corresponding modules, so that assignment is uniformly performed in a global variable mode, and uniform management and data maintenance are facilitated.
As shown in fig. 1, fig. 1 is a schematic terminal structure diagram of a hardware operating environment according to an embodiment of the present invention.
The terminal of the embodiment of the invention can be a vehicle-mounted PC, and can also be a mobile terminal device with a computing function, such as a smart phone, a tablet computer, a portable computer and the like.
As shown in fig. 1, the terminal may include: a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface). The memory 1005 may be a high-speed RAM memory or a non-volatile memory (e.g., a magnetic disk memory). The memory 1005 may alternatively be a storage device separate from the processor 1001.
Preferably, the terminal may further include a camera, a Radio Frequency (RF) circuit, a sensor, an audio circuit, a WiFi module, and the like. Such as light sensors, motion sensors, and other sensors. Specifically, the light sensor may include an ambient light sensor that may adjust the brightness of the display screen according to the brightness of ambient light, and a proximity sensor that may turn off the display screen and/or the backlight when the mobile terminal is moved to the ear. As one of the motion sensors, the gravity acceleration sensor can detect the magnitude of acceleration in each direction (generally, three axes), detect the magnitude and direction of gravity when the mobile terminal is stationary, and can be used for applications (such as horizontal and vertical screen switching, related games, magnetometer attitude calibration), vibration recognition related functions (such as pedometer and tapping) and the like for recognizing the attitude of the mobile terminal; of course, the mobile terminal may also be configured with other sensors such as a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor, which are not described herein again.
Those skilled in the art will appreciate that the terminal structure shown in fig. 1 is not intended to be limiting and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
As shown in fig. 1, a memory 1005, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and a chip authentication program.
In the terminal shown in fig. 1, the network interface 1004 is mainly used for connecting to a backend server and performing data communication with the backend server; the user interface 1003 is mainly used for connecting a client (user side) and performing data communication with the client; and the processor 1001 may be configured to call the chip verification program stored in the memory 1005 and perform the following operations:
further, the processor 1001 may call a chip verification program stored in the memory 1005, and also perform the following operations:
acquiring environmental information of a vehicle driving road through an environmental perception sensor;
the step of obtaining the information of the traffic participants on the driving road of the vehicle through the environment perception sensor comprises the following steps:
and judging whether collision occurs or not according to the environmental information, the predicted running path and the future motion path of the vehicle.
The specific embodiment of the chip verification device applied in the present invention is substantially the same as the embodiments of the chip verification method described below, and is not described herein again.
Referring to fig. 2, fig. 2 is a schematic flow chart of a first embodiment of a chip verification method of the present invention, the chip verification method including:
step S100, after receiving a verification instruction, initializing the environmental parameters of a module to be verified;
in the embodiment, a verification platform is constructed firstly, the verification platform comprises an automatic control sub-platform, configuration information and simulation output, in the verification process, the verification platform can generate a corresponding verification instruction according to verification operation triggered by a user, certainly, the verification process can be triggered regularly, the verification instruction is generated correspondingly, the verification platform starts simulation verification, and each module to be verified is controlled firstly to initialize, so that influence caused by historical data in each module to be verified is avoided.
Step S200, analyzing and extracting configuration information in a first electronic form from a preset directory according to a script, and verifying according to the configuration information to obtain a corresponding verification result;
the automation control sub-platform extracts configuration information in the first electronic form from a preset directory according to the script, wherein the configuration information can comprise parameters such as test case names, random seeds, simulation tools (VCS/XRUN) and the like. The configuration information may be set according to specific situations, and in this embodiment, the configuration information may include:
test case name TESTCASE: is used for describing the attributes and functions of the simulation.
Test MODULE NAME MODULE _ NAME: a module for indicating execution of the simulation. If MODULE _ NAME is all, then the simulation executes all IP/MODULEs.
RANDOM SEED RANDOM _ SEED: the random seeds corresponding to the test cases can be customized and can be randomly generated by a user.
Simulation cycle number LOOP _ N: the number of iterations required for the simulation.
Simulation tool TOOLS: sysnopsys vcs and cadence xrun are optional.
The USER-defined constraint USER _ constraints: the user is used to assign custom values to global variables in the verification environment.
Printing LEVEL LEVEL: UVM _ LOW, UVM _ MEDIUM, UVM _ DEBUG, UVM _ HIGH.
Code VERSION: and the GIT or SVN version number of the module to be tested.
And in the verification process, correspondingly verifying the module to be verified according to the obtained configuration information, and obtaining a verification result after the verification is finished.
Step S300, mapping the verification result to a preset second electronic form to determine whether the verification passes.
And comparing the obtained verification result with a preset second electronic form, and comparing whether the verification result is matched with the data of the second electronic form, namely mapping the verification result to the second electronic form so as to judge whether the verification is passed.
According to the chip verification method, the chip verification device and the computer-readable storage medium, after the verification instruction is received, the environment parameters of the module to be verified are initialized; analyzing and extracting configuration information of a first electronic form in a preset directory according to the script, and verifying according to the configuration information to obtain a corresponding verification result; and mapping the verification result to a preset second electronic form so as to judge whether the verification is passed. Through the mode, the information such as the test cases used for verification is stored in the preset directory as the configuration information, and during verification, the configuration information can be directly obtained from the preset directory, so that the verification can be performed on each module, and a user does not need to additionally manufacture the test cases during verification every time, so that the automatic verification is completely realized.
Further, based on the above embodiment, step S300: the step of mapping the verification result to a preset second electronic form to determine whether the verification passes may include:
step S310, analyzing the verification result to obtain a corresponding record file;
step S320, calculating the running time according to the starting and ending time of the record file, and mapping the record file to a second electronic form corresponding to the module to be verified through python to judge whether the verification is passed.
In this embodiment, the process of determining whether each module to be verified passes includes analyzing the verification result to obtain a verified record file, which includes but is not limited to: simulation running starting time information, ending time and a verification result of simulation verification.
As an example, in the present embodiment, log files with the test case name + RANDOM SEED as the name, such as $ (TESTCASE) _$ (RANDOM _ SEED) _ log file, and a python parsing script matches the corresponding log file according to parameters TESTCASE and RANDOM _ SEED in the parsed electronic form, and records information such as UVM _ facial/UVM _ warning/UVM _ ERROR in the file. The second electronic form also has corresponding information such as completion time information, UVM _ facial/UVM _ warning/UVM _ ERROR.
Further, based on the above embodiment, step S100: after receiving the verification instruction, the step of initializing the environmental parameters of the module to be verified comprises the following steps:
and controlling the reset of each module to be verified, and determining that the initialization of each module to be verified is completed when detecting that the reset completion signal of each module to be verified is at a high level.
Before verification, the present embodiment initializes each module, that is, initializes a verification environment, initializes $ PXP _ HOME as the current root directory of the item, and after the clock signal clk is valid, it needs to wait for all the reset completion signals rst _ n of each module to be high level at this stage before entering the next step.
Further, based on the above embodiment, step S200: the step of analyzing and extracting configuration information of a first electronic form in a preset directory according to the script, verifying according to the configuration information and obtaining a corresponding verification result comprises the following steps:
step S210, analyzing the configuration information of the first electronic form to obtain the name of the corresponding module to be tested;
step S220, executing corresponding verification codes to each module to be verified according to the test module name so as to complete verification of the module to be verified.
In this embodiment, the parameters of the electronic form are analyzed, after the verification environment is initialized, the electronic form of the corresponding module in the electronic form of the subsystem is analyzed, and the parameters of the test module name, the test case name _ name, the testcase, the random seed _ seed, the simulation tools, the simulation cycle times loop _ n, and the like are extracted. If module _ name is spi, the simulation Makefile script only executes spi module codes, and the verification of a certain module is completed; and if the module _ name is all, executing the full-chip code by the simulation Makefile script, and finishing the full-chip verification.
Further, based on the above embodiment, step S220: the step of executing corresponding verification codes for each module to be verified according to the test module name to complete the verification of the module to be verified further comprises the following steps:
step S221, configuring a verification environment, and analyzing parameters of a corresponding module according to the test module name;
step S222, assigning the module parameters obtained by analysis to the global variables of the corresponding modules, and verifying the module to be verified by adopting the simulation mode corresponding to the modules.
In this embodiment, in the verification process: and configuring a verification environment, analyzing the parameters of the corresponding modules and assigning to the global variables of the modules according to the module _ name string marks in the electronic form, and uniformly adopting the global variables to avoid independently making corresponding test cases for each module. The simulation verification mode selects sim _ mode, two different simulation modes are designed according to different stages of chip front-end verification, and corresponding modes can be adopted for simulation verification if different module verification requirements are different, specifically, single-use case simulation sim _ mode ═ signal and regression case simulation $ (sim _ mode) $ regression. The simulation tool is set to vcs or xrun according to tools.
Further, based on the above embodiment, after the step of mapping the verification result to a preset second electronic form to determine whether the verification passes, the method includes:
s400, extracting the verification result of each module to be verified and counting;
and S500, sending the statistical data to the corresponding mailbox according to the preset format.
After the verification result is obtained, the verification result is output to a corresponding directory for storage, a simulation log file is loaded through a python script, the simulation result is analyzed, then the simulation result is counted, and a corresponding statistical verification result is obtained, wherein the verification result comprises verification success, verification failure and the like, and the counted data can be sent to a corresponding user in a mailbox mode according to a preset format, so that the situation that the statistical data can only be obtained through manual inquiry in the prior art is avoided. In specific implementation, the statistical data can be sent to corresponding users through short messages or smart phones and the like.
Further, based on the above embodiment, the chip verification method further includes:
step S600, receiving a verification progress checking instruction triggered by a user;
and S700, obtaining corresponding statistical data according to the verification progress checking instruction and displaying the statistical data.
In order to facilitate the use of the user, the implementation provides a field viewing function besides a mail mode, the analysis result is firstly stored in the second electronic form, then the second electronic form is stored in the database, and the user can trigger the verification progress viewing instruction through the management device, so that the corresponding statistical data can be obtained from the storage catalog of the database and then displayed to the user, and the visualization is realized.
Further, step S700: obtaining corresponding statistical data according to the progress viewing instruction, and displaying the statistical data, wherein the step comprises the following steps:
step S710, verifying the user authority corresponding to the verification progress checking instruction;
and step S720, after the user authority passes, acquiring and displaying corresponding statistical data.
Further, in this embodiment, when a viewing instruction triggered by a user is received, the authority of the user may also be verified, and after the authority verification is passed, the corresponding statistical data is obtained and displayed, otherwise, the user is prompted that the authority is insufficient.
Further, in order to improve the system function, in this embodiment, the users are divided into common users and management users, the management users can also set the permissions of the common users, including opening the related permissions of the common users, adding new users, deleting user data, and adding or deleting mailbox addresses of the mail system, and the administrator can view not only the simulation information of each IP/module, but also subsystem or system level statistical data. The management user can view the project verification progress detailed data. The method comprises the total number of planning cases of each subsystem/module, the number of completed simulation cases, simulation passing rate and function coverage rate data, chip overall planning cases, chip executed simulation cases, chip overall simulation passing rate, chip overall coverage rate data and code version number of executed simulation. For convenience of use, the user data display interface may be as shown in fig. 3, and may include: a plurality of subsystems, wherein a subsystem (subsystem 1 shown in the figure) can: a module planning use case total window, a module completed use case total window, a module simulation passing rate window, a module function coverage rate window and a module BUG tracking curve window. A subsystem planning case total number window, a subsystem planning case simulation passing rate window and a kilometer coverage rate window (the function coverage rate is the verification process rate)
In addition, an embodiment of the present invention further provides a computer-readable storage medium, where a chip verification program is stored on the computer-readable storage medium, and when executed by a processor, the chip verification program implements the steps of the chip verification method described above.
The specific embodiment of the computer-readable storage medium of the present invention is substantially the same as the embodiments of the chip verification method described above, and is not described herein again.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A chip verification method is characterized by comprising the following steps:
after receiving a verification instruction, initializing the environment parameters of the module to be verified;
analyzing and extracting configuration information in the first electronic form from a preset directory according to the script, and verifying according to the configuration information to obtain a corresponding verification result;
and mapping the verification result to a preset second electronic form so as to judge whether the verification is passed.
2. The chip verification method of claim 1, wherein the step of mapping the verification result to a preset second electronic form to determine whether the verification passes comprises:
analyzing the verification result to obtain a corresponding record file;
and calculating the running time according to the starting and ending time of the record file, and mapping the record file to a second electronic form corresponding to the module to be verified through python to judge whether the verification is passed.
3. The chip verification method according to claim 1, wherein the step of initializing the environment parameters of the module to be verified after receiving the verification instruction comprises:
and controlling the reset of each module to be verified, and determining that the initialization of each module to be verified is completed when detecting that the reset completion signal of each module to be verified is at a high level.
4. The chip verification method according to claim 1, wherein the step of parsing and extracting configuration information of the first electronic form in a preset directory according to the script and performing verification according to the configuration information to obtain a corresponding verification result comprises:
analyzing the configuration information of the first electronic form to obtain the name of the corresponding module to be tested;
and executing corresponding verification codes for the modules to be verified according to the test module names so as to complete the verification of the modules to be verified.
5. The chip verification method according to claim 4, wherein the step of executing the corresponding verification code for each module to be verified according to the test module name to complete verification of the module to be verified further comprises:
configuring a verification environment, and analyzing parameters of a corresponding module according to the name of the test module;
and assigning the module parameters obtained by analysis to the global variables of the corresponding modules, and verifying the module to be verified by adopting the simulation mode corresponding to the modules.
6. The chip verification method according to claim 1, wherein the step of mapping the verification result to a preset second electronic form to determine whether the verification passes comprises:
extracting the verification result of each module to be verified, and counting;
and sending the statistical data to the corresponding mailbox according to the preset format.
7. The chip verification method of claim 6, further comprising:
receiving a verification progress checking instruction triggered by a user;
and obtaining and displaying corresponding statistical data according to the verification progress checking instruction.
8. The chip verification method according to claim 7, wherein the step of obtaining and displaying the corresponding statistical data according to the progress viewing instruction comprises:
verifying the user authority corresponding to the verification progress checking instruction;
and after the user authority passes, acquiring and displaying corresponding statistical data.
9. A chip verification apparatus, comprising: memory, a processor and a chip authentication program stored on the memory and executable on the processor, the chip authentication program when executed by the processor implementing the steps of the chip authentication method according to any one of claims 1 to 8.
10. A computer-readable storage medium, having stored thereon a chip authentication program, which when executed by a processor implements the steps of the chip authentication method according to any one of claims 1 to 8.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113986641A (en) * | 2021-12-28 | 2022-01-28 | 苏州浪潮智能科技有限公司 | Method, system, equipment and storage medium for verifying chip hardware function |
| CN117056897A (en) * | 2023-10-13 | 2023-11-14 | 沐曦集成电路(上海)有限公司 | Configuration information processing method for chip verification, electronic device and medium |
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