CN102999663A - Method for verifying MMU (Memory Management Unit) in SOC (System On Chip) - Google Patents
Method for verifying MMU (Memory Management Unit) in SOC (System On Chip) Download PDFInfo
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- CN102999663A CN102999663A CN2012104685846A CN201210468584A CN102999663A CN 102999663 A CN102999663 A CN 102999663A CN 2012104685846 A CN2012104685846 A CN 2012104685846A CN 201210468584 A CN201210468584 A CN 201210468584A CN 102999663 A CN102999663 A CN 102999663A
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Abstract
The invention discloses a method for verifying an MMU (Memory Management Unit) in an SOC (System On Chip). The method comprises the steps that a page table generation unit generates a page table file after reading a page table configuration file, and a memory model initializes and stores the page table file in a page table memory address appointed in an MMU configuration file; a special circuit behavior generation model automatically reads a special circuit configuration file, and initiates a read-write transmission behavior according to the special circuit configuration file; the MMU to be verified designs and automatically reads the MMU configuration file, accepts the transmission behavior initiated by the special circuit behavior generation model, reads page table information from the page table memory address in the memory model, maps virtual and real addresses, and initiates a post-map address transmission behavior; a C model code reads an original address file and a page table generation configuration file, and generates an expected post-map address file; and a file comparison unit automatically reads a practical post-map address file and the expected post-map address file, compares the two files, and outputs a verification result whether to be correct or not.
Description
[technical field]
The invention belongs to integrated circuit fields, specifically refer to the verification method of the MMU in a kind of SOC chip.
[background technology]
MMU is the abbreviation of Memory Management Unit, Chinese name is memory management unit, be considered to traditionally to be used in the central processing unit (CPU) operation circuit of managing virtual storer, physical storage, also being responsible for virtual address map simultaneously is physical address, and the internal storage access mandate that hardware mechanisms is provided.
Progress along with technology, a large amount of appearance of ultra-large SOC chip, there is a large amount of independent dedicated processes circuit modules among the SOC, such as the graph and image processing circuit, the memory headroom that needs is increasing, if do not use virtual address space, operating system be difficult to satisfy opens up one section continuous physical address space and satisfies the dedicated processes circuit requirements.Because the operating system of handheld device is day by day complicated, operating system expects that all programs can operate in the virtual address space, so various dedicated processes circuit is also more and more stronger to the demand of MMU simultaneously.
Because MMU only is used for CPU usually in the past, verification environment is the MMU structure of specific aim checking CPU also, lacks at present the verification method that the MMU of various IP is verified in a kind of general can being used for.
In view of this, the inventor furthers investigate for the defective of prior art, and has this case to produce.
[summary of the invention]
Technical matters to be solved by this invention is to provide the verification method of the MMU in a kind of SOC chip.
The present invention solves the problems of the technologies described above by the following technical solutions:
The verification method of MMU in a kind of SOC chip comprises the steps:
Step 1: fill in the special circuit configuration file, describe the behavior that special circuit is initiated transmission;
In the described special circuit configuration file, it is the configuration information that the configure dedicated circuit is initiated the behavior of transmission;
Step 2: fill in the MMU configuration file, describe the storage address of page table in memory model, the information of page table size;
Described MMU configuration file comprises the storage address of page table in memory model, the information of page table size;
Described memory model is responsible for the storage data, comprises page table memory block and data field, deposits respectively page table and other data;
Step 3: fill in page table and produce configuration file, describe the page table size, the page table information of actual situation address mapping relation, wherein the page table size is consistent with the page table size information in the described MMU configuration file;
Described page table produces in the configuration file, comprises the page table information of actual situation address mapping relation;
Step 4: after verification platform is started working, the page table generation unit reads in and produces the page table file that is used for depositing in the required form of described memory model after described page table produces configuration file, and then described memory model enters the initialization of page table file the page table storage address of appointment in the described MMU configuration file;
Step 5: special circuit behavior generation model reads in described special circuit configuration file automatically, and initiates the read-write transport behavior according to described special circuit configuration file, and wherein reference address is random address;
Described special circuit behavior generation model is responsible for the model according to special circuit configuration file initiation read-write transport behavior, is used for simulating the transport behavior of actual special circuit;
Step 6: described MMU configuration file is read in MMU design to be verified automatically, then accept the transport behavior that described special circuit behavior generation model is initiated, then the page table memory address in the described memory model reads page table information, carries out sending after the mapping of actual situation address the transport behavior of address after the mapping;
Step 7: in the whole transmission course, original transmitted behavior collecting unit and actual transmissions behavior collecting unit gather all special circuit behavior generation models all the time to MMU design to be verified, MMU to be verified is designed into the transport behavior between the memory model, and produces respectively original address file and the rear address file of actual mapping according to the address information in the transport behavior;
Step 8: repeating step 4-step 7, until all transport behaviors finish;
Step 9: after all transport behaviors finish, the C model code reads in the original address file and page table produces configuration file, the map information that produces in the configuration file according to page table transfers the virtual address of original address file to after the mapping real address, and produces address file after the expectation mapping;
Step 10: the file comparing unit is responsible for automatically reading that address file and expectation shine upon rear address file after the actual mapping, then two files is compared whether correct the result of rear Output rusults.
Further, described special circuit is initiated the behavior of transmission, comprises different burst transfer length, different data bit widths.
Further, described file comparing unit can be reported the address that begins to occur mistake, the position that makes things convenient for the checking personnel to locate errors.
The invention has the advantages that: 1, come the behavior of configuration of IP behavior model for the characteristic of various IP, random address can obtain larger checking coverage rate; 2, page table produces automatically, automatic loading, and flexible configuration can cover multiple page table type and page table length; 3, the transport behavior collecting unit can gather the behavior of special circuit in the used proof procedure and produce address file, and the address date that this process can make identifier person observe in the whole special circuit course of work flows, and makes things convenient for checking personnel debug.
[description of drawings]
The invention will be further described in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is groundwork schematic flow sheet of the present invention.
[embodiment]
As shown in Figure 1, the verification method of the MMU in a kind of SOC chip comprises the steps:
Step 1: fill in the special circuit configuration file, describe the behavior that special circuit is initiated transmission;
In the described special circuit configuration file, it is the configuration information that the configure dedicated circuit is initiated the behavior of transmission;
Described special circuit is initiated the behavior of transmission, can comprise multiple transport behavior, comprises different burst transfer length, different data bit widths etc.;
Step 2: fill in the MMU configuration file, describe the storage address of page table in memory model, the information of page table size;
Described MMU configuration file comprises the storage address of page table in memory model, the information of page table size;
Described memory model is responsible for the storage data, comprises page table memory block and data field, deposits respectively page table and other data;
Step 3: fill in page table and produce configuration file, describe the page table size, the page table information of actual situation address mapping relation, wherein the page table size is consistent with the page table size information in the described MMU configuration file;
Described page table produces in the configuration file, comprises the page table information of actual situation address mapping relation;
Step 4: after verification platform is started working, the page table generation unit reads in and produces the page table file that is used for depositing in the required form of described memory model after described page table produces configuration file, and then described memory model enters the initialization of page table file the page table storage address of appointment in the described MMU configuration file;
Step 5: special circuit behavior generation model reads in described special circuit configuration file automatically, and initiates the read-write transport behavior according to described special circuit configuration file, and wherein reference address is random address;
Described special circuit behavior generation model is responsible for the model according to special circuit configuration file initiation read-write transport behavior, is used for simulating the transport behavior of actual special circuit;
Step 6: described MMU configuration file is read in MMU design to be verified automatically, then accept the transport behavior that described special circuit behavior generation model is initiated, then the page table memory address in the described memory model reads page table information, carries out sending after the mapping of actual situation address the transport behavior of address after the mapping;
Step 7: in the whole transmission course, original transmitted behavior collecting unit and actual transmissions behavior collecting unit gather all special circuit behavior generation models all the time to MMU design to be verified, MMU to be verified is designed into the transport behavior between the memory model, and produces respectively original address file and the rear address file of actual mapping according to the address information in the transport behavior;
Step 8: repeating step 4-step 7, until all transport behaviors finish;
Step 9: after all transport behaviors finish, the C model code reads in the original address file and page table produces configuration file, the map information that produces in the configuration file according to page table transfers the virtual address of original address file to after the mapping real address, and produces address file after the expectation mapping;
Step 10: the file comparing unit is responsible for automatically reading that address file and expectation shine upon rear address file after the actual mapping, then two files is compared whether correct the result of rear Output rusults.Described file comparing unit can be reported the address that begins to occur mistake, the position that makes things convenient for the checking personnel to locate errors.
If the result is correct, show that the function of MMU design to be verified is correct, otherwise capability error needs debug.
Beneficial effect of the present invention is: 1, come the behavior of configuration of IP behavior model for the characteristic of various IP, random address can obtain larger checking coverage rate; 2, page table produces automatically, automatic loading, and flexible configuration can cover multiple page table type and page table length; 3, the transport behavior collecting unit can gather the behavior of special circuit in the used proof procedure and produce address file, and the address date that this process can make identifier person observe in the whole special circuit course of work flows, and makes things convenient for checking personnel debug.
The above only is better enforcement use-case of the present invention, is not be used to limiting protection model figure of the present invention.Within the spirit and principles in the present invention all, any modification of doing, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. the verification method of the MMU in the SOC chip is characterized in that: comprise the steps:
Step 1: fill in the special circuit configuration file, describe the behavior that special circuit is initiated transmission;
In the described special circuit configuration file, it is the configuration information that the configure dedicated circuit is initiated the behavior of transmission;
Step 2: fill in the MMU configuration file, describe the storage address of page table in memory model, the information of page table size;
Described MMU configuration file comprises the storage address of page table in memory model, the information of page table size;
Described memory model is responsible for the storage data, comprises page table memory block and data field, deposits respectively page table and computing source data and operation result data;
Step 3: fill in page table and produce configuration file, describe the page table size, the page table information of actual situation address mapping relation, wherein the page table size is consistent with the page table size information in the described MMU configuration file;
Described page table produces in the configuration file, comprises the page table information of actual situation address mapping relation;
Step 4: after verification platform is started working, the page table generation unit reads in and produces the page table file that is used for depositing in the required form of described memory model after described page table produces configuration file, and then described memory model enters the initialization of page table file the page table storage address of appointment in the described MMU configuration file;
Step 5: special circuit behavior generation model reads in described special circuit configuration file automatically, and initiates the read-write transport behavior according to described special circuit configuration file, and wherein reference address is random address;
Described special circuit behavior generation model is responsible for the model according to special circuit configuration file initiation read-write transport behavior, is used for simulating the transport behavior of actual special circuit;
Step 6: described MMU configuration file is read in MMU design to be verified automatically, then accept the transport behavior that described special circuit behavior generation model is initiated, then the page table memory address in the described memory model reads page table information, carries out sending after the mapping of actual situation address the transport behavior of address after the mapping;
Step 7: in the whole transmission course, original transmitted behavior collecting unit and actual transmissions behavior collecting unit gather all special circuit behavior generation models all the time to MMU design to be verified, MMU to be verified is designed into the transport behavior between the memory model, and produces respectively original address file and the rear address file of actual mapping according to the address information in the transport behavior;
Step 8: repeating step 4-step 7, until all transport behaviors finish;
Step 9: after all transport behaviors finish, the C model code reads in the original address file and page table produces configuration file, the map information that produces in the configuration file according to page table transfers the virtual address of original address file to after the mapping real address, and produces address file after the expectation mapping;
Step 10: the file comparing unit is responsible for automatically reading that address file and expectation shine upon rear address file after the actual mapping, then two files is compared whether correct the result of rear Output rusults.
2. the verification method of the MMU in a kind of SOC chip as claimed in claim 1 is characterized in that: described special circuit is initiated the behavior of transmission, comprises different burst transfer length, different data bit widths.
3. the verification method of the MMU in a kind of SOC chip as claimed in claim 1, it is characterized in that: described file comparing unit can be reported the address that begins to occur mistake, the position that makes things convenient for the checking personnel to locate errors.
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| CN110399726A (en) * | 2019-06-25 | 2019-11-01 | 苏州浪潮智能科技有限公司 | TPM phy chip detection method, device, equipment and readable storage medium storing program for executing |
| CN110489169A (en) * | 2019-08-06 | 2019-11-22 | 晶晨半导体(上海)股份有限公司 | A kind of memory quick start method of system on chip |
| CN111159005A (en) * | 2018-11-07 | 2020-05-15 | 珠海全志科技股份有限公司 | Method and system for testing memory management function |
| CN111400623A (en) * | 2020-03-10 | 2020-07-10 | 百度在线网络技术（北京）有限公司 | Method and apparatus for searching information |
| CN113485882A (en) * | 2021-07-21 | 2021-10-08 | 鹏城实验室 | Chip verification method and device and computer readable storage medium |
| CN118095156A (en) * | 2024-04-29 | 2024-05-28 | 北京燧原智能科技有限公司 | Verification method, device, equipment and medium of memory management unit MMU circuit |
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| CN118095156A (en) * | 2024-04-29 | 2024-05-28 | 北京燧原智能科技有限公司 | Verification method, device, equipment and medium of memory management unit MMU circuit |
| CN118095156B (en) * | 2024-04-29 | 2024-07-05 | 北京燧原智能科技有限公司 | Verification method, device, equipment and medium of memory management unit MMU circuit |
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