CN115203067A - Memory initialization method and device, electronic equipment and computer readable storage medium - Google Patents
Memory initialization method and device, electronic equipment and computer readable storage medium Download PDFInfo
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- CN115203067A CN115203067A CN202210825119.7A CN202210825119A CN115203067A CN 115203067 A CN115203067 A CN 115203067A CN 202210825119 A CN202210825119 A CN 202210825119A CN 115203067 A CN115203067 A CN 115203067A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The application discloses a memory initialization method, a device, an electronic device and a computer readable storage medium, wherein the method comprises the following steps: acquiring first information preset in a power management chip of the memory based on a serial communication bus, and determining identity information of the memory based on the first information; acquiring a corresponding configuration file based on the identity information; the configuration file comprises configuration parameters for configuring the memory; based on the configuration file, an initialization operation is performed on the memory. Because the first information can be obtained from the power management chip based on the serial communication bus, the identity of the memory does not need to be identified by occupying pins of the memory, and the power management chip can provide diversified identity identification modes for the memory. Therefore, the difficulty of the identity recognition of the memory can be reduced, the flexibility of the identity recognition of the memory is improved, the initialization of the memory is facilitated, and the difficulty of the memory design can be reduced.
Description
Technical Field
The present disclosure relates to the field of electronic devices, and in particular, to a memory initialization method, a memory initialization apparatus, an electronic device, and a computer-readable storage medium.
Background
In the initialization stage of the electronic device, differentiated identification needs to be performed on hardware on the motherboard, such as identifying information of manufacturers, storage capacity, models and the like of the memory. And the Unified Extensible Firmware Interface (UEFI) or the basic input/output system (BIOS) performs different software settings for the memory based on the identified identity information so as to meet the differential design requirements of the software settings.
In the prior art, the memory is configured differentially, generally by setting a specific number of pins of the memory differentially, so that the pins can present a specific potential, such as a high potential or a low potential, in an initial state, and a code is formed by the potentials of the pins. When the electronic equipment is initialized, the mainboard identifies the codes of the memory by identifying the potentials of the pins so as to further determine identity information of manufacturers, storage capacity, models and the like of the memory. Such a configuration requires more pins, which increases the difficulty in manufacturing and designing the memory.
Disclosure of Invention
In view of the foregoing technical problems in the prior art, embodiments of the present application provide a memory initialization method, a memory initialization apparatus, an electronic device, and a computer-readable storage medium.
In order to solve the technical problem, the embodiment of the application adopts the following technical scheme:
a memory initialization method comprises the following steps:
acquiring first information preset in a power management chip of a memory based on a serial communication bus, and determining identity information of the memory based on the first information;
acquiring a corresponding configuration file based on the identity information; the configuration file comprises configuration parameters for configuring the memory;
and executing initialization operation on the memory based on the configuration file.
In some embodiments, the obtaining first information preset in a power management chip of a memory based on a serial communication bus and determining identity information of the memory based on the first information includes:
determining address information of the power management chip based on the serial communication bus, and/or acquiring identification information in a preset storage space of the power management chip;
and determining the type of the memory based on the address information and/or the identification information.
In some embodiments, the acquiring first information preset in a power management chip of a memory based on a serial communication bus and determining identity information of the memory based on the first information includes:
determining address information of the power management chip based on the serial communication bus;
acquiring identification information in a preset storage space of the power management chip based on the address information;
determining a first attribute and a second attribute of the memory based on the address information and the identification information respectively;
and determining the identity information of the memory based on the first attribute and the second attribute.
In some embodiments, the determining address information of the power management chip based on the serial communication bus comprises:
sending an access request to the power management chip based on the serial communication bus and a plurality of preset address information;
and under the condition of acquiring the feedback information of the power management chip, determining the address information contained in the access request as the address information of the power management chip.
In some embodiments, the determining the first attribute and the second attribute of the memory based on the address information and the identification information, respectively, includes:
determining the storage capacity of the memory based on the address information;
and determining the manufacturer of the memory based on the identification information.
A memory initialization apparatus comprising:
the device comprises a determining module, a judging module and a judging module, wherein the determining module is used for acquiring first information preset in a power management chip of the memory based on a serial communication bus and determining identity information of the memory based on the first information;
the acquisition module is used for acquiring a corresponding configuration file based on the identity information; the configuration file comprises configuration parameters for configuring the memory;
and the initialization module is used for executing initialization operation on the memory based on the configuration file.
In some embodiments, the determining module is specifically configured to:
determining address information of the power management chip based on the serial communication bus, and/or acquiring identification information in a preset storage space of the power management chip;
and determining the type of the memory based on the address information and/or the identification information.
In some embodiments, the determining module is specifically configured to:
determining address information of the power management chip based on the serial communication bus;
acquiring identification information in a preset storage space of the power management chip based on the address information;
determining a first attribute and a second attribute of the memory based on the address information and the identification information respectively;
and determining the identity information of the memory based on the first attribute and the second attribute.
An electronic device comprising at least a memory having a program stored thereon and a processor implementing the method as described above when executing the program on the memory.
A computer-readable storage medium having stored therein computer-executable instructions that, when executed, implement a method as described above.
The memory initialization method of the embodiment of the application obtains first information preset in a power management chip of a memory based on a serial communication bus, determines identity information of the memory based on the first information, obtains a corresponding configuration file based on the identity information, and performs initialization operation on the memory based on the configuration file. Because the first information can be acquired from the power management chip based on the serial communication bus, the identity of the memory does not need to be identified by occupying pins of the memory, and the power management chip can provide diversified identity identification modes for the memory. Therefore, the difficulty of the identity recognition of the memory can be reduced, the flexibility of the identity recognition of the memory is improved, the initialization of the memory is facilitated, and the difficulty of the memory design can be reduced.
Drawings
Fig. 1 is a flowchart of a memory initialization method according to a first embodiment of the present application;
fig. 2 to fig. 4 are schematic diagrams of the PID pin of the power management chip in different connection states, respectively;
fig. 5 is a flowchart of a memory initialization method according to a second embodiment of the present application;
fig. 6 is a flowchart of step S201;
fig. 7 is a block diagram illustrating a memory initialization apparatus according to a third embodiment of the present application;
fig. 8 is a block diagram of an electronic device according to a fourth embodiment of the present application.
Detailed Description
Various aspects and features of the present application are described herein with reference to the drawings.
It will be understood that various modifications may be made to the embodiments of the present application. Accordingly, the foregoing description should not be construed as limiting, but merely as exemplifications of embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the application.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the application and, together with a general description of the application given above and the detailed description of the embodiments given below, serve to explain the principles of the application.
These and other characteristics of the present application will become apparent from the following description of preferred forms of embodiment, given as non-limiting examples, with reference to the attached drawings.
It should also be understood that, although the present application has been described with reference to some specific examples, a person of skill in the art shall certainly be able to achieve many other equivalent forms of application, having the characteristics as set forth in the claims and hence all coming within the field of protection defined thereby.
The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.
Specific embodiments of the present application are described hereinafter with reference to the drawings; however, it is to be understood that the disclosed embodiments are merely exemplary of the application, which can be embodied in various forms. Well-known and/or repeated functions and constructions are not described in detail to avoid obscuring the application of unnecessary or unnecessary detail. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present application in virtually any appropriately detailed structure.
The description may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments in accordance with the application.
A first embodiment of the present application provides a memory initialization method, which is applied to an electronic device with a memory, and is used for executing an initialization operation on the electronic device at a start stage of the electronic device. The electronic device may be, for example, a desktop computer, a notebook computer, a tablet computer, a smart phone, a smart car, and the like, and the specific type of the electronic device is not limited herein.
Fig. 1 is a flowchart of a memory initialization method according to a first embodiment of the present application, and referring to fig. 1, the memory initialization method according to the first embodiment of the present application may specifically include the following steps.
S101, first information preset in a power management chip of a memory is obtained based on a serial communication bus, and identity information of the memory is determined based on the first information.
Optionally, the power management chip may be connected to a processor (CPU) of the electronic device through a serial communication bus, or may be connected to a south bridge chip (PCH) of the electronic device through a serial communication bus. Taking the example that the PCH is connected with the power management chip through the serial communication bus as an example, in the starting process of the electronic device, the PCH can acquire preset first information from the power management chip based on the serial communication bus and give the first information to determine identity information of the memory. For example, a mapping table between the first information and the identity information of the memory may be preconfigured, and the PCH acquires the first information and may invoke the mapping table to determine the identity information of the memory.
Optionally, the serial communication bus may conform to an I2C protocol or an I3C protocol. A power management chip (PMIC) is a chip responsible for transforming, distributing, sensing and other duties of power management. According to the requirements of the solid state technology association (JEDEC), to satisfy the flexibility of power supply design of the 5 th generation double data rate synchronous dynamic random access memory (DDR 5), the DDR5 must integrate PMIC, that is, PMIC must be provided on the DDR 5. PMICs typically communicate based on either an I2C protocol or an I3C protocol.
More information is reserved in the power management chip for a manufacturer to customize and set. For example, the address information of the power management chip and the information in some specific registers in the power management chip can be customized by the manufacturer to some extent.
Taking the PMIC conforming to the I2C protocol as an example, the PMIC usually includes an 8-bit address information, which includes a four-bit PID address field, a three-bit HID address field, and a bit flag for indicating the read/write status. By adjusting the connection state of the PID pin of the PMIC, the assignment of the PID address field can be adjusted. When the PID pin is connected to the VOUT _1.8V pin through the first resistor R1, the PID address segment is assigned to 1100, as shown in FIG. 2. When the PID pin is grounded through the second resistor, the PID address segment is assigned 1001, as shown in FIG. 3. When the PID pin is in a floating state, i.e., neither connected to VOUT _1.8V pin nor grounded, the PID address field is assigned a value of 1000, as shown in fig. 4. The HID address field defaults to 111, but can be set by software. The address information of the PMIC is specifically shown in the following table.
TABLE 1
As can be seen from the above table, at least three address combinations can be formed by merely adjusting the PID pins, and if necessary, the HID address field can be set by software, so that various combinations can be formed. Therefore, the manufacturer can use the address information of the PMIC as the first information. In the initialization process of the electronic equipment, the address information of the PMIC can be determined based on the serial communication bus, and the identity information of the memory can be determined based on the address information. For example, the manufacturer, storage capacity, model, etc. of the memory are determined.
The power management chip eliminates address information to allow the manufacturer to make customized settings, and some registers allow the manufacturer to make customized settings. For example, the 0x40 register to the 0x6F register all allow the manufacturer to set itself. Therefore, the manufacturer may also write some identification information into these registers before shipping to identify the memory. Of course, the part of the identification information is not limited to the identity used for identifying the memory. For example, when the information in the registers 0x40 to 0x42 is used to identify the power-on sequence, the information can be used to identify the memory by customizing the power-on sequence.
It should be noted that, in the specific implementation, the identity information of the memory may be determined by using the address information, or the identity information of the memory may be determined by using the identification information in the specific storage space, or the identity information of the memory may be determined by using a combination of the address information and the identification information.
For example, a first attribute of the memory may be identified by the address information, a second attribute of the memory may be identified by the identification information, the first attribute of the memory may be determined based on the address information, the second attribute of the memory may be determined based on the identification information, and then the identity information of the memory may be determined based on both the first attribute and the second attribute. The first attribute and the second attribute may include multiple types of attribute information of the memory. Optionally, the first attribute may include storage capacity, manufacturer, algebra, model, etc., and the second attribute may also include storage capacity, manufacturer, algebra, model, etc. For example, in the case where the storage capacity of the memory is identified by the first attribute, the manufacturer of the memory may be identified by the second attribute.
S102, acquiring a corresponding configuration file based on the identity information. The configuration file comprises configuration parameters for configuring the memory.
Alternatively, in the event that the identity information of the memory is determined by the processor or south bridge information, the identity information may be sent to the boot program. Such as a basic input output system (BIOD) or a Unified Extensible Firmware Interface (UEFI). And acquiring a corresponding configuration file based on the identity information by using the bootstrap program. The configuration file includes a plurality of configuration parameters for configuring the memory, for example, configuration parameters related to initialization of the memory, such as operating voltage, clock cycle, and vertical address burst (CAS) delay time.
Alternatively, configuration files of various memories may be written in a read-only storage space such as firmware in advance. Under the condition that the bootstrap program acquires the identity information of the memory, the bootstrap program can call the corresponding configuration file from the read-only storage space based on the identity information of the memory.
S103, based on the configuration file, initializing the memory.
The bootstrap program, upon acquiring the configuration file, may perform an initialization operation on the memory based on the configuration file. That is, the memory is initially set based on various configuration parameters in the configuration file. For example, the operating voltage, clock cycle, CAS latency, etc. of the memory are set, so that the memory can be booted up and operate normally.
The memory initialization method of the embodiment of the application obtains first information preset in a power management chip of a memory based on a serial communication bus, determines identity information of the memory based on the first information, obtains a corresponding configuration file based on the identity information, and performs initialization operation on the memory based on the configuration file. Because the first information can be obtained from the power management chip based on the serial communication bus, the identity of the memory does not need to be identified by occupying pins of the memory, and the power management chip can provide diversified identity identification modes for the memory. Therefore, the difficulty of the identity recognition of the memory can be reduced, the flexibility of the identity recognition of the memory is improved, the initialization of the memory is facilitated, and the difficulty of the memory design can be reduced.
A second embodiment of the present application provides a memory initialization method, which is described in detail with reference to specific embodiments. Fig. 5 is a flowchart of a memory initialization method according to a second embodiment of the present application, and referring to fig. 5, the memory initialization method according to the second embodiment of the present application may specifically include the following steps.
S201, determining address information of the power management chip based on the serial communication bus.
Optionally, the identity of the memory may be identified based on the address information of the power management chip and the identification information in the specific register. For example, the storage capacity of the memory can be identified by the PID address field in the address information, and the manufacturer of the memory can be identified by the identification information in the specific register.
Optionally, in step S201, determining address information of the power management chip based on the serial communication bus may include the following steps.
And S2011, based on the serial communication bus and a plurality of preset address information, sending an access request to the power management chip.
S2012, determining, when the feedback information of the power management chip is obtained, that the address information included in the access request is the address information of the power management chip.
For example, as shown in fig. 6, the south bridge chip may send an access request to the power management chip based on the address information of 0x8F, determine that the address information of the power management chip is 0x8F (hexadecimal) if the feedback information (ACK) of the power management chip is acquired, and determine that 0x8F is not the address information of the power management chip if the feedback information (NACK) of the power management chip is not acquired.
Further, an access request may be sent to the power management chip based on the address information of 0x9F, if feedback information (ACK) of the power management chip is acquired, it is determined that the address information of the power management chip is 0x9F, and if feedback information (NACK) of the power management chip is not acquired, it is determined that 0x9F is not the address information of the power management chip.
Further, an access request may be sent to the power management chip based on 0xCF, and if feedback information (ACK) of the power management chip is obtained, it is determined that the address information of the power management chip is 0x9F.
S202, acquiring identification information in a preset storage space of the power management chip based on the address information.
Alternatively, the identification information may be written in a specific register of the power management chip. For example, two bits of binary identification information may be written in the R43 register. For example, when the address information of the power management chip is determined to be 0x8F, the identification information in the R43 register in the power management chip may be read based on the address information of 0x 8F. When the address information of the power management chip is determined to be 0x9F, the identification information in the R43 register in the power management chip may be read based on this address information of 0x9F. When the address information of the power management chip is determined to be 0xCF, the identification information in the R43 register in the power management chip may be read based on the address information of 0xCF. Alternatively, the identification information may include, for example, 00, 01, 10, and so on.
S203, determining a first attribute and a second attribute of the memory based on the address information and the identification information respectively.
In step S203, the determining the first attribute and the second attribute of the memory based on the address information and the identification information respectively may include the following steps.
S2031, based on the address information, determining the storage capacity of the memory.
S2032, based on the identification information, determining the manufacturer of the memory.
Alternatively, a 1000 (binary) PID address field may be used to identify a 16GB storage capacity, a 1001 PID address field may be used to identify a 32GB storage capacity, and a 1100 PID address field may be used to identify a 64GB storage capacity. The HID address field is a default value 111, the PMIC address information is 0x8F (hexadecimal) when the PID address field is 1000, the PMIC address information is 0x9F when the PID address field is 1001, and the PMIC address information is 0xCF when the PID address field is 1100. Therefore, when the address information of the PMIC is determined to be 0x8F, the memory capacity of the memory may be determined to be 16GB, when the address information of the PMIC is determined to be 0x9F, the memory capacity of the memory may be determined to be 32GB, and when the address information of the PMIC is determined to be 0xCF, the memory capacity of the memory may be determined to be 64GB.
Alternatively, beauty lights (Micron) can be identified by "00", samsung (Samsung) by "01", and heishi (Hynix) by "10". And if the identification information acquired from the R43 register is '00', determining that the manufacturer of the memory is Meiguang, if the identification information is '01', determining that the manufacturer of the memory is Samsung, and if the identification information is '10', determining that the manufacturer of the memory is Hailishi.
S204, determining the identity information of the memory based on the first attribute and the second attribute.
Optionally, in the case that the storage capacity of the memory and the manufacturer are determined, the identity information of the memory may be determined based on the storage capacity and the manufacturer. For example, the identity information of the memory may be a 16GB memory, a 32GB memory, a 64GB memory, a 8230, a 32GB memory, a 64GB memory, and the like. In particular, the identity information of the memory can be provided by, for example, a number or other information.
S205, acquiring a corresponding configuration file based on the identity information. The configuration file comprises configuration parameters for configuring the memory.
Alternatively, in the event that the identity information of the memory is determined by the processor or south bridge information, the identity information may be sent to the boot program. Such as a basic input output system (BIOD) or a Unified Extensible Firmware Interface (UEFI). And acquiring a corresponding configuration file based on the identity information by using the bootstrap program. The configuration file includes various configuration parameters for configuring the memory, such as operating voltage, clock cycle, vertical address pulse (CAS) delay time, and other configuration parameters related to initialization of the memory. For example, in the case where the memory is determined to be a 64GB memory, a configuration file matching the memory may be called.
S206, based on the configuration file, initializing the memory.
The bootstrap program, upon acquiring the configuration file, may perform an initialization operation on the memory based on the configuration file. That is, the memory is initially set based on various configuration parameters in the configuration file. For example, the operating voltage, clock cycle, CAS latency, etc. of the memory are set, so that the memory can be booted up and operate normally.
The memory initialization method of the embodiment of the application determines address information of a power management chip based on a serial communication bus, acquires identification information in a preset storage space of the power management chip based on the address information, determines a first attribute and a second attribute of a memory based on the address information and the identification information respectively, determines identity information of the memory based on the first attribute and the second attribute, and executes initialization operation on the memory based on a configuration file. The address information and the identification information are acquired from the power management chip based on the serial communication bus, and the identity of the memory is identified without occupying pins of the memory. Therefore, the difficulty of the identity recognition of the memory can be reduced, the flexibility of the identity recognition of the memory is improved, the initialization of the memory is facilitated, and the difficulty of the memory design can be reduced.
Referring to fig. 7, a third embodiment of the present application provides a memory initialization apparatus, including:
the determining module 301 is configured to obtain first information preset in a power management chip of a memory based on a serial communication bus, and determine identity information of the memory based on the first information;
an obtaining module 302, configured to obtain a corresponding configuration file based on the identity information; the configuration file comprises configuration parameters for configuring the memory;
an initialization module 303, configured to perform an initialization operation on the memory based on the configuration file.
In some embodiments, the determining module 301 is specifically configured to:
determining address information of the power management chip based on the serial communication bus, and/or acquiring identification information in a preset storage space of the power management chip;
and determining the type of the memory based on the address information and/or the identification information.
In some embodiments, the determining module 301 is specifically configured to:
determining address information of the power management chip based on the serial communication bus;
acquiring identification information in a preset storage space of the power management chip based on the address information;
determining a first attribute and a second attribute of the memory based on the address information and the identification information respectively;
and determining the identity information of the memory based on the first attribute and the second attribute.
In some embodiments, the determining module 301 is specifically configured to:
based on the serial communication bus and a plurality of preset address information, sending an access request to the power management chip;
and under the condition of acquiring the feedback information of the power management chip, determining the address information contained in the access request as the address information of the power management chip.
In some embodiments, the determining module 301 is specifically configured to:
determining the storage capacity of the memory based on the address information;
and determining the manufacturer of the memory based on the identification information.
Referring to fig. 8, the fourth embodiment of the present application further provides an electronic device, which at least includes a memory 401 and a processor 402, where the memory 401 stores a program, and the processor 402 implements the method according to any one of the above embodiments when executing the program on the memory 401.
A fifth embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions in the computer-readable storage medium are executed, the method according to any one of the above embodiments is implemented.
It will be apparent to one skilled in the art that embodiments of the present application may be provided as methods, electronic devices, computer-readable storage media, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied in the medium. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
The processor may be a general purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof. The general purpose processor may be a microprocessor or any conventional processor or the like.
The memory may include volatile memory in a computer readable medium, random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.
The readable storage medium may be a magnetic disk, an optical disk, a DVD, a USB, a Read Only Memory (ROM), a Random Access Memory (RAM), etc., and the application does not limit the specific storage medium form.
The above embodiments are only exemplary embodiments of the present application, and are not intended to limit the present application, and the protection scope of the present application is defined by the claims. Various modifications and equivalents may be made to the disclosure by those skilled in the art within the spirit and scope of the disclosure, and such modifications and equivalents should also be considered as falling within the scope of the disclosure.
The above embodiments are only exemplary embodiments of the present application, and are not intended to limit the present application, and the protection scope of the present application is defined by the claims. Various modifications and equivalents may be made to the disclosure by those skilled in the art within the spirit and scope of the disclosure, and such modifications and equivalents should also be considered as falling within the scope of the disclosure.
Claims (10)
1. A method for initializing a memory, comprising:
acquiring first information preset in a power management chip of a memory based on a serial communication bus, and determining identity information of the memory based on the first information;
acquiring a corresponding configuration file based on the identity information; the configuration file comprises configuration parameters for configuring the memory;
and executing initialization operation on the memory based on the configuration file.
2. The method according to claim 1, wherein the obtaining first information preset in a power management chip of a memory based on a serial communication bus and determining identity information of the memory based on the first information comprises:
determining address information of the power management chip based on the serial communication bus, and/or acquiring identification information in a preset storage space of the power management chip;
and determining the type of the memory based on the address information and/or the identification information.
3. The method according to claim 1, wherein the obtaining first information preset in a power management chip of a memory based on a serial communication bus and determining identity information of the memory based on the first information comprises:
determining address information of the power management chip based on the serial communication bus;
acquiring identification information in a preset storage space of the power management chip based on the address information;
determining a first attribute and a second attribute of the memory based on the address information and the identification information respectively;
and determining the identity information of the memory based on the first attribute and the second attribute.
4. The method of claim 3, wherein determining the address information of the power management chip based on the serial communication bus comprises:
based on the serial communication bus and a plurality of preset address information, sending an access request to the power management chip;
and under the condition of acquiring the feedback information of the power management chip, determining the address information contained in the access request as the address information of the power management chip.
5. The method of claim 3, wherein determining the first attribute and the second attribute of the memory based on the address information and the identification information, respectively, comprises:
determining the storage capacity of the memory based on the address information;
and determining the manufacturer of the memory based on the identification information.
6. A memory initialization apparatus, comprising:
the device comprises a determining module, a judging module and a judging module, wherein the determining module is used for acquiring first information preset in a power management chip of the memory based on a serial communication bus and determining identity information of the memory based on the first information;
the acquisition module is used for acquiring a corresponding configuration file based on the identity information; the configuration file comprises configuration parameters for configuring the memory;
and the initialization module is used for executing initialization operation on the memory based on the configuration file.
7. The apparatus of claim 6, wherein the determining module is specifically configured to:
determining address information of the power management chip based on the serial communication bus, and/or acquiring identification information in a preset storage space of the power management chip;
and determining the type of the memory based on the address information and/or the identification information.
8. The apparatus of claim 6, wherein the determining module is specifically configured to:
determining address information of the power management chip based on the serial communication bus;
acquiring identification information in a preset storage space of the power management chip based on the address information;
determining a first attribute and a second attribute of the memory based on the address information and the identification information respectively;
and determining the identity information of the memory based on the first attribute and the second attribute.
9. An electronic device comprising at least a memory and a processor, the memory having a program stored thereon, wherein the processor, when executing the program on the memory, implements the method of any of claims 1-5.
10. A computer-readable storage medium having computer-executable instructions stored therein, wherein the method of any one of claims 1-5 is implemented when the computer-executable instructions in the computer-readable storage medium are executed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210825119.7A CN115203067A (en) | 2022-07-13 | 2022-07-13 | Memory initialization method and device, electronic equipment and computer readable storage medium |
Applications Claiming Priority (1)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117056897A (en) * | 2023-10-13 | 2023-11-14 | 沐曦集成电路(上海)有限公司 | Configuration information processing method for chip verification, electronic device and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117056897A (en) * | 2023-10-13 | 2023-11-14 | 沐曦集成电路(上海)有限公司 | Configuration information processing method for chip verification, electronic device and medium |
| CN117056897B (en) * | 2023-10-13 | 2023-12-26 | 沐曦集成电路(上海)有限公司 | Configuration information processing method for chip verification, electronic device and medium |
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