CN114690682A - Serial peripheral interface SPI system and data transmission method thereof - Google Patents
Serial peripheral interface SPI system and data transmission method thereof Download PDFInfo
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- CN114690682A CN114690682A CN202111598785.3A CN202111598785A CN114690682A CN 114690682 A CN114690682 A CN 114690682A CN 202111598785 A CN202111598785 A CN 202111598785A CN 114690682 A CN114690682 A CN 114690682A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
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Abstract
The application discloses a Serial Peripheral Interface (SPI) system and a data transmission method thereof, wherein the SPI system comprises a plurality of slave devices and a master device. The main device comprises a chip selection control circuit and a chip selection mode selection circuit. The chip selection control circuit generates a first selection signal and a second selection signal. The chip selection mode selection circuit is coupled with the chip selection control circuit and the dynamic chip selection pin circuit, and determines whether to select the dynamic chip selection pin circuit according to the first selection signal to select the chip selection pin. When the dynamic chip selection pin circuit is selected, the chip selection control circuit transmits a second selection signal to the dynamic chip selection pin circuit to select the chip selection pin from the plurality of chip selection pins and transmits data to one of the plurality of slave devices corresponding to the selected chip selection pin. The serial peripheral interface system and the data transmission method provided by the invention can avoid the waste of pins.
Description
Technical Field
Embodiments of the present invention generally relate to a Serial Peripheral Interface (SPI) technology, and more particularly, to a SPI technology for dynamically selecting chip select pins.
Background
Serial Peripheral Interface Bus (SPI) is a synchronous Serial communication Interface specification for chip communication. The serial peripheral interface is widely used in the field of single Chip (SOC) and Microcontroller (MCU).
In the current technology of serial peripheral interface, when the master device is connected to the slave device, a set of serial peripheral interface master ports of the master device is configured with a chip select pin to connect to a slave device (slave device). However, when the master device is connected to a plurality of slave devices, the master device must be configured with a plurality of sets of serial peripheral interface master ports, which results in a waste of pins.
Disclosure of Invention
In view of the foregoing background, embodiments of the present invention provide a Serial Peripheral Interface (SPI) system and a data transmission method.
According to an embodiment of the present invention, a serial peripheral interface system is provided. The serial peripheral interface system comprises a plurality of slave devices and a master device. The main device comprises a chip selection control circuit and a chip selection mode selection circuit. The chip selection control circuit is used for generating a first selection signal and a second selection signal. The chip selection mode selection circuit is coupled with the chip selection control circuit and a dynamic chip selection pin circuit, and determines whether to select the dynamic chip selection pin circuit according to the first selection signal so as to select a chip selection pin. When the dynamic chip selection pin circuit is selected, the chip selection control circuit transmits the second selection signal to the dynamic chip selection pin circuit to select the chip selection pin from a plurality of chip selection pins and transmits data to one of the plurality of slave devices corresponding to the selected chip selection pin.
In some embodiments, the chip selection mode selection circuit is further coupled to a static chip selection pin circuit, and the chip selection mode selection circuit determines to select the static chip selection pin circuit or the dynamic chip selection pin circuit according to the first selection signal to select the chip selection pin.
In some embodiments, the static chip select pin circuit, the dynamic chip select pin circuit, and the plurality of chip select pins are included in a universal input/output interface.
In some embodiments, the host device further includes a control interface, and the chip selection control circuit generates the first selection signal according to a control signal output from the control interface.
In some embodiments, the host device further includes a memory interface, and the chip selection control circuit generates the second selection signal according to a determination result generated from the memory interface.
In some embodiments, the master device further includes a logic circuit to output data to be transmitted to the slave device corresponding to the selected chip select pin.
According to an embodiment of the present invention, a data transmission method is provided. The data transmission method is suitable for a Serial Peripheral Interface (SPI) system. The data transmission method comprises the following steps: generating a first selection signal by a chip selection control circuit of a main device of the serial peripheral interface system; selecting a chip selection pin by a chip selection mode selection circuit of the main device and determining whether to select a dynamic chip selection pin circuit of the serial peripheral interface system according to the first selection signal; when the dynamic chip selection pin circuit is selected, the chip selection control circuit transmits a second selection signal to the dynamic chip selection pin circuit so as to select the chip selection pins from a plurality of chip selection pins of the serial peripheral interface system; and transmitting data to one of the plurality of slave devices of the serial peripheral interface system corresponding to the selected chip select pin.
According to the serial peripheral interface system and the data transmission method provided by the invention, the static chip selection pin corresponding to the slave device needing to be communicated can be selected by a dynamic chip selection pin circuit. Therefore, in the serial peripheral interface system provided by the invention, the main device can achieve the purpose of switching different static chip selection pins only by configuring one group of main ports. Therefore, the serial peripheral interface system and the data transmission method provided by the invention can avoid the waste of pins.
Other additional features and advantages of the present invention will be apparent to those skilled in the art, and it is intended that the present invention may be implemented in other embodiments and methods without departing from the spirit and scope of the present invention.
Drawings
FIG. 1 is a block diagram illustrating a serial peripheral interface system 100 according to an embodiment of the present invention.
Fig. 2 is a flowchart of a data transmission method according to an embodiment of the invention.
Reference numerals
100: serial peripheral interface system
110: advanced microcontroller bus architecture
120: master device
121: memory interface
122: control interface
123: logic circuit
124: chip selection control circuit
125: chip selection mode selection circuit
130: universal input/output interface
131: static chip pin selecting circuit
132: dynamic chip pin selecting circuit
140: first slave device
150: second slave device
And (3) MISO: master device input slave device output pin
MISO 1: input port of master device and output port of slave device
MOSI: master device output slave device input pin
MOSI 1: input port of master/slave device
CLK: clock pulse pin
CLK 1: clock output port
CS 0: first chip selection pin
CS 1: second chip selection pin
nCS: chip selection port
S1: the judgment result
S2: control signal
S3: a first selection signal
S4: second selection signal
S210 to S250: step (ii) of
Detailed Description
The preferred embodiments of the present invention are described in this section for the purpose of illustrating the spirit of the invention and not for the purpose of limiting the scope of the invention, which is defined in the claims appended hereto.
Fig. 1 is a block diagram of a Serial Peripheral Interface (SPI) system 100 according to an embodiment of the present invention. As shown in fig. 1, the serial peripheral interface system 100 may include an Advanced Microcontroller Bus Architecture (AMBA) (e.g., an Advanced High-Performance Bus (AHB)) 110, a master device (master device)120, a General-purpose input/output (GPIO) interface 130, a first slave device (slave device)140, and a second slave device 150. Note that the block diagram shown in fig. 1 is only for convenience of describing the embodiment of the present invention, but the present invention is not limited to fig. 1. Other components may also be included in the SPI system 100.
According to an embodiment of the present invention, as shown in fig. 1, the master device 120 may at least include a memory interface (memory interface)121, a control interface (control interface)122, a logic circuit 123, a Chip Select (CS) control circuit 124, and a Chip Select (CS) mode select circuit 125. Note that the master device 120 shown in fig. 1 is only for convenience of describing the embodiment of the present invention, but the present invention is not limited to fig. 1. Other components may also be included in the master device 120.
In addition, according to an embodiment of the invention, as shown in fig. 1, the general-purpose Input/Output 130 may include a Master Input/Slave Output pin MISO (Master Input/Slave Output), a Master Output/Slave Input pin MOSI (Master Output/Slave Input), a clock pin CLK, a first chip select pin CS0, a second chip select pin CS1, a static chip select pin circuit 131, and a dynamic chip select pin circuit 132. In addition, according to an embodiment of the present invention, as shown in FIG. 1, the first chip select pin CS0 is connected to the first slave device 140, and the second chip select pin CS1 is connected to the second slave device 150.
According to the embodiment of the present invention, the memory interface 121 determines to which slave the memory address accessed by the advanced microcontroller bus architecture 110 corresponds to, so as to generate a determination result S1. For example, if the memory address range corresponding to the first slave device 140 is 0x1000 to 0x1ffff and the memory address range corresponding to the second slave device 150 is 0x2000 to 0x2ffff, when the memory interface 121 determines that the memory address accessed by the advanced microcontroller bus structure 110 is within the memory address range 0x1000 to 0x1ffff, the memory interface 121 will determine that the memory address accessed by the advanced microcontroller bus structure 110 corresponds to the first slave device 140. It should be noted that the above examples are only for illustrating the embodiments of the present invention, but the present invention is not limited thereto. The memory interface 121 will transmit the determination result S1 to the logic circuit 123 and the chip selection control circuit 124.
According to the embodiment of the present invention, the control interface 122 generates a control signal S2 according to the command from the high-level microcontroller bus architecture 110, and transmits the control signal S2 to the logic circuit 123 and the chip selection control circuit 124. The logic circuit 123 and the chip selection control circuit 124 can select the chip selection pin according to the control signal S2, which indicates whether the static chip selection pin function or the dynamic chip selection pin function (i.e., the static chip selection pin circuit 131 or the dynamic chip selection pin circuit 132) is to be used.
According to embodiments of the present invention, the logic circuit 123 may be considered a set of serial peripheral interface host ports (master ports). According to embodiments of the present invention, the logic circuit 123 may include a master input slave output port MISO1, a master output slave input port MOSI1, a clock output port CLK1 and a chip select port nCS. The logic circuit 123 can transmit data or signals to the selected slave device via the master input slave output port MISO1, the master output slave input port MOSI1, the clock output port CLK1 and the chip select port nCS. As shown in FIG. 1, the master input slave output port MISO1 is connected to the master input slave output pin MISO of the general purpose input output 130 to transmit the signal MISO _ OUT to the master input slave output pin MISO. The master output slave input port MOSI1 is connected to the master output slave input pin MOSI of the general purpose input/output 130 for transmitting a signal MOSI _ OUT to the master output slave input pin MOSI. The clock output port CLK1 is connected to the clock pin CLK of the universal input/output 130 for transmitting the clock signal CLK _ OUT to the clock pin CLK. The chip select port nCS is connected to the chip select mode select circuit 125 for transmitting the signal nCS _ OUT to the chip select mode select circuit 125.
According to the embodiment of the invention, the chip selection control circuit 124 selects the chip selection pin according to whether the static chip selection pin function or the dynamic chip selection pin function (i.e. whether the static chip selection pin circuit 131 or the dynamic chip selection pin circuit 132 is selected) is known according to the received control signal S2, and generates a first selection signal S3 accordingly. Then, the chip selection control circuit 124 transmits the first selection signal S3 to the chip selection mode selection circuit 125. The chip selection mode selection circuit 125 may determine to use the static chip selection pin circuit 131 or the dynamic chip selection pin circuit 132 to select the chip selection pin and the transmission signal nCS _ OUT according to the first selection signal S3.
When the static chip select pin circuit 131 is selected, the static chip select pin circuit 131 determines to activate the first chip select pin CS0 or the second chip select pin CS1 according to a value of a register (not shown) of the general purpose input/output 130.
When the dynamic chip select pin circuit 132 is selected, the dynamic chip select pin circuit 132 may determine to activate the first chip select pin CS0 or the second chip select pin CS1 according to the second select signal S4 from the chip select control circuit 124. As will be described in more detail below.
According to an embodiment of the present invention, when the chip select control circuit 124 determines that the chip select pin is to be selected using the dynamic chip select pin function (i.e., the dynamic chip select pin circuit 132 is selected) according to the control signal S2, the chip select control circuit 124 determines which slave device is to be accessed according to the determination result S1 to determine whether the first chip select pin CS0 or the second chip select pin CS1 is to be activated, and accordingly generates a second select signal S4. Then, the chip select control circuit 124 transmits the second select signal S4 to the dynamic chip select pin circuit 132. The dynamic chip select pin circuit 132 may determine to activate the first chip select pin CS0 or the second chip select pin CS1 according to the second select signal S4, so as to transmit the data included in the signal nCS _ OUT to the first chip select pin CS0 or the second chip select pin CS 1. That is, the dynamic chip select pin circuit 132 can dynamically select the first chip select pin CS0 or the second chip select pin CS1 according to the second select signal S4.
The master device 120 may communicate with the first slave device 140 when the first chip select pin CS0 is selected, and the master device 120 may communicate with the second slave device 150 when the second chip select pin CS1 is selected.
Fig. 2 is a flow chart of a data transmission method according to an embodiment of the invention. The data transmission method is applicable to a Serial Peripheral Interface (SPI) system 100. As shown in fig. 2, in step S210, a first selection signal is generated by a chip selection control circuit of the master device of the serial peripheral interface system 100.
In step S220, a chip selection pin is selected by determining whether to select a dynamic chip selection pin circuit or a static chip selection pin circuit of the serial peripheral interface system according to the first selection signal by using a chip selection mode selection circuit of the main device of the serial peripheral interface system 100.
When the dynamic chip selection pin circuit is selected, step S230 is performed. In step S230, a second selection signal is transmitted to the dynamic chip selection pin circuit by the chip selection control circuit, so as to select the chip selection pins from the plurality of chip selection pins of the serial peripheral interface system 100 according to the second selection signal. In step S250, the slave device is given data to be output to the slave device corresponding to the selected chip select pin by a logic circuit of the serial peripheral interface system 100. In this embodiment, the static chip select pin circuit, the dynamic chip select pin circuit, and the plurality of chip select pins may be included in a general purpose input/output interface of the serial peripheral interface system 100.
When the static chip select pin circuit is selected, step S240 is performed. In step S240, a chip select pin is selected from the plurality of chip select pins of the serial peripheral interface system 100 through the general purpose input/output interface of the serial peripheral interface system 100. Subsequently, step S250 is performed.
According to an embodiment of the present invention, the data transmission method further includes generating the first selection signal by the chip selection control circuit of the serial peripheral interface system 100 according to a control signal output from a control interface of the serial peripheral interface system 100.
According to an embodiment of the present invention, the data transmission method further includes generating the second selection signal according to a determination result from a memory interface of the serial peripheral interface system 100 by the chip selection control circuit of the serial peripheral interface system 100. The memory interface may generate a determination result S1 by determining to which slave device the memory address accessed by an advanced micro-controller bus architecture of the SPI system 100 corresponds.
According to the serial peripheral interface system and the data transmission method provided by the invention, the static chip selection pin corresponding to the slave device needing to be communicated can be selected by a dynamic chip selection pin circuit. Therefore, in the serial peripheral interface system provided by the invention, the main device can achieve the purpose of switching different static chip selection pins only by configuring one group of main ports. Therefore, the serial peripheral interface system and the data transmission method provided by the invention can avoid the waste of pins.
The ordinal numbers such as "first", "second", etc. in this specification and in the claims are for convenience only and do not have any ordinal relation with one another.
The steps of the methods and algorithms disclosed in the present specification may be implemented directly in hardware or software modules or a combination thereof by executing a processor. A software module (including executable instructions and related data) and other data may be stored in a data storage device, such as Random Access Memory (RAM), flash memory (ROM), Read Only Memory (ROM), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), registers, a hard disk, a portable hard disk, a compact disc read only memory (CD-ROM), a DVD, or any other computer-readable storage medium format known in the art. A storage medium may be coupled to a machine, such as, for example, a computer or a processor (which may be referred to herein as a processor for convenience of description), which may be used to read information (such as program code) from and write information to the storage medium. A storage medium may incorporate a processor. An Application Specific Integrated Circuit (ASIC) includes a processor and a storage medium. A user equipment includes an ASIC. In other words, the processor and the storage medium are included in the user equipment without being directly connected to the user equipment. In addition, in some embodiments, any suitable computer program product includes a readable storage medium including program code associated with one or more of the disclosed embodiments. In some embodiments, the product of the computer program may comprise packaging material.
The above paragraphs use various levels of description. It should be apparent that the teachings herein may be implemented in a wide variety of ways and that any specific architecture or functionality disclosed in the examples is merely representative. It will be appreciated by those of ordinary skill in the art, in light of the teachings herein, that each of the layers disclosed herein can be practiced independently or that two or more of the layers can be combined in a practical application.
Although the present disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure.
Claims (10)
1. A Serial Peripheral Interface (SPI) system, comprising:
a plurality of slave devices; and
a master device, comprising:
a chip selection control circuit for generating a first selection signal and a second selection signal; and
a chip selection mode selection circuit coupled to the chip selection control circuit and a dynamic chip selection pin circuit, and determining whether to select the dynamic chip selection pin circuit according to the first selection signal to select a chip selection pin;
when the dynamic chip selection pin circuit is selected, the chip selection control circuit transmits the second selection signal to the dynamic chip selection pin circuit to select the chip selection pin from a plurality of chip selection pins and transmit data to one of the plurality of slave devices corresponding to the selected chip selection pin.
2. The system of claim 1, wherein the chip selection mode selection circuit is further coupled to a static chip selection pin circuit, and the chip selection mode selection circuit selects the chip selection pin by determining whether to select the static chip selection pin circuit or the dynamic chip selection pin circuit according to the first selection signal.
3. The spi system of claim 2 wherein the static chip select pin circuit, the dynamic chip select pin circuit and the plurality of chip select pins are included in a common type of i/o interface.
4. The spi system of claim 1 wherein the master device further comprises a control interface and the chip select control circuit generates the first select signal based on a control signal output from the control interface.
5. The spi system of claim 1 wherein the master device further comprises a memory interface and the chip select control circuit generates the second select signal based on a determination from the memory interface.
6. The spi system of claim 1 wherein the master device further comprises a logic circuit for outputting data to be transmitted to the slave device corresponding to the selected chip select pin.
7. A data transmission method is suitable for a Serial Peripheral Interface (SPI) system, and is characterized by comprising the following steps:
generating a first selection signal by a chip selection control circuit of a main device of the serial peripheral interface system;
selecting a chip selection pin by a chip selection mode selection circuit of the main device and determining whether to select a dynamic chip selection pin circuit of the serial peripheral interface system according to the first selection signal;
when the dynamic chip selection pin circuit is selected, the chip selection control circuit transmits a second selection signal to the dynamic chip selection pin circuit so as to select the chip selection pins from a plurality of chip selection pins of the serial peripheral interface system; and
and transmitting the data to one of the slave devices of the serial peripheral interface system corresponding to the selected chip selection pin.
8. The data transmission method of claim 7, further comprising:
the chip selection mode selection circuit selects the chip selection pin by determining to select a static chip selection pin circuit or the dynamic chip selection pin circuit according to the first selection signal.
9. The data transmission method of claim 7, further comprising:
the chip selection control circuit generates the first selection signal according to a control signal output by a control interface of the serial peripheral interface system.
10. The data transmission method of claim 7, further comprising:
the chip selection control circuit generates the second selection signal according to a judgment result generated by a memory interface of the serial peripheral interface system.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW109146777A TWI750980B (en) | 2020-12-30 | 2020-12-30 | Serial peripheral interface system and data transmssion method thereof |
| TW109146777 | 2020-12-30 |
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| Publication Number | Publication Date |
|---|---|
| CN114690682A true CN114690682A (en) | 2022-07-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111598785.3A Pending CN114690682A (en) | 2020-12-30 | 2021-12-24 | Serial peripheral interface SPI system and data transmission method thereof |
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| TW (1) | TWI750980B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI818659B (en) * | 2022-08-04 | 2023-10-11 | 新唐科技股份有限公司 | Micro-controller, operating system and control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070136502A1 (en) * | 2005-12-14 | 2007-06-14 | Mediatek Inc. | SPI device |
| TWI394050B (en) * | 2009-09-29 | 2013-04-21 | Hon Hai Prec Ind Co Ltd | Data transmission device and method based on serial peripheral interface |
| US8135881B1 (en) * | 2010-09-27 | 2012-03-13 | Skyworks Solutions, Inc. | Dynamically configurable serial data communication interface |
| TWI497304B (en) * | 2012-03-13 | 2015-08-21 | Novatek Microelectronics Corp | Serial interface transmitting method and related device |
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2020
- 2020-12-30 TW TW109146777A patent/TWI750980B/en active
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| TW202225990A (en) | 2022-07-01 |
| TWI750980B (en) | 2021-12-21 |
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