TW202225990A - Serial peripheral interface system and data transmssion method thereof - Google Patents

Serial peripheral interface system and data transmssion method thereof Download PDF

Info

Publication number
TW202225990A
TW202225990A TW109146777A TW109146777A TW202225990A TW 202225990 A TW202225990 A TW 202225990A TW 109146777 A TW109146777 A TW 109146777A TW 109146777 A TW109146777 A TW 109146777A TW 202225990 A TW202225990 A TW 202225990A
Authority
TW
Taiwan
Prior art keywords
chip selection
circuit
pin
selection
chip
Prior art date
Application number
TW109146777A
Other languages
Chinese (zh)
Other versions
TWI750980B (en
Inventor
王政傑
Original Assignee
新唐科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新唐科技股份有限公司 filed Critical 新唐科技股份有限公司
Priority to TW109146777A priority Critical patent/TWI750980B/en
Application granted granted Critical
Publication of TWI750980B publication Critical patent/TWI750980B/en
Priority to CN202111598785.3A priority patent/CN114690682A/en
Publication of TW202225990A publication Critical patent/TW202225990A/en

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/24—Pc safety
    • G05B2219/24215—Scada supervisory control and data acquisition

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Information Transfer Systems (AREA)

Abstract

A Serial Peripheral Interface (SPI) system is provided in the invention. The SPI system includes a plurality of slave devices and a master device. The master device includes a chip selection (CS) control circuit and a CS mode selection circuit. The CS control circuit generates a first selection signal and a second selection signal. The CS mode selection circuit is coupled to the CS control circuit and a dynamic CS pin selection circuit, and determines whether to select the dynamic CS pin selection circuit according to the first selection signal to select a CS pin. When the dynamic CS pin selection circuit is selected, the CS control circuit transmits the second selection signal to the dynamic CS pin selection circuit to select the CS pin from a plurality of CS pins to transmit the data to the slave device of the slave devices which corresponds to the selected CS pin.

Description

串列週邊介面系統和其資料傳輸方法Serial peripheral interface system and data transmission method thereof

本發明之實施例主要係有關於一串列週邊介面(Serial Peripheral Interface，SPI)技術，特別係有關於動態選取晶片選取腳位之串列週邊介面技術。Embodiments of the present invention mainly relate to a Serial Peripheral Interface (SPI) technology, and particularly relate to a SPI technology for dynamically selecting chip selection pins.

串列週邊介面(Serial Peripheral Interface Bus，SPI)是一種用於晶片通信的同步串行通信介面規範。串列週邊介面在單晶片(System on a Chip，SOC)和微控制器(Microcontroller，MCU)的領域中廣泛被使用。Serial Peripheral Interface Bus (SPI) is a synchronous serial communication interface specification for chip communication. Serial peripheral interfaces are widely used in the fields of single chip (System on a Chip, SOC) and microcontroller (Microcontroller, MCU).

在目前的串列週邊介面技術，當主裝置連接從裝置時，主裝置(master device)之一組串列週邊介面主埠(master port)會配置一晶片選取腳位來連接一從裝置(slave device)。然而，當主裝置連接多個從裝置時，主裝置往往必須配置多組串列週邊介面主埠，因而造成腳位之浪費。In the current serial peripheral interface technology, when the master device is connected to the slave device, a set of serial peripheral interface master ports of the master device is configured with a chip select pin to connect to a slave device. device). However, when the master device is connected to multiple slave devices, the master device often has to configure multiple sets of serial peripheral interface master ports, thus resulting in a waste of pins.

有鑑於上述先前技術之問題，本發明之實施例提供了一種串列週邊介面(SPI)系統和資料傳輸方法。In view of the above-mentioned problems of the prior art, embodiments of the present invention provide a Serial Peripheral Interface (SPI) system and a data transmission method.

根據本發明之一實施例提供了一種串列週邊介面系統。串列週邊介面系統包括複數從裝置和一主裝置。主裝置包括一晶片選取控制電路和一晶片選取模式選取電路。晶片選取控制電路用以產生一第一選取信號和一第二選取信號。晶片選取模式選取電路耦接上述晶片選取控制電路和一動態晶片選取腳位電路，且根據上述第一選取信號決定是否選取上述動態晶片選取腳位電路，來選取一晶片選取腳位。當上述動態晶片選取腳位電路被選取時，上述晶片選取控制電路傳送上述第二選取信號至上述動態晶片選取腳位電路，以從複數晶片選取腳位選取上述晶片選取腳位，並將資料傳送給對應上述被選取之晶片選取腳位之上述複數從裝置之一者。According to an embodiment of the present invention, a serial peripheral interface system is provided. The serial peripheral interface system includes a plurality of slave devices and a master device. The main device includes a wafer selection control circuit and a wafer selection mode selection circuit. The chip selection control circuit is used for generating a first selection signal and a second selection signal. The chip selection mode selection circuit is coupled to the chip selection control circuit and a dynamic chip selection pin circuit, and determines whether to select the dynamic chip selection pin circuit according to the first selection signal to select a chip selection pin. When the dynamic chip selection pin circuit is selected, the chip selection control circuit transmits the second selection signal to the dynamic chip selection pin circuit, so as to select the chip selection pin from a plurality of chip selection pins, and transmit the data One of the plurality of slave devices corresponding to the selected chip selection pin is selected.

在一些實施例中，上述晶片選取模式選取電路更耦接一靜態晶片選取腳位電路，且上述晶片選取模式選取電路根據上述第一選取信號，決定選取上述靜態晶片選取腳位電路或上述動態晶片選取腳位電路，來選取上述晶片選取腳位。In some embodiments, the chip selection mode selection circuit is further coupled to a static chip selection pin circuit, and the chip selection mode selection circuit determines to select the static chip selection pin circuit or the dynamic chip according to the first selection signal The selection pin circuit is used to select the above chip selection pins.

在一些實施例中，上述靜態晶片選取腳位電路、上述動態晶片選取腳位電路和上述複數晶片選取腳位包含在一通用型之輸入輸出介面中。In some embodiments, the static chip selection pin circuit, the dynamic chip selection pin circuit, and the plurality of chip selection pins are included in a general-purpose I/O interface.

在一些實施例中，上述主裝置更包括一控制介面，且上述晶片選取控制電路根據來自上述控制介面輸出之一控制信號，產生上述第一選取信號。In some embodiments, the host device further includes a control interface, and the chip selection control circuit generates the first selection signal according to a control signal output from the control interface.

在一些實施例中，上述主裝置更包括一記憶體介面，且上述晶片選取控制電路根據來自上述記憶體介面產生之一判斷結果，產生上述第二選取信號。In some embodiments, the host device further includes a memory interface, and the chip selection control circuit generates the second selection signal according to a judgment result generated from the memory interface.

在一些實施例中，上述主裝置更包括一邏輯電路，以輸出要傳輸給對應上述被選取之晶片選取腳位之上述從裝置之資料。In some embodiments, the master device further includes a logic circuit for outputting data to be transmitted to the slave device corresponding to the selected chip selection pin.

根據本發明之一實施例提供了一種資料傳輸方法。資料傳輸方法適用一串列週邊介面(SPI)系統。資料傳輸方法之步驟包括： 藉由上述串列週邊介面系統之一主裝置之一晶片選取控制電路，產生一第一選取信號；藉由上述主裝置之一晶片選取模式選取電路，根據上述第一選取信號決定是否選取上述串列週邊介面系統之一動態晶片選取腳位電路，來選取一晶片選取腳位；當上述動態晶片選取腳位電路被選取時，藉由上述晶片選取控制電路傳送一第二選取信號至上述動態晶片選取腳位電路，以從上述串列週邊介面系統之複數晶片選取腳位選取上述晶片選取腳位；以及將資料傳送給對應上述被選取之晶片選取腳位之上述串列週邊介面系統之複數從裝置之一者。According to an embodiment of the present invention, a data transmission method is provided. The data transfer method is suitable for a Serial Peripheral Interface (SPI) system. The steps of the data transmission method include: generating a first selection signal by a chip selection control circuit of a host device of the serial peripheral interface system; The selection signal determines whether to select a dynamic chip selection pin circuit of the serial peripheral interface system to select a chip selection pin; when the dynamic chip selection pin circuit is selected, the chip selection control circuit transmits a first Two select signals are sent to the dynamic chip select pin circuit to select the chip select pin from a plurality of chip select pins of the serial peripheral interface system; and send data to the string corresponding to the selected chip select pin One of the plural slave devices of the row peripheral interface system.

關於本發明其他附加的特徵與優點，此領域之熟習技術人士，在不脫離本發明之精神和範圍內，當可根據本案實施方法中所揭露之串列週邊介面系統和資料傳輸方法，做些許的更動與潤飾而得到。Regarding other additional features and advantages of the present invention, those skilled in the art may, without departing from the spirit and scope of the present invention, do some obtained by changing and retouching.

本章節所敘述的是實施本發明之較佳方式，目的在於說明本發明之精神而非用以限定本發明之保護範圍，本發明之保護範圍當視後附之申請專利範圍所界定者為準。What is described in this chapter is the best way to implement the present invention, and the purpose is to illustrate the spirit of the present invention rather than to limit the protection scope of the present invention. .

第1圖係顯示根據本發明之一實施例所述之一串列週邊介面(Serial Peripheral Interface，SPI)系統100之方塊圖。如第1圖所示，串列週邊介面系統100可包括一高級微控制器匯流排架構(Advanced Microcontroller Bus Architecture， AMBA)(例如：一高級高性能匯流排(Advanced High-Performance Bus，AHB))110、一主裝置(master device)120、一通用型之輸入輸出(General-purpose input/output，GPIO)介面130、一第一從裝置(slave device)140以及一第二從裝置150。注意地是，在第1圖中所示之方塊圖，僅係為了方便說明本發明之實施例，但本發明並不以第1圖為限。串列週邊介面系統100中亦可包含其他元件。FIG. 1 shows a block diagram of a Serial Peripheral Interface (SPI) system 100 according to an embodiment of the present invention. As shown in FIG. 1, the serial peripheral interface system 100 may include an Advanced Microcontroller Bus Architecture (AMBA) (eg, an Advanced High-Performance Bus (AHB)) 110 , a master device 120 , a general-purpose input/output (GPIO) interface 130 , a first slave device 140 and a second slave device 150 . It should be noted that the block diagram shown in FIG. 1 is only for the convenience of explaining the embodiment of the present invention, but the present invention is not limited to the first FIG. Other components may also be included in the serial peripheral interface system 100 .

根據本發明一實施例，如第1圖所示，主裝置120可至少包括一記憶體介面(memory interface)121、一控制介面(control interface)122、一邏輯電路123、一晶片選取(chip select，CS)控制電路124，以及一晶片選取(CS)模式選取電路125。注意地是，在第1圖中所示之主裝置120，僅係為了方便說明本發明之實施例，但本發明並不以第1圖為限。主裝置120中亦可包含其他元件。According to an embodiment of the present invention, as shown in FIG. 1 , the host device 120 may at least include a memory interface 121 , a control interface 122 , a logic circuit 123 , and a chip select , CS) control circuit 124 , and a chip selection (CS) mode selection circuit 125 . It should be noted that, the main device 120 shown in FIG. 1 is only for the convenience of explaining the embodiment of the present invention, but the present invention is not limited to FIG. 1 . Other elements may also be included in the host device 120 .

此外，根據本發明一實施例，如第1圖所示，通用型之輸入輸出130可包括一主裝置輸入從裝置輸出腳位MISO(Master Output/Slave Input)、一主裝置輸出從裝置輸入腳位MOSI(Master Input/Slave Output)、一時脈腳位CLK、一第一晶片選取腳位CS0、一第二晶片選取腳位CS1、一靜態晶片選取腳位電路131和一動態晶片選取腳位電路132。此外，根據本發明一實施例，如第1圖所示，第一晶片選取腳位CS0會連接至第一從裝置140，且第二晶片選取腳位CS1會連接至第二從裝置150。In addition, according to an embodiment of the present invention, as shown in FIG. 1 , the general-purpose I/O 130 may include a master input and slave output pin MISO (Master Output/Slave Input), a master output and a slave input pin Bit MOSI (Master Input/Slave Output), a clock pin CLK, a first chip selection pin CS0, a second chip selection pin CS1, a static chip selection pin circuit 131 and a dynamic chip selection pin circuit 132. In addition, according to an embodiment of the present invention, as shown in FIG. 1 , the first chip pick pin CS0 is connected to the first slave device 140 , and the second chip pick pin CS1 is connected to the second slave device 150 .

根據本發明之實施例，記憶體介面121可判斷高級微控制器匯流排架構110所存取之記憶體位址係對應到哪一從裝置，以產生依判斷結果S1。舉例來說，若第一從裝置140所對應之記憶體位址範圍是0x1000~0x1ffff，且第二從裝置150所對應之記憶體位址範圍是0x2000~0x2ffff，當記憶體介面121判斷高級微控制器匯流排架構110所存取之記憶體位址係在記憶體位址範圍0x1000~0x1ffff中，記憶體介面121就會判斷高級微控制器匯流排架構110所存取之記憶體位址係對應到第一從裝置140。注意地是，上述例子僅係用以說明本發明之實施例，但本發明不以此為限。記憶體介面121會將判斷結果S1傳送給邏輯電路123和晶片選取控制電路124。According to an embodiment of the present invention, the memory interface 121 can determine which slave device the memory address accessed by the advanced microcontroller bus architecture 110 corresponds to, so as to generate the determination result S1. For example, if the memory address range corresponding to the first slave device 140 is 0x1000~0x1ffff, and the memory address range corresponding to the second slave device 150 is 0x2000~0x2ffff, when the memory interface 121 determines that the advanced microcontroller The memory address accessed by the bus architecture 110 is in the memory address range 0x1000~0x1ffff, and the memory interface 121 determines that the memory address accessed by the advanced microcontroller bus architecture 110 corresponds to the first slave device 140 . Note that the above examples are only used to illustrate the embodiments of the present invention, but the present invention is not limited thereto. The memory interface 121 transmits the judgment result S1 to the logic circuit 123 and the chip selection control circuit 124 .

根據本發明之實施例，控制介面122可根據來自高級微控制器匯流排架構110之指令，產生一控制信號S2，並將控制訊號S2傳送給邏輯電路123和晶片選取控制電路124。邏輯電路123和晶片選取控制電路124可根據控制信號S2得知係要使用靜態晶片選取腳位功能或是動態晶片選取腳位功能(即得知要選取靜態晶片選取腳位電路131或動態晶片選取腳位電路132)，來選取晶片選取腳位。According to an embodiment of the present invention, the control interface 122 can generate a control signal S2 according to an instruction from the advanced microcontroller bus architecture 110 and transmit the control signal S2 to the logic circuit 123 and the chip selection control circuit 124 . The logic circuit 123 and the chip selection control circuit 124 can know whether to use the static chip selection pin function or the dynamic chip selection pin function according to the control signal S2 (that is, know that the static chip selection pin circuit 131 or the dynamic chip selection pin function is to be selected. The pin circuit 132) is used to select the chip selection pin.

根據本發明之實施例，邏輯電路123可視為一組串列週邊介面主埠(master port)。根據本發明之實施例，邏輯電路123可包括一主裝置輸入從裝置輸出埠MISO1、一主裝置輸出從裝置輸入埠MOSI1、一時脈腳位CLK1埠和一晶片選取埠nCS。邏輯電路123可藉由主裝置輸入從裝置輸出埠MISO1、主裝置輸出從裝置輸入埠MOSI1、時脈腳位CLK1埠和晶片選取埠nCS傳送資料或訊號給被選取之從裝置。如第1圖所示，主裝置輸入從裝置輸出埠MISO1會連接到通用型之輸入輸出130之主裝置輸入從裝置輸出腳位MISO，以傳送信號MISO_OUT至主裝置輸入從裝置輸出腳位MISO。主裝置輸出從裝置輸入埠MOSI1會連接到通用型之輸入輸出130之主裝置輸出從裝置輸入腳位MOSI，以傳送信號MOSI_OUT至主裝置輸出從裝置輸入腳位MOSI。時脈輸出埠CLK1埠會連接到通用型之輸入輸出130之時脈腳位CLK，以傳送時脈信號CLK_OUT至時脈腳位CLK。晶片選取埠nCS會連接到晶片選取模式選取電路125，以傳送訊號nCS_OUT至晶片選取模式選取電路125。According to an embodiment of the present invention, the logic circuit 123 can be regarded as a set of serial peripheral interface master ports. According to an embodiment of the present invention, the logic circuit 123 may include a master input slave output port MISO1, a master output slave input port MOSI1, a clock pin CLK1 port and a chip select port nCS. The logic circuit 123 can transmit data or signals to the selected slave device through the master input slave output port MISO1, the master output slave input port MOSI1, the clock pin CLK1 port and the chip select port nCS. As shown in FIG. 1, the master input and slave output port MISO1 is connected to the master input slave output pin MISO of the general-purpose I/O 130 to transmit the signal MISO_OUT to the master input slave output pin MISO. The master output slave input port MOSI1 is connected to the master output slave input pin MOSI of the general-purpose I/O 130 to transmit the signal MOSI_OUT to the master output slave input pin MOSI. The clock output port CLK1 is connected to the clock pin CLK of the general-purpose input and output 130 to transmit the clock signal CLK_OUT to the clock pin CLK. The chip select port nCS is connected to the chip select mode select circuit 125 to transmit the signal nCS_OUT to the chip select mode select circuit 125 .

根據本發明之實施例，晶片選取控制電路124可根據接收到控制信號S2，得知要使用靜態晶片選取腳位功能或是動態晶片選取腳位功能(即得知要選取靜態晶片選取腳位電路131或動態晶片選取腳位電路132)，來選取晶片選取腳位，並據此產生一第一選取信號S3。接著，晶片選取控制電路124會將第一選取信號S3傳送給晶片選取模式選取電路125。晶片選取模式選取電路125可根據第一選取信號S3，決定使用靜態晶片選取腳位電路131或動態晶片選取腳位電路132，來選取晶片選取腳位和傳送訊號nCS_OUT。According to an embodiment of the present invention, the chip selection control circuit 124 can know whether to use the static chip selection pin function or the dynamic chip selection pin function according to the received control signal S2 (that is, know that the static chip selection pin circuit is to be selected) 131 or the dynamic chip selection pin circuit 132) to select the chip selection pin and generate a first selection signal S3 accordingly. Next, the wafer selection control circuit 124 transmits the first selection signal S3 to the wafer selection mode selection circuit 125 . The chip selection mode selection circuit 125 can decide to use the static chip selection pin circuit 131 or the dynamic chip selection pin circuit 132 according to the first selection signal S3 to select the chip selection pin and transmit the signal nCS_OUT.

當靜態晶片選取腳位電路131被選取時，靜態晶片選取腳位電路131會根據通用型之輸入輸出130之一暫存器(圖未顯示)之數值決定致能第一晶片選取腳位CS0或第二晶片選取腳位CS1。When the static chip selection pin circuit 131 is selected, the static chip selection pin circuit 131 determines to enable the first chip selection pin CS0 or the value of a register (not shown in the figure) of the general-purpose input and output 130. The second chip select pin CS1.

當動態晶片選取腳位電路132被選取時，動態晶片選取腳位電路132可根據來自晶片選取控制電路124之第二選取信號S4，決定致能第一晶片選取腳位CS0或第二晶片選取腳位CS1。底下將會有更詳細之敘述。When the dynamic chip selection pin circuit 132 is selected, the dynamic chip selection pin circuit 132 can determine to enable the first chip selection pin CS0 or the second chip selection pin according to the second selection signal S4 from the chip selection control circuit 124 bit CS1. There will be a more detailed description below.

根據本發明之一實施例，當晶片選取控制電路124根據控制信號S2得知要使用動態晶片選取腳位功能(即動態晶片選取腳位電路132被選取)來選取晶片選取腳位時，晶片選取控制電路124會根據判斷結果S1，得知要從存取哪一從裝置，以決定要致能第一晶片選取腳位CS0或第二晶片選取腳位CS1，並據此產生一第二選取信號S4。接著，晶片選取控制電路124會將第二選取信號S4傳送給動態晶片選取腳位電路132。動態晶片選取腳位電路132即可根據第二選取信號S4，決定致能第一晶片選取腳位CS0或第二晶片選取腳位CS1，以將訊號nCS_OUT所包含之資料傳送給第一晶片選取腳位CS0或第二晶片選取腳位CS1。也就是說，動態晶片選取腳位電路132可根據第二選取信號S4，動態選取第一晶片選取腳位CS0或第二晶片選取腳位CS1。According to an embodiment of the present invention, when the chip selection control circuit 124 learns according to the control signal S2 to use the dynamic chip selection pin function (ie, the dynamic chip selection pin circuit 132 is selected) to select the chip selection pin, the chip selection The control circuit 124 will know which slave device to access from according to the judgment result S1, so as to determine whether to enable the first chip selection pin CS0 or the second chip selection pin CS1, and generate a second selection signal accordingly S4. Next, the chip selection control circuit 124 transmits the second selection signal S4 to the dynamic chip selection pin circuit 132 . The dynamic chip selection pin circuit 132 can determine to enable the first chip selection pin CS0 or the second chip selection pin CS1 according to the second selection signal S4, so as to transmit the data contained in the signal nCS_OUT to the first chip selection pin Bit CS0 or the second chip select pin CS1. That is, the dynamic chip selection pin circuit 132 can dynamically select the first chip selection pin CS0 or the second chip selection pin CS1 according to the second selection signal S4.

當第一晶片選取腳位CS0被選取時，主裝置120即可和第一從裝置140進行通訊，以及當第二晶片選取腳位CS1被選取時，主裝置120即可和第二從裝置150進行通訊。When the first chip pick pin CS0 is selected, the master device 120 can communicate with the first slave device 140, and when the second chip pick pin CS1 is selected, the master device 120 can communicate with the second slave device 150 to communicate.

第2圖係根據本發明之一實施例所述之一資料傳輸方法之流程圖。資料傳輸方法可適用串列週邊介面(Serial Peripheral Interface，SPI)系統100。如第2圖所示，在步驟S210，藉由串列週邊介面系統100之主裝置之一晶片選取控制電路，產生一第一選取信號。FIG. 2 is a flowchart of a data transmission method according to an embodiment of the present invention. The data transmission method is applicable to the Serial Peripheral Interface (SPI) system 100 . As shown in FIG. 2 , in step S210 , a first selection signal is generated by a chip selection control circuit of a main device of the serial peripheral interface system 100 .

在步驟S220，藉由串列週邊介面系統100之主裝置之一晶片選取模式選取電路，根據第一選取信號決定是否選取串列週邊介面系統之一動態晶片選取腳位電路或一靜態晶片選取腳位電路，來選取一晶片選取腳位。In step S220, a chip selection mode selection circuit of the main device of the SPI system 100 determines whether to select a dynamic chip selection pin circuit or a static chip selection pin according to the first selection signal. A bit circuit is used to select a chip selection pin.

當動態晶片選取腳位電路被選取時，進行步驟S230。在步驟S230，藉由晶片選取控制電路傳送一第二選取信號至動態晶片選取腳位電路，以根據第二選取信號從串列週邊介面系統100之複數晶片選取腳位選取上述晶片選取腳位。在步驟S250，藉由串列週邊介面系統100之一邏輯電路將要輸出給對應被選取之晶片選取腳位之從裝置之資料給該從裝置。在此實施例中，靜態晶片選取腳位電路、動態晶片選取腳位電路和複數晶片選取腳位可包含在串列週邊介面系統100之一通用型之輸入輸出介面中。When the dynamic chip selection pin circuit is selected, step S230 is performed. In step S230, the chip selection control circuit transmits a second selection signal to the dynamic chip selection pin circuit to select the chip selection pin from the plurality of chip selection pins of the serial peripheral interface system 100 according to the second selection signal. In step S250, data to be output to the slave device corresponding to the selected chip selection pin is sent to the slave device by a logic circuit of the serial peripheral interface system 100. In this embodiment, the static chip select pin circuit, the dynamic chip select pin circuit, and the plurality of chip select pins may be included in a general-purpose I/O interface of the serial peripheral interface system 100 .

當靜態晶片選取腳位電路被選取時，進行步驟S240。在步驟S240，藉由串列週邊介面系統100之通用型之輸入輸出介面從串列週邊介面系統100之複數晶片選取腳位選取一晶片選取腳位。接著，進行步驟S250。When the static chip selection pin circuit is selected, step S240 is performed. In step S240 , a chip selection pin is selected from a plurality of chip selection pins of the SATA peripheral interface system 100 by using the general-purpose I/O interface of the serial peripheral interface system 100 . Next, step S250 is performed.

根據本發明之實施例，資料傳輸方法更包括，藉由串列週邊介面系統100之晶片選取控制電路根據來自串列週邊介面系統100之一控制介面輸出之一控制信號，產生第一選取信號。According to an embodiment of the present invention, the data transmission method further includes: generating a first selection signal according to a control signal output from a control interface of the serial peripheral interface system 100 by the chip selection control circuit of the serial peripheral interface system 100 .

根據本發明之實施例，資料傳輸方法更包括，藉由串列週邊介面系統100之晶片選取控制電路根據來自串列週邊介面系統100之一記憶體介面產生之一判斷結果，產生第二選取信號。記憶體介面可藉由判斷串列週邊介面系統100之一高級微控制器匯流排架構所存取之記憶體位址係對應到哪一從裝置，以產生依判斷結果S1。According to an embodiment of the present invention, the data transmission method further includes: generating a second selection signal according to a judgment result generated from a memory interface of the serial peripheral interface system 100 by the chip selection control circuit of the serial peripheral interface system 100 . The memory interface can generate the judgment result S1 by judging which slave device the memory address accessed by an advanced microcontroller bus structure of the serial peripheral interface system 100 corresponds to.

根據本發明提出之串列週邊介面系統和資料傳輸方法，可藉由一動態晶片選取腳位電路來選取需要進行通訊之從裝置所對應之靜態晶片選取腳位。因此，在本發明提出之串列週邊介面系統中，主裝置僅需要配置一組主埠即可達成切換不同靜態晶片選取腳位之目的。因此，本發明提出之串列週邊介面系統和資料傳輸方法可避免腳位之浪費。According to the serial peripheral interface system and data transmission method proposed in the present invention, a static chip selection pin corresponding to a slave device that needs to be communicated can be selected by a dynamic chip selection pin circuit. Therefore, in the serial peripheral interface system proposed by the present invention, the main device only needs to configure one set of main ports to achieve the purpose of switching different static chip selection pins. Therefore, the serial peripheral interface system and data transmission method proposed by the present invention can avoid the waste of pins.

本說明書中以及申請專利範圍中的序號，例如「第一」、「第二」等等，僅係為了方便說明，彼此之間並沒有順序上的先後關係。The serial numbers in this specification and in the scope of the patent application, such as "first", "second", etc., are only for convenience of description, and there is no sequential relationship between them.

本發明之說明書所揭露之方法和演算法之步驟，可直接透過執行一處理器直接應用在硬體以及軟體模組或兩者之結合上。一軟體模組(包括執行指令和相關數據)和其它數據可儲存在數據記憶體中，像是隨機存取記憶體(RAM)、快閃記憶體(flash memory)、唯讀記憶體(ROM)、可抹除可規化唯讀記憶體(EPROM)、電子可抹除可規劃唯讀記憶體(EEPROM)、暫存器、硬碟、可攜式應碟、光碟唯讀記憶體(CD-ROM)、DVD或在此領域習之技術中任何其它電腦可讀取之儲存媒體格式。一儲存媒體可耦接至一機器裝置，舉例來說，像是電腦/處理器(爲了說明之方便，在本說明書以處理器來表示)，上述處理器可透過來讀取資訊(像是程式碼)，以及寫入資訊至儲存媒體。一儲存媒體可整合一處理器。一特殊應用積體電路(ASIC)包括處理器和儲存媒體。一用戶設備則包括一特殊應用積體電路。換句話說，處理器和儲存媒體以不直接連接用戶設備的方式，包含於用戶設備中。此外，在一些實施例中，任何適合電腦程序之產品包括可讀取之儲存媒體，其中可讀取之儲存媒體包括和一或多個所揭露實施例相關之程式碼。在一些實施例中，電腦程序之產品可包括封裝材料。The steps of the method and algorithm disclosed in the description of the present invention can be directly applied to hardware and software modules or a combination of the two by executing a processor. A software module (including execution instructions and associated data) and other data can be stored in data memory, such as random access memory (RAM), flash memory, read only memory (ROM) , Erasable Programmable Read-Only Memory (EPROM), Electronically Erasable Programmable Read-Only Memory (EEPROM), Scratchpad, Hard Disk, Portable Disk, CD-ROM ROM), DVD, or any other computer-readable storage media format known in the art. A storage medium can be coupled to a machine device, such as a computer/processor (for convenience of description, it is referred to as a processor in this specification), and the processor can read information (such as a program) through code), and write information to the storage medium. A storage medium can integrate a processor. An application specific integrated circuit (ASIC) includes a processor and a storage medium. A user equipment includes an application-specific integrated circuit. In other words, the processor and storage medium are included in the user equipment in a manner that is not directly connected to the user equipment. Furthermore, in some embodiments, any product suitable for a computer program includes a readable storage medium, wherein the readable storage medium includes code associated with one or more of the disclosed embodiments. In some embodiments, the product of the computer program may include packaging material.

以上段落使用多種層面描述。顯然的，本文的教示可以多種方式實現，而在範例中揭露之任何特定架構或功能僅為一代表性之狀況。根據本文之教示，任何熟知此技藝之人士應理解在本文揭露之各層面可獨立實作或兩種以上之層面可以合併實作。The above paragraphs use multiple levels of description. Obviously, the teachings herein can be implemented in a variety of ways, and any particular architecture or functionality disclosed in the examples is merely a representative case. Based on the teachings herein, anyone skilled in the art should understand that each aspect disclosed herein may be implemented independently or two or more aspects may be implemented in combination.

雖然本揭露已以實施例揭露如上，然其並非用以限定本揭露，任何熟習此技藝者，在不脫離本揭露之精神和範圍內，當可作些許之更動與潤飾，因此發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present disclosure has been disclosed above with examples, it is not intended to limit the present disclosure. Anyone who is familiar with the art can make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the invention is The scope of the patent application attached herewith shall prevail.

100:串列週邊介面系統 110:高級微控制器匯流排架構 120:主裝置 121:記憶體介面 122:控制介面 123:邏輯電路 124:晶片選取控制電路 125:晶片選取模式選取電路 130:通用型之輸入輸出介面 131:靜態晶片選取腳位電路 132:動態晶片選取腳位電路 140:第一從裝置 150:第二從裝置 MISO:主裝置輸入從裝置輸出腳位 MISO1:主裝置輸入從裝置輸出埠 MOSI:主裝置輸出從裝置輸入腳位 MOSI1:主裝置輸出從裝置輸入埠 CLK:時脈腳位 CLK1:時脈輸出埠 CS0:第一晶片選取腳位 CS1:第二晶片選取腳位 nCS:晶片選取埠 S1:判斷結果 S2:控制信號 S3:第一選取信號 S4:第二選取信號 S210~S250:步驟 100: Serial Peripheral Interface System 110: Advanced Microcontroller Bus Architecture 120: Main unit 121: Memory interface 122: Control interface 123: Logic Circuits 124: Chip selection control circuit 125: Chip selection mode selection circuit 130: Universal input and output interface 131: Static chip selection pin circuit 132: Dynamic chip selection pin circuit 140: First slave device 150: Second slave device MISO: Master input slave output pin MISO1: Master input slave output port MOSI: master device output slave device input pin MOSI1: Master output slave input port CLK: Clock pin CLK1: clock output port CS0: The first chip selection pin CS1: The second chip selection pin nCS: Chip Select Port S1: Judgment result S2: control signal S3: First selection signal S4: Second selection signal S210~S250: Steps

第1圖係顯示根據本發明之一實施例所述之一串列週邊介面系統100之方塊圖。 第2圖係根據本發明之一實施例所述之資料傳輸方法之流程圖。 FIG. 1 shows a block diagram of a serial peripheral interface system 100 according to one embodiment of the present invention. FIG. 2 is a flowchart of a data transmission method according to an embodiment of the present invention.

100:串列週邊介面系統 100: Serial Peripheral Interface System

110:高級微控制器匯流排架構 110: Advanced Microcontroller Bus Architecture

120:主裝置 120: Main unit

121:記憶體介面 121: Memory interface

122:控制介面 122: Control interface

123:邏輯電路 123: Logic Circuits

124:晶片選取控制電路 124: Chip selection control circuit

125:晶片選取模式選取電路 125: Chip selection mode selection circuit

130:通用型之輸入輸出介面 130: Universal input and output interface

131:靜態晶片選取腳位電路 131: Static chip selection pin circuit

132:動態晶片選取腳位電路 132: Dynamic chip selection pin circuit

140:第一從裝置 140: First slave device

150:第二從裝置 150: Second slave device

MISO:主裝置輸入從裝置輸出腳位 MISO: Master input slave output pin

MISO1:主裝置輸入從裝置輸出埠 MISO1: Master input slave output port

MOSI:主裝置輸出從裝置輸入腳位 MOSI: master device output slave device input pin

MOSI1:主裝置輸出從裝置輸入埠 MOSI1: Master output slave input port

CLK:時脈腳位 CLK: Clock pin

CLK1:時脈輸出埠 CLK1: clock output port

CS0:第一晶片選取腳位 CS0: The first chip selection pin

CS1第二晶片選取腳位 CS1 second chip selection pin

nCS:晶片選取埠 nCS: Chip Select Port

S1:判斷結果 S1: Judgment result

S2:控制信號 S2: control signal

S3:第一選取信號 S3: First selection signal

S4:第二選取信號 S4: Second selection signal

Claims (10)

一種串列週邊介面(SPI)系統，包括： 複數從裝置；以及 一主裝置，包括： 一晶片選取控制電路，產生一第一選取信號和一第二選取信號；以及 一晶片選取模式選取電路，耦接上述晶片選取控制電路和一動態晶片選取腳位電路，且根據上述第一選取信號決定是否選取上述動態晶片選取腳位電路，來選取一晶片選取腳位； 其中當上述動態晶片選取腳位電路被選取時，上述晶片選取控制電路傳送上述第二選取信號至上述動態晶片選取腳位電路，以從複數晶片選取腳位選取上述晶片選取腳位，並將資料傳送給對應上述被選取之晶片選取腳位之上述複數從裝置之一者。 A Serial Peripheral Interface (SPI) system, comprising: plural slave devices; and a main unit, including: a chip selection control circuit that generates a first selection signal and a second selection signal; and a chip selection mode selection circuit, coupled to the chip selection control circuit and a dynamic chip selection pin circuit, and determines whether to select the dynamic chip selection pin circuit according to the first selection signal to select a chip selection pin; When the dynamic chip selection pin circuit is selected, the chip selection control circuit transmits the second selection signal to the dynamic chip selection pin circuit, so as to select the chip selection pin from a plurality of chip selection pins, and transfer the data It is transmitted to one of the plurality of slave devices corresponding to the selected chip selection pin. 如請求項1之串列週邊介面系統，其中上述晶片選取模式選取電路更耦接一靜態晶片選取腳位電路，且上述晶片選取模式選取電路根據上述第一選取信號，決定選取上述靜態晶片選取腳位電路或上述動態晶片選取腳位電路，來選取上述晶片選取腳位。The serial peripheral interface system of claim 1, wherein the chip selection mode selection circuit is further coupled to a static chip selection pin circuit, and the chip selection mode selection circuit determines to select the static chip selection pin according to the first selection signal The bit circuit or the dynamic chip selection pin circuit is used to select the chip selection pin. 如請求項2之串列週邊介面系統，其中上述靜態晶片選取腳位電路、上述動態晶片選取腳位電路和上述複數晶片選取腳位包含在一通用型之輸入輸出介面中。The serial peripheral interface system of claim 2, wherein the static chip selection pin circuit, the dynamic chip selection pin circuit, and the plurality of chip selection pins are included in a general-purpose I/O interface. 如請求項1之串列週邊介面系統，其中上述主裝置更包括一控制介面，且上述晶片選取控制電路根據來自上述控制介面輸出之一控制信號，產生上述第一選取信號。The serial peripheral interface system of claim 1, wherein the host device further comprises a control interface, and the chip selection control circuit generates the first selection signal according to a control signal output from the control interface. 如請求項1之串列週邊介面系統，其中上述主裝置更包括一記憶體介面，且上述晶片選取控制電路根據來自上述記憶體介面產生之一判斷結果，產生上述第二選取信號。The serial peripheral interface system of claim 1, wherein the host device further includes a memory interface, and the chip selection control circuit generates the second selection signal according to a judgment result generated from the memory interface. 如請求項1之串列週邊介面系統，其中上述主裝置更包括一邏輯電路，以輸出要傳輸給對應上述被選取之晶片選取腳位之上述從裝置之資料。The serial peripheral interface system of claim 1, wherein the master device further comprises a logic circuit for outputting data to be transmitted to the slave device corresponding to the selected chip selection pin. 一種資料傳輸方法，適用一串列週邊介面(SPI)系統，包括： 藉由上述串列週邊介面系統之一主裝置之一晶片選取控制電路，產生一第一選取信號； 藉由上述主裝置之一晶片選取模式選取電路，根據上述第一選取信號決定是否選取上述串列週邊介面系統之一動態晶片選取腳位電路，來選取一晶片選取腳位； 當上述動態晶片選取腳位電路被選取時，藉由上述晶片選取控制電路傳送一第二選取信號至上述動態晶片選取腳位電路，以從上述串列週邊介面系統之複數晶片選取腳位選取上述晶片選取腳位；以及 將資料傳送給對應上述被選取之晶片選取腳位之上述串列週邊介面系統之複數從裝置之一者。 A data transmission method suitable for a Serial Peripheral Interface (SPI) system, comprising: A first selection signal is generated by a chip selection control circuit of a main device of the serial peripheral interface system; A chip selection pin is selected by determining whether to select a dynamic chip selection pin circuit of the serial peripheral interface system according to the first selection signal by a chip selection mode selection circuit of the host device; When the dynamic chip selection pin circuit is selected, the chip selection control circuit transmits a second selection signal to the dynamic chip selection pin circuit to select the chip selection pin from a plurality of chip selection pins of the serial peripheral interface system chip selection pins; and The data is transmitted to one of the plurality of slave devices of the serial peripheral interface system corresponding to the selected chip selection pin. 如請求項7之資料傳輸方法，更包括： 藉由上述晶片選取模式選取電路根據上述第一選取信號，決定選取一靜態晶片選取腳位電路或上述動態晶片選取腳位電路，來選取上述晶片選取腳位。 If the data transmission method of claim 7, it also includes: The chip selection pin is selected by the chip selection mode selection circuit determining to select a static chip selection pin circuit or the dynamic chip selection pin circuit according to the first selection signal. 如請求項7之資料傳輸方法，更包括： 藉由上述晶片選取控制電路根據來自上述串列週邊介面系統之一控制介面輸出之一控制信號，產生上述第一選取信號。 If the data transmission method of claim 7, it also includes: The first selection signal is generated by the chip selection control circuit according to a control signal output from a control interface of the serial peripheral interface system. 如請求項7之資料傳輸方法，更包括： 藉由上述晶片選取控制電路根據來自上述串列週邊介面系統之一記憶體介面產生之一判斷結果，產生上述第二選取信號。 If the data transmission method of claim 7, it also includes: The second selection signal is generated by the chip selection control circuit according to a judgment result generated from a memory interface of the serial peripheral interface system.
TW109146777A 2020-12-30 2020-12-30 Serial peripheral interface system and data transmssion method thereof TWI750980B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW109146777A TWI750980B (en) 2020-12-30 2020-12-30 Serial peripheral interface system and data transmssion method thereof
CN202111598785.3A CN114690682A (en) 2020-12-30 2021-12-24 Serial peripheral interface SPI system and data transmission method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW109146777A TWI750980B (en) 2020-12-30 2020-12-30 Serial peripheral interface system and data transmssion method thereof

Publications (2)

Publication Number Publication Date
TWI750980B TWI750980B (en) 2021-12-21
TW202225990A true TW202225990A (en) 2022-07-01

Family

ID=80681409

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109146777A TWI750980B (en) 2020-12-30 2020-12-30 Serial peripheral interface system and data transmssion method thereof

Country Status (2)

Country Link
CN (1) CN114690682A (en)
TW (1) TWI750980B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI818659B (en) * 2022-08-04 2023-10-11 新唐科技股份有限公司 Micro-controller, operating system and control method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070136502A1 (en) * 2005-12-14 2007-06-14 Mediatek Inc. SPI device
TWI394050B (en) * 2009-09-29 2013-04-21 Hon Hai Prec Ind Co Ltd Data transmission device and method based on serial peripheral interface
US8135881B1 (en) * 2010-09-27 2012-03-13 Skyworks Solutions, Inc. Dynamically configurable serial data communication interface
TWI497304B (en) * 2012-03-13 2015-08-21 Novatek Microelectronics Corp Serial interface transmitting method and related device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI818659B (en) * 2022-08-04 2023-10-11 新唐科技股份有限公司 Micro-controller, operating system and control method

Also Published As

Publication number Publication date
CN114690682A (en) 2022-07-01
TWI750980B (en) 2021-12-21

Similar Documents

Publication Publication Date Title
TWI679539B (en) Master-slave system, command execution method and data access method
JP5128683B2 (en) Method for providing a peripheral component interconnect (PCI) compatible transaction level protocol for system on chip (SoC)
US10140242B2 (en) General purpose input/output (GPIO) signal bridging with I3C bus interfaces and virtualization in a multi-node network
US8010731B2 (en) Integrating non-peripheral component interconnect (PCI) resource into a personal computer system
US7353315B2 (en) Bus controller with virtual bridge
JP2002049576A (en) Bus architecture for system mounted on chip
KR20140035772A (en) A embedded multimedia card(emmc), emmc system including the emmc, and a method for operating the emmc
CN101320344B (en) Multi-core or numerous-core processor function verification device and method
US20230266963A1 (en) Firmware updating method, apparatus and data system
TWI750980B (en) Serial peripheral interface system and data transmssion method thereof
CN110781130A (en) System on chip
US20080052474A1 (en) Write data mask method and system
CN103226531A (en) Dual-port peripheral configuration interface circuit
JP3287283B2 (en) PCI bus interrupt steering circuit
JP4257358B2 (en) Bus control method and apparatus
US9442788B2 (en) Bus protocol checker, system on chip including the same, bus protocol checking method
US20040186973A1 (en) Memory management in a data processing system
US20020188771A1 (en) Direct memory access controller for carrying out data transfer by determining whether or not burst access can be utilized in an external bus and access control method thereof
US20050120155A1 (en) Multi-bus I2C system
US20230315591A1 (en) PCIe DEVICE AND COMPUTING SYSTEM INCLUDING THE SAME
JP2007018403A (en) Register compatible with different interface
TW201709707A (en) Method for enhancing PCIe compatibility