TW201709707A - Method for enhancing PCIe compatibility - Google Patents

Abstract

The present invention provides a method for enhancing Peripheral Component Interconnect Express (PCIe) compatibility. To carry out the present invention, it needs to firstly disposed a memory and a repeater on a PCIe device for storing a plurality of setting parameters; therefore, when a X86 system having the PCIe device is booted, BIOS would automatically look up corresponding setting parameters from the memory and then write the parameters into repeater after confirming the type of the PCIe device. Therefore, the repeater is able to enhance the signal transmission strength between the X86 system CPU and the PCIe device according to different PCIe specifications.

Description

Method for improving the compatibility of the standard architecture of the fast peripheral interconnection

The present invention relates to the technical field of server systems, and more particularly to a method for compatibility of a standard architecture of a fast peripheral interconnect, which method can be applied to a server system having multiple PCI e slots.

Intel Corporation-led 3GIO (Th ird Ge neration I / OArchitecture), combined with a number of companies to form PCI - SIG (PCI S pecial I nteres tGr oup), and proposed a fast peripheral interconnection standard (PCI Ex press, PCI -E / The PCI e) architecture replaces the prior art.

Currently, PCIe technology is widely used in servers. Please refer to FIG. 1 , which is a structural diagram of a conventional server. As shown in FIG. 1 , the conventional server 1 ′ mainly includes: a casing 11 ′, a motherboard 12 ′, a plurality of Ethernet communication module boards 13 ′, a plurality of hard disks 14 ′, and a plurality of a cooling fan 15', at least one control and display module 16'; wherein the Ethernet communication module board 13' is designed based on a PCIe technology architecture and communicates with the motherboard 12 through an intermediate interface board 17' 'Achieve a communication connection.

PCIe introduces a switch peer-to-peer sequence transmission technique that transmits signals through differential signal pairs called lanes. PCIe allows each Ethernet communication module board 13' to establish an independent data transmission channel without having to request bandwidth from the entire system, thereby increasing the data transmission rate. PCIe's serial connection method can greatly reduce the signal interference and electromagnetic interference between cables, and the number of transmission cables is reduced compared with the parallel connection mode, which saves space.

In the technical architecture of PCIe, a set of channels includes a transmitter and a receiver, and the transmission bandwidth is 250 MB/s in the simplex mode. The specification of a group of channels is called PCIe x1, and PCIe can increase the bandwidth by increasing the number of channels, such as x1, x2, x4, x8, x16, x32, etc., and the length of each PCIe interface is different, PCIe x1 is the shortest. The rest grows in turn. With 16 channels of PCIe x16, it has a 4GB/s bandwidth for simplex operation and nearly double the AGP 8X's 2.1GB/s bandwidth.

However, as shown in Figure 1, the technical architecture of PCIe has strict rules for the signal transmission distance d' (Trace Length) between the transmitting end and the receiving end. Here, the transmitting end refers to the CPU 121', and the receiving end refers to the PCIe device (i.e., the Ethernet communication module board 13'). According to Intel's specifications, PCIe's signal transmission distance d' cannot exceed 13.5 inches. Such regulations are very difficult to achieve for PCIe x8, PCIe x16, and PCIe x32 with relatively long interfaces. In order to solve the above problem, the server manufacturer sets a repeater on the PCIe device (that is, the Ethernet communication module board 13'), and the repeater is disposed on the transmitting end and the receiving end. Between, to enhance the strength of signal transmission.

Although setting up a repeater can solve the problem of insufficient signal transmission strength between the transmitting end and the receiving end, it has a new problem:

(1) According to the PCIe specification of the different Ethernet communication module board 13', the server manufacturer must write the corresponding parameter setting value in the repeater. However, in general, the server 1' provided by the server manufacturer allows the user to replace the Ethernet communication module board 13', and the Ethernet communication module board 13 replaced by the user. The PCIe specification cannot correspond to the parameter setting value written in the repeater, which may cause the server 1' to be unable to drive the Ethernet communication module board 13'.

(2) In view of the above problem (1), the user usually sends the server 1' back to the server manufacturer, and the server manufacturer assists in replacing the parameter settings in the repeater; however, This way not only takes time and effort, but also delays the normal operation of the user.

In view of the above reasons, the most important issue for server manufacturers is how to consider the transmission distance (Trace Length) while providing users with the ability to replace the Ethernet interface module 13' of different PCIe specifications. ), and then develop a highly applicable, adaptable server product. Therefore, the inventor of the present invention tried to study the invention and finally developed a method for improving the compatibility of the standard architecture of the fast peripheral interconnection of the present invention.

The main purpose of the present invention is to provide a method for improving the compatibility of the standard architecture of the fast peripheral interconnection, which is to store the complex array parameter setting value in a memory on the fast peripheral interconnection standard architecture device (PCI edevice). In this way, when the X8 6 system device is powered on, the BIOS only needs to confirm the specification of the fast peripheral interconnect standard architecture device (PCI edevice), and write the parameter setting value after the memory queries the corresponding parameter setting value. Into the repeater; thus, the repeater can interconnect the standard architecture module according to different specifications of the fast peripherals, thereby enhancing the central processor between the X8 6 system device and the standard peripheral module of the fast peripheral interconnection Signal transmission strength.

In order to achieve the above-mentioned primary object of the present invention, the inventor of the present invention provides a method for improving compatibility of a standard architecture of a fast peripheral interconnection, the method comprising the following steps: Step (1): providing a repeater and a The memory and the memory are disposed on a plurality of PCI Express devices (PCIe devices); wherein the memory stores complex array parameters. Step (2): starting an X86 system device and confirming a status flag of one of the repeaters (Register) through a basic input/output system (BIOS) of the X86 system device ( Whether flag has been changed; if yes, step (5) is performed; if not, the basic input/output system then performs step (3). Step (3): confirming the specifications of the plurality of shortcut peripheral interconnection standard architecture modules, and further finding a corresponding plurality of parameter setting values from the complex array parameters stored in the memory. Step (4): writing the plurality of parameter setting values into the register, and repeating the above step (2). Step (5): Enter one of the operating systems (OS) of the X86 system device.

In order to more clearly describe a method for improving the compatibility of the standard architecture of the fast peripheral interconnection proposed by the present invention, a preferred embodiment of the present invention will be described in detail below with reference to the drawings.

Since the method of the present invention is applied to an X86 system device, such as an industrial computer or a server, a simple block diagram of the X86 system device must first be introduced. As shown in the simplified block diagram of the X86 system device shown in FIG. 2, the central processing unit 12 and the Basic Input/Output System (BIOS) are disposed on the motherboard 11 of the X86 system device 1. . Moreover, a plurality of PCI Express devices (PCIe devices) are electrically connected to the central processing unit 12. In particular, a repeater 2 and a memory 3 are disposed on the plurality of shortcut peripheral interconnect standard architecture modules 4, and the repeater 2 is connected to the plurality of shortcut peripheral interconnections. The standard architecture module 4 and the central processing unit 12 are used to enhance the strength of signal transmission between the two.

Here, it must be additionally noted that since the present invention does not limit the type of the X86 system device 1, the type of the fast peripheral interconnection standard architecture device 4 is also not limited. In a typical application, the fast peripheral interconnect standard architecture device 4 can be an Ethernet communication module, a video drive processor module, an audio drive processor module, a sensor module, or a memory read/ Write the processor module.

Continuing, please refer to FIG. 3, which is a flow chart of the steps of a method for improving the compatibility of the standard architecture of the fast peripheral interconnection. As shown in FIG. 3, the method of the present invention first performs the step (S1): providing a repeater 2 and a memory 3, and setting the repeater 2 and the memory 3 to a plurality of shortcut peripherals. The standard architecture module 4 is above; wherein the memory 3 can be a flash memory or an electrically erasable EEPROM (Electrically-Erasable Programmable Read-Only Memory (EEPROM)), wherein the memory array is stored in a complex array. parameter. In addition, although FIG. 2 illustrates the repeater 2 and the memory 3 being two wafers independent of each other, it should not be construed as a technical limitation. It is known that the repeater 2 and the memory 3 can be integrated into a single wafer through an integrated circuit design.

After the step (S1) is completed, the step (S2) is subsequently performed: the X86 system device 1 is activated, and a register of the repeater 2 is confirmed by the basic input/output system chip 13 of the X86 system device 1. Whether a state flag has been changed. If the status flag has not been changed, the method proceeds to step (S3) and step (S4): confirming the specifications of the plurality of shortcut peripheral interconnect standard architecture modules 4, and further storing the complex array from the memory 3. Among the parameters, a corresponding plurality of parameter setting values are found, thereby writing the plurality of parameter setting values into the register 21, and repeating the above step (2).

As described above, the status flag of the register 21 has not been changed, indicating that the parameter setting value written in the register 21 may not accurately correspond to the standard peripheral architecture module 4 of the X86 system device 1. Therefore, after confirming the specifications of the shortcut peripheral interconnect standard architecture module 4, the corresponding parameter setting values must be written into the temporary memory device 21; thus, the repeater 2 can be configured according to different specifications. The fast peripheral interconnect standard architecture module 4 further enhances the signal transmission strength between the central processing unit 12 of the X86 system device 1 and the fast peripheral interconnect standard architecture module 4. It is well known to the system engineer that when the status flag is changed, the status flag bit of the register 21 is normally 0; conversely, the status flag of the register 21 after the status flag has been changed. The bit is 1. However, the above manner of setting the status flag bit to 0 or 1 is not particularly limited. In a possible application, the status flag bit of the register 21 may also be 0 after the status flag has been changed.

Moreover, when the result of the determination in the above step (S2) is NO, it indicates that the state flag of the register 21 has been changed, so that the parameter setting value in the register 21 can accurately correspond to the X86 system device 1 The fast peripheral interconnection standard architecture module 4; in such a situation, there is no need to write any data to the temporary memory device 21, and the step (S5) can be directly executed: enter the operating system of the X86 system device 1 ( Operation System, OS). Of course, after the parameter value setting inside the register 21 is completed by the steps (S1) to (S4), the method flow is also followed by the step (S5).

In this case, it must be additionally stated that when the system method cannot confirm the specifications of the plurality of shortcut peripheral interconnection standard architecture modules 4 through the step (S3), the system method continues to perform the step (S4a): at least one group The default parameter setting value is written into the register 21, and the repeater 2 can set the value according to the preset parameter, thereby enhancing the central processing unit 12 of the X86 system device 1 and The fast peripheral interconnects the signal transmission strength between the standard architecture modules 4.

Thus, the inventors have completely and clearly disclosed a method for improving the compatibility of the standard architecture of the fast peripheral interconnection of the present invention; in general, the method of the present invention has the following advantages:

(1) The present invention pre-stores the complex array parameter setting value in a memory 3 above the PCIe device 4; thus, when the X86 system device 1 is powered on, the BIOS As long as the specification of the PCIe device 4 is confirmed, and the memory 3 queries the corresponding parameter setting value, the parameter setting value is written into the repeater 2; thus, the repeater 2, the standard architecture module 4 can be interconnected according to different specifications of the fast peripherals, thereby enhancing the signal transmission strength between the central processing unit 12 of the X86 system device 1 and the standard peripheral architecture module 4 of the fast peripherals.

(2) According to the above first point, once the method of the present invention is applied to the X86 system device 1 (for example, a server system), the user can replace the Ethernet communication module board of different PCIe specifications by himself. There is no need to consider whether the Ethernet communication module board of different PCIe specifications has the adaptability of the signal transmission distance.

It is to be understood that the foregoing detailed description of the embodiments of the present invention is not intended to Both should be included in the scope of the patent in this case.

<present invention>
S1~S5‧‧‧ method steps
1‧‧‧X86 system installation
11‧‧‧ Motherboard
12‧‧‧Central processor
13‧‧‧Basic Input and Output System Wafer
4‧‧‧Quick Peripheral Interconnect Standard Architecture Module
2‧‧‧Repeat
3‧‧‧ memory
21‧‧‧Scratch

<知知>
1'‧‧‧Server
11'‧‧‧Shell
12'‧‧‧ Motherboard
13'‧‧‧Ethernet communication module board
14'‧‧‧ hard disk
15'‧‧‧ cooling fan
16'‧‧‧Control and display module
D'‧‧‧ signal transmission distance
17'‧‧‧Intermediate interface board
121'‧‧‧CPU

1 is a block diagram showing a conventional server; FIG. 2 is a simplified block diagram showing an X86 system device; and FIG. 3 is a flow chart showing a method for improving the compatibility of the standard architecture of the fast peripheral interconnection according to the present invention. Figure.

S1~S5‧‧‧ method steps

Claims (7)

A method for improving compatibility of a standard architecture of a fast peripheral interconnection includes the following steps: (1) providing a repeater and a memory, and interconnecting the repeater and the memory in a plurality of shortcut peripherals Above the PCI Express Device (PCIe device); wherein the memory stores a complex array parameter; (2) starting an X86 system device and passing through a basic input/output system of the X86 system device ( Basic Input/Output System, BIOS) confirms whether a status flag of one of the repeaters of the repeater has been changed; if yes, step (5) is performed; if not, the basic input/output system then performs step (3) (3) confirming the specifications of the plurality of shortcut peripheral interconnect standard architecture modules, and further finding a corresponding plurality of parameter setting values from the complex array parameters stored in the memory; (4) the plural number The parameter setting values are written into the register, and the above steps (2) are repeated; and (5) enters one of the operating systems of the X86 system device. The method for improving the compatibility of the standard architecture of the fast peripheral interconnection, as described in claim 1, wherein the memory may be any of the following: a flash memory or an electronic erasable rewritable read-only memory ( Electrically-Erasable Programmable Read-Only Memory, EEPROM). The method for improving the compatibility of the standard architecture of the fast peripheral interconnection, as described in claim 1, wherein the repeater and the memory can be integrated into a single chip. The method for improving the compatibility of the standard architecture of the fast peripheral interconnection, as described in claim 1, wherein the X86 system device can be any of the following: an industrial computer or a server. For example, in the method of claim 1, the method for improving the compatibility of the standard architecture of the fast peripheral interconnection, wherein the standard device of the fast peripheral interconnection may be any one of the following: an Ethernet communication module, a video driver A processor module, an audio drive processor module, a sensor module, or a memory read/write processor module. A method for improving the compatibility of a standard architecture of a fast peripheral interconnection, as described in claim 1, wherein in the step (2), after the status flag has been changed, one of the registers is in a state The flag bit is 1. A method for improving the compatibility of a standard architecture of a fast peripheral interconnection, as described in claim 3, wherein in the step (2), after the status flag has been changed, one of the registers is in a state The flag bit is 0.