CN114546890A - System-level space read-write verification method, system, storage medium and equipment - Google Patents
System-level space read-write verification method, system, storage medium and equipment Download PDFInfo
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Abstract
The invention provides a system-level space read-write verification method, a system, a storage medium and equipment. When a bus initiates a write operation for a certain address, the subsequent conversion module maps the address and data sent by the bus to each block memory according to the generated address mapping table, and initiates the write operation for the same offset address of a plurality of block memories. In order to improve the efficiency, the memory space is partitioned, an address mapping table is generated according to the partitioned blocks, and a newly-added conversion module can simultaneously send read-write operations sent by an AMBA bus to each block of memory according to the address mapping table, so that the aim of simultaneously operating a plurality of addresses by sending one bus operation is fulfilled, and the efficiency is improved in multiples.
Description
Technical Field
The invention relates to the technical field of computers, in particular to the technical field of chip development, and specifically relates to the technical field of register read-write verification.
Background
In the chip development process, the read-write inspection of the register is a more critical step in the initial stage of verification. The register test case is generated by utilizing a self-developed automation tool, and the register under a real scene is tested according to the actual address mapping table, so that whether the operation of each register is correct or not is checked. In addition, when accessing a register, an AMBA (Advanced Microcontroller Bus Architecture) Bus is usually used to initiate read and write operations, but the Bus can only perform read and write accesses to one address at a time. For a larger address space, the bus can only access addresses sequentially. This results in a longer time spent accessing addresses by the bus, which affects the efficiency of the simulation.
However, in an actual SoC (System on Chip) level application scenario, some modules occupy a larger register address space or define a larger storage space, and the above-mentioned register test case is to cyclically read and write the register, which takes a longer simulation time. Meanwhile, at a complex SoC level, the interconnection bus module is mainly used for interconnection among all IPs, generally comprises an input logic part, an address decoding part, a bus arbitration part and an output logic part, and can complete functions of data stream exchange, address allocation, priority determination of shared resources and the like. The module is used as an interface module between IPs, is a necessary channel of data flow, and is also a key point of verification. When accessing the memory, it is first necessary to check whether the decoding logic is correct. In addition, the SoC level also has related test for the clock domain with low power consumption. The memory operation mode will be different in different scenes. Therefore, at the system level, how to quickly cover the address space for the larger address space becomes a key problem to be solved.
It can be said that, for some modules occupying large addresses, the test will result in long time consumption, and further result in low test efficiency, and even delay the development progress of the whole chip.
Therefore, in order to overcome the above drawbacks and problems in the prior art, it is necessary to provide a method for performing read-write verification on how quickly an address space is covered for a larger address space, so as to reduce time consumption and improve test efficiency.
Disclosure of Invention
In view of the above, an object of the present invention is to provide an improved method, system, storage medium and device for system level space read-write verification, especially for large address space, so as to solve the problems in the prior art that the test consumes a long time, and thus the test efficiency is low, and even the development progress of the whole chip is delayed.
Based on the above objects, in one aspect, the present invention provides a system-level space read-write verification method, wherein the method comprises the following steps:
according to the space size of an actual memory, performing virtual partitioning processing on a large memory address space to obtain a plurality of small memories, and forming an address mapping table according to the addresses of the small memories;
generating register models and test cases of all modules by using a register model generation tool, and sequentially performing read-write inspection on each register in the test cases, wherein only the internal memory offset address of each module is subjected to write access in the test cases;
responding to the read-write operation of the memory initiated through the address bus according to the test case, addressing through the address decoding logic and initiating a transmission request;
simultaneously executing read-write operation on a plurality of addresses through a conversion module based on an address mapping table;
after the write operation is executed, the read operation is simultaneously initiated aiming at each small block memory, and the data read from the corresponding offset address of each small block memory is collected so as to check the correctness of the write data and the address decoding.
In some embodiments of the method for system level space read-write verification according to the present invention, after performing the write operation, simultaneously initiating a read operation for each of the small blocks of memory, and collecting data read at a corresponding offset address of each of the small blocks of memory to check correctness of the write data and the address decoding further comprises:
and reading the write data on the corresponding offset address of each small block memory by using a back-gate reading mode so as to check the correctness of the write data and the address decoding.
In some embodiments of the method for system level space read-write verification according to the present invention, after performing the write operation, simultaneously initiating a read operation for each of the small blocks of memory, and collecting data read at a corresponding offset address of each of the small blocks of memory to check correctness of the write data and the address decoding further comprises:
verifying that the written data and the address decoding are correct in response to the fact that the data read by the back door is the same as the data written through the address bus;
in response to the back gate reading data being different from the data written via the address bus, the written data and/or address decode error is verified.
In some embodiments of the method for system level space read-write verification according to the present invention, after performing the write operation, simultaneously initiating a read operation for each of the small blocks of memory, and collecting data read at a corresponding offset address of each of the small blocks of memory to check correctness of the write data and the address decoding further comprises:
and reading the write data at any correct address by using a front door reading mode so as to check the correctness of the write data.
In some embodiments of the method for system level space read-write verification according to the invention, performing read-write operations on multiple addresses simultaneously based on an address mapping table further comprises:
and simultaneously sending the addresses sent by the bus to the corresponding small block memories through address mapping, and simultaneously sending data to the corresponding small block memories according to the address mapping.
In some embodiments of the method for verifying system-level space read-write according to the present invention, the virtually blocking a large block of memory address space according to the size of the space of the actual memory to obtain a plurality of small blocks of memory, and forming an address mapping table according to the addresses of the plurality of small blocks of memory further includes:
dividing a large memory address space into a plurality of small memories equally according to the space size of the actual memory, and determining the base address of each small memory according to the number of the divided small memories and the divided memory units.
In some embodiments of the method for system level space read-write verification according to the present invention, in response to initiating a read-write operation to a memory through an address bus according to a test case, addressing through address decode logic and initiating a transmission request further comprises:
when initiating bus operation, firstly checking address decoding, checking whether the address sent by decoding logic is correct according to an actual chip address mapping table, and simultaneously checking whether the sent address meets the requirement of blocking.
In another aspect of the present invention, a system for system-level space read-write verification is further provided, where the system includes:
the memory virtual partition module is configured to perform virtual partition processing on a large memory address space according to the space size of an actual memory to obtain a plurality of small memories, and form an address mapping table according to the addresses of the small memories;
the test case generation module is configured to generate register models and test cases of all the modules by using a register model generation tool, wherein each register is sequentially subjected to read-write inspection in the test cases, and only the internal memory offset address of each register is subjected to write access in the test cases;
the read-write test initiating module is configured to respond to the read-write operation initiated to the memory through the address bus according to the test case, perform addressing through the address decoding logic and initiate a transmission request;
the read-write operation conversion module is configured to simultaneously execute read-write operation on a plurality of addresses through the conversion module based on an address mapping table;
and the data address verification module is configured to simultaneously initiate a read operation aiming at each small block memory after the write operation is executed, and collect data read from corresponding offset addresses of each small block memory so as to check the correctness of the written data and address decoding.
In still another aspect of the present invention, a computer-readable storage medium is further provided, which stores computer program instructions, and when the computer program instructions are executed, the method for performing the system level space read-write verification according to any one of the above embodiments is implemented.
In yet another aspect of the present invention, a computer device is further provided, which includes a memory and a processor, the memory stores a computer program, and the computer program is executed by the processor to execute any of the above methods for system level space read-write verification according to the present invention.
The invention has at least the following beneficial technical effects: based on the method of the invention, especially aiming at the problem that the test of some modules occupying larger addresses can lead to longer time consumption, the method provides that the larger memory is flexibly processed in a blocking way, when the write operation of an address is sent through a bus, the operation of the address can be simultaneously sent to the small partitioned memories through the intermediate conversion module, so as to achieve the purpose of simultaneously operating a plurality of addresses by sending one bus operation, and improve the efficiency in multiples.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
In the figure:
FIG. 1 shows a schematic flow diagram of an embodiment of a method of system level spatial read-write verification according to the invention;
FIG. 2 is a schematic diagram of memory partitioning according to an embodiment of a system level space read-write verification method of the present invention;
FIG. 3 shows a schematic block diagram of an embodiment of a method of system level spatial read-write verification according to the present invention;
FIG. 4 is a schematic diagram of address mapping according to an embodiment of a method of system level spatial read-write verification of the present invention;
FIG. 5 shows a schematic diagram of a conversion module of an embodiment of a method of system level spatial read-write verification according to the invention;
FIG. 6 shows a schematic block diagram of an embodiment of a system for system level spatial read-write verification in accordance with the present invention;
FIG. 7 shows a schematic diagram of an embodiment of a computer-readable storage medium implementing a method for system level spatial read-write verification in accordance with the present invention;
fig. 8 shows a hardware structure diagram of an embodiment of a computer device implementing a method for system level space read-write verification according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two non-identical entities with the same name or different parameters, and it is understood that "first" and "second" are only used for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements does not include all of the other steps or elements inherent in the list.
Briefly, the inventive concept is particularly directed to the case where system level module registers occupy a large address space. According to the invention, a larger memory space is divided into a plurality of memory blocks with the same memory size according to the actual situation, and the corresponding address mapping table is generated according to the divided memory blocks. When a bus initiates a write operation for a certain address, the subsequent conversion module maps the address and data sent by the bus to each block memory according to the generated address mapping table, and initiates the write operation for the same offset address of a plurality of block memories. Different from the conventional method for sequentially reading and writing each register in the register test, the method can simultaneously write all the memory blocks according to the address mapping when initiating the bus operation by dividing the plurality of memory blocks. Meanwhile, the back door can be used for reading and writing data and checking whether the data and address decoding is correct or not. Fig. 1 shows a schematic flow diagram of an embodiment of a method for system level spatial read-write verification according to the present invention.
Typically, register testing is checked sequentially in register address order, both in module level and system level verification. When the module register occupies a large address space at the system level, it takes a long simulation time if the test is performed according to the conventional register test method. In order to improve the efficiency, the memory space is partitioned, an address mapping table is generated according to the partitioned blocks, and a newly-added conversion module can simultaneously send read-write operations sent by an AMBA bus to each block of memory according to the address mapping table, so that the aim of simultaneously operating a plurality of addresses by sending one bus operation is fulfilled, and the efficiency is improved in multiples. Fig. 2 is a schematic diagram illustrating memory partitioning according to an embodiment of the system level space read-write verification method of the present invention.
To this end, in a first aspect of the present invention, a method 100 for system-level spatial read-write verification is provided. Fig. 3 shows a schematic block diagram of an embodiment of a method of system level spatial read-write verification according to the present invention. In an embodiment as shown in fig. 3, the method comprises:
step S110: according to the space size of an actual memory, carrying out virtual partitioning processing on a large memory address space to obtain a plurality of small memories, and forming an address mapping table according to the addresses of the small memories;
step S120: generating register models and test cases of all modules by using a register model generation tool, and sequentially performing read-write inspection on each register in the test cases, wherein only the internal memory offset address of each module is subjected to write access in the test cases;
step S130: responding to the read-write operation of the memory initiated through the address bus according to the test case, addressing through the address decoding logic and initiating a transmission request;
step S140: simultaneously executing the read-write operation on a plurality of addresses through a conversion module based on the address mapping table;
step S150: after the write operation is executed, the read operation is simultaneously initiated aiming at each small block memory, and the data read from the corresponding offset address of each small block memory is collected so as to check the correctness of the write data and the address decoding.
In summary, aiming at the above problems in the prior art, the basic idea of the present invention is to perform a block processing on a larger memory, appropriately divide a plurality of block memories with the same memory size according to the actual memory space size, and generate a corresponding address mapping table. Therefore, in step S110, a large block of memory address space is virtually partitioned according to the size of the real memory space to obtain a plurality of small blocks of memory, and an address mapping table is formed according to the addresses of the small blocks of memory. FIG. 4 is a schematic diagram of address mapping according to an embodiment of the method for system level spatial read-write verification of the present invention.
Subsequently, in step S120, a register model automatic generation tool is used to generate register models and test cases of all modules, and the test cases sequentially perform read-write inspection on each register. After the memory blocks are divided, only the memory offset addresses of the memory blocks need to be accessed by writing in the test case. The bus write operation is initiated only to the offset address of the general small memory block, and the following conversion module initiates write access to each small memory block according to the base address of the block memory block
On this basis, when the read-write operation to the memory is initiated through the address bus according to the test case, the addressing is performed through the address decoding logic and the transmission request is initiated in step S130. The address decoding logic directs the input binary address to the corresponding physical space. When a CPU initiates read-write operation on a memory through an address bus, the CPU needs to find a corresponding address through address decoding logic and then initiates a transmission request. When initiating a bus operation, a check is first made for address decoding. And checking whether the address sent by the decoding logic is correct according to an actual chip address mapping table, and simultaneously checking whether the sent address meets the blocking requirement.
Then, in step S140, the read/write operation is performed on a plurality of addresses simultaneously by the translation module based on the address mapping table. After passing through the address decoding logic, the real read-write operation is initiated, and according to the actual situation, the read-write operation can be divided into the following two situations. And simultaneously initiating write operation and simultaneously reading operation to check data, and initiating simultaneous write operation and simultaneously reading operation to check data validity when only one memory is valid. FIG. 5 shows a schematic diagram of a conversion module according to an embodiment of the method of system level space read-write verification of the present invention. When the memory is operated by the bus, the address and the data are corresponding to each block of memory through the generated address mapping table, and the corresponding offset address of each block of memory can be written at the same time.
Finally, in step S150, after the write operation is performed, a read operation is simultaneously initiated for each small block of memory, and the data read at the corresponding offset address of each small block of memory is collected to check the correctness of the write data and the address decoding.
In some embodiments, a flow chart of a method for performing system level space read/write verification for fast address overlay for a system level larger memory space according to the present invention is shown in fig. 1. The purchasing machine of the method is based on the following points: the test system comprises a register test case, an AMBA bus, a conversion module and a partitioned memory. The process of the method according to the invention is described in further detail below.
1) Partitioning a larger memory space
In a real chip, some modules take a lot of time when accessing registers because of large address space occupied by functions. In order to improve the access efficiency, virtual blocking processing can be performed on a large block of memory address space.
For example, as shown in fig. 2, a 12KB address space is taken as an example, and is divided into 3 small blocks of memories with 4KB as a unit, the offset address (offset address) range of each 4KB small block of memories is 32 'h 00000000-32' h00000FFF, and the base address (base address) is different.
2) Obtaining an address mapping table from a block memory address
According to the above memory division, a corresponding address mapping table can be obtained, as shown in fig. 4. Each block memory is divided into 4KB address space, the first block memory address space is 32 'h 0-32' hFFF, the second block memory address space is 32 'h 1000+ 0-32' h1000+32 'hFFF, and the third block memory address space is 32' h2000+ 0-32 'h 2000+ 32' hFFF. The offset address range of each small block memory is 32 'h 0-32' hFFF, the base address is obtained according to the number of the divided memory blocks and the divided memory units, the base address of the block 1 memory is 0, the base address of the block 2 memory is 0+32 'h 1000, and the base address of the block 3 memory is 0+2 x 32' h 1000.
By analogy, when the memory cells are divided more finely or a larger address space is encountered, assuming that the memory size needs to be divided into mMB, the (m/n) × 210 blocks of memory need to be divided according to nKB as a unit of divided memory. The memory offset address in each block is 0 to nKB, and the a-th block memory base address is 0+ (a-1) × nKB (0< a ═ m/n) × 210). The division of the memory unit can be flexibly selected according to the size of the memory.
Therefore, in some embodiments of the method 100 for verifying system-level space read-write according to the present invention, the step S110 performs virtual block processing on a large memory address space according to the size of the space of the actual memory to obtain a plurality of small memories, and forms an address mapping table according to the addresses of the plurality of small memories further includes: dividing a large memory address space into a plurality of small memories equally according to the space size of the actual memory, and determining the base address of each small memory according to the number of the divided small memories and the divided memory units.
3) Generating register test cases
And generating register models and test cases of all modules by using an automatic register model generation tool, and sequentially performing read-write inspection on each register in the test cases. After the memory blocks are divided, only the offset addresses of the partitioned memories need to be subjected to write access in a test case.
A bus write operation is initiated only to the general block memory offset address, followed by a translation module that initiates a write access to each block memory simultaneously based on the block memory base address.
4) Logical addressing by address decoding
The address decoding logic directs the input binary address to the corresponding physical space. When a CPU initiates read-write operation on a memory through an address bus, the CPU needs to find a corresponding address through address decoding logic and then initiates a transmission request. When initiating a bus operation, a check is first made for address decoding. And checking whether the address sent by the decoding logic is correct according to an actual chip address mapping table, and simultaneously checking whether the sent address meets the blocking requirement.
To this end, in some embodiments of the method 100 for system level space read-write verification according to the present invention, the step S130, in response to initiating a read-write operation on a memory through an address bus according to the test case, addressing through address decoding logic and initiating a transmission request further includes: when initiating bus operation, firstly checking address decoding, checking whether the address sent by decoding logic is correct according to an actual chip address mapping table, and simultaneously checking whether the sent address meets the requirement of blocking.
5) Initiating operation of an address mapping table for multiple addresses simultaneously
After passing through the address decoding logic, the real read-write operation is initiated, and according to the actual situation, the read-write operation can be divided into the following two situations. And simultaneously initiating write operation, simultaneously reading operation and checking data, and initiating simultaneous write operation and simultaneously reading operation and checking data validity when only one memory is valid.
That is, in some embodiments of the method 100 for system level space read-write verification according to the present invention, the step S140 of performing the read-write operation on a plurality of addresses simultaneously based on the address mapping table further comprises: and simultaneously sending the address sent by the bus to the corresponding small block memories through address mapping, and simultaneously sending data to the corresponding small block memories according to the address mapping. Wherein the reading and writing process can be divided into two cases below.
(1) Simultaneous writing and reading
After passing through the address decoding logic, the address space is judged to be capable of being divided into a plurality of small blocks of memories to carry out read-write operation. As can be seen from fig. 1, the register test sequence is initiated and the corresponding address is operated on via the AMBA bus. In general, a bus performs data read-write operation only on one address, and when a large address space is accessed, each address needs to initiate the bus to perform read-write operation, which results in long simulation time. In order to solve this problem, it is considered to add a conversion module behind the bus module to implement the parallel access function to the larger memory. A schematic diagram of the conversion module is shown in fig. 5.
When the AMBA bus initiates write operation aiming at the register, the address and the data can pass through the conversion module, the address sent by the AMBA bus can be simultaneously sent to the divided block memories through the address mapping module, and the sent data is also simultaneously sent to each block memory according to the mapping. Therefore, after passing through the conversion module, each time a write operation is sent through the AMBA bus, which is equivalent to simultaneously writing to the same offset address in a plurality of blocks, so that the access efficiency can be improved by times.
In order to check the correctness of the written data, the read operation can be simultaneously initiated for each block memory, the data on the corresponding offset address of each block memory is collected through the read operation monitoring module, and the written data of the front door is checked through a front door reading mode. The correct address data can be optionally output to the AMBA bus via the output selection module.
Therefore, in some embodiments of the method 100 for system level space read-write verification according to the present invention, the step S150, after performing the write operation, simultaneously initiating a read operation for each of the small blocks of memory, and collecting data read at a corresponding offset address of each of the small blocks of memory, so as to check correctness of the write data and address decoding further includes: and reading the write data at any correct address by using a front door reading mode so as to check the correctness of the write data.
(2) Write to one block of memory and read simultaneously
When a plurality of memory blocks have different base addresses and the same offset address, simultaneous read and write operations can be performed on the memory blocks. For example, 3 LMU modules with different base addresses and the same memory space store data, and when write operation is performed on any LMU memory, the write operation of the other two memories is invalid. When the AMBA bus initiates write operation to any LMU memory, the data is written into 3 LMU memories simultaneously through the write conversion module. And utilizing the read conversion module to initiate simultaneous read operation on each block memory so as to check the correctness of the written data. In this case, when the simultaneous write operation is initiated, only one memory block has valid write data, and the other memory blocks have invalid write data. In order to check whether the written address and the data are correct, a simultaneous read operation is initiated for each internal memory, the data on the same offset address of each internal memory is read out, the read address and the read data are compared with the written address and the written data, when the written data and the read data are the same, the access of the internal memory block is indicated to be valid at the moment, and the read address and the read data are output to an external AMBA bus through a selection module. And the writing operation of the rest invalid memory blocks is invalid, and the read data is different from the written data. The memory block validity can be checked using a concurrent read and write operation.
The read operation for the register can be realized in two other ways, one is to check the write data by using combinational logic, and the other is to check the write data by using a back-gate read mode. When the combinational logic is used for checking, the data which are simultaneously written into the offset addresses of all the memory blocks are subjected to AND operation, if the result is the same as the data written by the bus, the data check is correct, and if the result is not the same as the data written by the bus, the data check is wrong. And reading the write data on the offset address corresponding to each memory block by using a back door reading mode, checking the correctness if the back door read data is equal to the bus write data, and otherwise, checking the error. The read data of the back door can not only compare whether the written data is correct, but also check whether the address decoding is correct according to the access path of the back door.
Therefore, in some embodiments of the method 100 for system level space read-write verification according to the present invention, the step S150, after performing the write operation, simultaneously initiating a read operation for each of the small blocks of memory, and collecting data read at a corresponding offset address of each of the small blocks of memory, so as to check correctness of the write data and address decoding further includes: and reading the write data on the corresponding offset address of each small block memory by using a back-gate reading mode so as to check the correctness of the write data and the address decoding.
Furthermore, in some embodiments of the method 100 for verifying system-level space read-write according to the present invention, the step S150, after performing the write operation, simultaneously initiating a read operation for each small block memory, and collecting data read at a corresponding offset address of each small block memory to check correctness of the write data and the address decoding, and further, reading the write data at the corresponding offset address of each small block memory by using a back-gate read method to check correctness of the write data and the address decoding further includes: verifying that the written data and the address decoding are correct in response to the fact that the data read by the back door is the same as the data written through the address bus; in response to the back gate reading data that is not the same as the data written via the address bus, a write data and/or address decode error is verified.
In summary, according to the foregoing embodiments of the present invention, in an actual chip, the read/write operations for the register and the memory space are initiated by the CPU. The random read-write operation of the register is achieved by using a bus VIP (authentication IP) to replace a CPU in an SoC-level authentication platform. But for some modules that occupy a large address, the test can be time consuming. Aiming at the problems, the invention provides a method for flexibly partitioning a larger memory, and when a write operation of an address is sent through a bus, the operation of the address can be simultaneously sent to the partitioned small memories through an intermediate conversion module so as to improve the test efficiency.
In a second aspect of the present invention, a system 200 for system-level space read-write verification is also provided. FIG. 6 shows a schematic block diagram of an embodiment of a system 200 for system level spatial read-write verification in accordance with the present invention. As shown in fig. 6, the system includes:
a memory virtual partition module 210, where the memory virtual partition module 210 is configured to perform virtual partitioning on a large memory address space according to the size of the space of an actual memory to obtain a plurality of small memories, and form an address mapping table according to the addresses of the small memories;
a test case generation module 220, wherein the test case generation module 220 is configured to generate register models and test cases of all modules by using a register model generation tool, and the test cases sequentially perform read-write inspection on each register, wherein only write access is performed on internal memory offset addresses of the modules in the test cases;
a read-write test initiating module 230, where the read-write test initiating module 230 is configured to respond to initiating a read-write operation on the memory through the address bus according to the test case, perform addressing through the address decoding logic, and initiate a transmission request;
a read-write operation conversion module 240, wherein the read-write operation conversion module 240 is configured to perform read-write operations on a plurality of addresses simultaneously through the conversion module based on the address mapping table;
a data address verification module 250, wherein the data address verification module 250 is configured to initiate a read operation for each small block memory at the same time after the write operation is performed, and collect data read at a corresponding offset address of each small block memory to check correctness of the written data and address decoding.
In a third aspect of the embodiment of the present invention, a computer-readable storage medium is further provided, and fig. 7 is a schematic diagram of a computer-readable storage medium of a method for performing system-level space read-write verification according to an embodiment of the present invention. As shown in fig. 7, the computer-readable storage medium 300 stores computer program instructions 310, the computer program instructions 310 being executable by a processor. The computer program instructions 310, when executed, implement the method of any of the embodiments described above.
It should be understood that all embodiments, features and advantages set forth above with respect to the method for system level space read-write verification according to the present invention apply equally, without conflict with each other, to the system and the storage medium for system level space read-write verification according to the present invention.
In a fourth aspect of the embodiments of the present invention, there is further provided a computer device 400, comprising a memory 420 and a processor 410, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements the method of any one of the above embodiments.
Fig. 8 is a schematic hardware structure diagram of an embodiment of a computer device for performing a system-level space read-write verification method according to the present invention. Taking the computer device 400 shown in fig. 8 as an example, the computer device includes a processor 410 and a memory 420, and may further include: an input device 430 and an output device 440. The processor 410, the memory 420, the input device 430, and the output device 440 may be connected by a bus or other means, as exemplified by the bus connection in fig. 8. The input device 430 may receive input numeric or character information and generate signal inputs related to system level space read-write authentication. The output device 440 may include a display device such as a display screen.
The memory 420 is a non-volatile computer-readable storage medium, and can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the resource monitoring method in the embodiment of the present application. The memory 420 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by use of the resource monitoring method, and the like. Further, the memory 420 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 420 may optionally include memory located remotely from processor 410, which may be connected to local modules via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The processor 410 executes various functional applications of the server and data processing by executing nonvolatile software programs, instructions and modules stored in the memory 420, that is, implements the resource monitoring method of the above-described method embodiment.
Finally, it is noted that the computer-readable storage medium (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A system-level space read-write verification method is characterized by comprising the following steps:
according to the space size of an actual memory, performing virtual partitioning processing on a large memory address space to obtain a plurality of small memories, and forming an address mapping table according to the addresses of the small memories;
generating register models and test cases of all modules by using a register model generation tool, and sequentially performing read-write inspection on each register in the test cases, wherein only the internal memory offset address of each module is subjected to write access in the test cases;
responding to the read-write operation of the memory initiated through the address bus according to the test case, addressing through the address decoding logic and initiating a transmission request;
simultaneously executing the read-write operation on a plurality of addresses through a conversion module based on the address mapping table;
after the write operation is executed, the read operation is simultaneously initiated aiming at each small block memory, and the data read from the corresponding offset address of each small block memory is collected so as to check the correctness of the write data and the address decoding.
2. The method of claim 1, wherein after performing the write operation, simultaneously initiating a read operation for each of the small blocks of memory, and collecting data read at a corresponding offset address of each of the small blocks of memory to check correctness of the write data and address decoding further comprises:
and reading the write data on the corresponding offset address of each small block memory by using a back-gate reading mode so as to check the correctness of the write data and the address decoding.
3. The method of claim 2, wherein after performing the write operation, simultaneously initiating a read operation for each of the small blocks of memory, and collecting data read at a corresponding offset address of each of the small blocks of memory to check correctness of the write data and the address decoding further comprises:
verifying that the written data and the address decoding are correct in response to the fact that the data read by the back door is the same as the data written through the address bus;
in response to the back gate reading data that is not the same as the data written via the address bus, a write data and/or address decode error is verified.
4. The method of claim 1, wherein after performing the write operation, simultaneously initiating a read operation for each of the small blocks of memory, and collecting data read at a corresponding offset address of each of the small blocks of memory to check correctness of the write data and address decoding further comprises:
and reading the write data at any correct address by using a front door reading mode so as to check the correctness of the write data.
5. The method of any of claims 1 to 4, wherein the performing the read and write operations on multiple addresses simultaneously based on the address mapping table further comprises:
and simultaneously sending the addresses sent by the bus to the corresponding small block memories through address mapping, and simultaneously sending data to the corresponding small block memories according to the address mapping.
6. The method according to any one of claims 1 to 4, wherein the virtually blocking a large block of memory address space according to the size of the real memory space to obtain a plurality of small blocks of memory, and forming an address mapping table according to the addresses of the plurality of small blocks of memory further comprises:
dividing a large memory address space into a plurality of small memories equally according to the space size of the actual memory, and determining the base address of each small memory according to the number of the divided small memories and the divided memory units.
7. The method of any of claims 1 to 4, wherein the addressing and initiating a transfer request by address decode logic in response to initiating a read or write operation to a memory over an address bus according to the test case further comprises:
when initiating bus operation, firstly checking address decoding, checking whether the address sent by decoding logic is correct according to an actual chip address mapping table, and simultaneously checking whether the sent address meets the requirement of blocking.
8. A system-level spatial read-write verification system, comprising:
the memory virtual partition module is configured to perform virtual partition processing on a large memory address space according to the space size of an actual memory to obtain a plurality of small memories, and form an address mapping table according to the addresses of the small memories;
the test case generation module is configured to generate register models and test cases of all the modules by using a register model generation tool, wherein each register is sequentially subjected to read-write inspection in the test cases, and only the internal memory offset address of each register is subjected to write access in the test cases;
the read-write test initiating module is configured to respond to initiate read-write operation on the memory through an address bus according to the test case, address through address decoding logic and initiate a transmission request;
a read-write operation conversion module configured to perform the read-write operation on a plurality of addresses simultaneously through a conversion module based on the address mapping table;
and the data address verification module is configured to simultaneously initiate a read operation aiming at each small block memory after the write operation is executed, and collect data read from corresponding offset addresses of each small block memory so as to check the correctness of the written data and address decoding.
9. A computer-readable storage medium, having stored thereon computer program instructions, which when executed, implement a method of system level space read-write verification as claimed in any one of claims 1-7.
10. A computer device comprising a memory and a processor, characterized in that the memory has stored therein a computer program which, when executed by the processor, performs the method for system level spatial read-write verification according to any of claims 1-7.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115543876A (en) * | 2022-11-24 | 2022-12-30 | 北京紫光芯能科技有限公司 | Method and device for verifying address decoding function, electronic equipment and medium |
| CN115861026A (en) * | 2022-12-07 | 2023-03-28 | 格兰菲智能科技有限公司 | Data processing method and device, computer equipment and storage medium |
| CN116055243A (en) * | 2022-09-27 | 2023-05-02 | 上海创贤半导体有限公司 | Method for controlling system address mapping of power semiconductor wire bonding machine |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116055243A (en) * | 2022-09-27 | 2023-05-02 | 上海创贤半导体有限公司 | Method for controlling system address mapping of power semiconductor wire bonding machine |
| CN115543876A (en) * | 2022-11-24 | 2022-12-30 | 北京紫光芯能科技有限公司 | Method and device for verifying address decoding function, electronic equipment and medium |
| CN115861026A (en) * | 2022-12-07 | 2023-03-28 | 格兰菲智能科技有限公司 | Data processing method and device, computer equipment and storage medium |
| CN115861026B (en) * | 2022-12-07 | 2023-12-01 | 格兰菲智能科技有限公司 | Data processing method, device, computer equipment and storage medium |
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