CN116738909A - Memory integration method of integrated circuit - Google Patents
Memory integration method of integrated circuit Download PDFInfo
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- CN116738909A CN116738909A CN202310753584.9A CN202310753584A CN116738909A CN 116738909 A CN116738909 A CN 116738909A CN 202310753584 A CN202310753584 A CN 202310753584A CN 116738909 A CN116738909 A CN 116738909A
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- 230000015654 memory Effects 0.000 title claims abstract description 132
- 238000000034 method Methods 0.000 title claims abstract description 60
- 230000010354 integration Effects 0.000 title claims abstract description 24
- 238000005538 encapsulation Methods 0.000 claims abstract description 14
- 238000012795 verification Methods 0.000 claims abstract description 10
- 238000012216 screening Methods 0.000 claims description 39
- 238000004806 packaging method and process Methods 0.000 claims description 9
- 238000004088 simulation Methods 0.000 claims description 8
- 230000009191 jumping Effects 0.000 claims description 4
- 238000000354 decomposition reaction Methods 0.000 claims description 3
- 238000012858 packaging process Methods 0.000 claims description 2
- 238000001914 filtration Methods 0.000 claims 2
- 238000011161 development Methods 0.000 abstract description 5
- 238000012827 research and development Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000005587 bubbling Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000013515 script Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a Memory integration method of an integrated circuit, which comprises the following steps: establishing a general user demand table and an instantiation Memory general interface; decomposing user demands in a general user demand table, and determining a physical Memory with the smallest total area; and hierarchical encapsulation is carried out on the Memory through functional division. The method can be used for establishing the top layer of the universal Memory according to different Memory tools of a process and a provider and combining with specific Memory requirements of the project, the bottom layer is shielded, the universal top layer is conveniently and clearly called in the project, the Memory integration efficiency of the project is improved, the comprehensive use of the project in the early verification and later stage is met, and the research and development management level of the integrated circuit project is improved. The application can be applied to all chip development projects.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a Memory integration method for an integrated circuit.
Background
Memory is often used in integrated circuit designs, which are strongly related to chip technology and EDA manufacturers, and in chip design processes, tools provided by suppliers are required to configure width, depth, bank, mux, type and other parameters of the Memory, so that after proper configuration, a specific Memory is regenerated. Due to the limitations of step, mux, depth, width, etc., the generated Memory is not required to meet the demands of users, the waste of areas is possibly caused, the time sequence is possibly not met, and the use methods and parameters of Memory generating tools provided by different manufacturers are not consistent, so that the Memory is a tedious, error-prone and iteration-prone work for common designers. There is a need for an efficient method for creating, packaging, and integrating Memory work in integrated circuit designs.
Disclosure of Invention
Aiming at the problems existing in the prior art, a Memory integration method of an integrated circuit is provided, project work iteration is reduced by establishing a general Memory demand interface and combining with a minimum area screening idea, and when in packaging, hierarchical packaging is adopted, each layer is used for completing different functional division, so that the method is beneficial to shielding bottom details of Memory technology, suppliers and the like.
The technical scheme adopted by the application is as follows: a Memory integration method of an integrated circuit, comprising:
establishing a general user demand table and an instantiation Memory general interface;
decomposing user demands in a general user demand table, and determining a physical Memory with the smallest total area;
and hierarchical encapsulation is carried out on the Memory through functional division.
As a preferred solution, the general user requirement table forms the requirement characteristics related to the Memory into configuration items, including depth, width, byte write enable, PG enable, redundancy parameters, and type of Memory.
As a preferred scheme, when the Memory universal interface is instantiated, interface signals and parameters are configured, so that the process is irrelevant; and EDA simulation and FPGA verification interfaces are also provided.
As a preferable scheme, the decomposition process is as follows:
s1, aiming at an established user demand table, carrying out split screening treatment on each configuration item according to the sequence of the configuration items;
s2, judging whether a screening result meets the requirement after the splitting and screening of one configuration item are finished, recording the configuration item if the screening result meets the requirement, and simultaneously comparing the configuration item with the previous screening result and recording the optimal configuration item;
s3, traversing all the configuration items in sequence, and if the splitting and screening are successful, recording an optimal result and all the configuration items meeting the conditions; if no satisfied configuration item is found, corresponding resolution screening information is recorded, and the resolution granularity of screening is adjusted in the subsequent process.
As a preferred scheme, the method for adjusting the resolution granularity of the screening comprises the following steps: adjusting width splitting granularity, depth splitting strength, width-to-length ratio and timing margin.
As a preferred solution, in the step S2, the specific method for splitting and screening the configuration items is as follows:
s21, calculating to obtain a minimum splitting base number according to user requirements and depth and width requirements of the configuration item, and calculating a specific splitting table item by combining splitting granularity of the depth and the width;
s22, splitting the splitting table items in sequence, generating corresponding Memory by utilizing the split configuration, calculating whether the Memory time sequence generated by the configuration items is met according to the frequency required by the user, and if so, jumping out the sub-function and entering the next Memory configuration item; if the splitting of the configuration options is completed, the Memory meeting the conditions is not found, the sub-function is also exited, and the next Memory configuration item is entered.
In a preferred embodiment, in the step S22, when the split table entry is split, if the split table entry is configured as a decimal, an upward rounding process is required.
As a preferable scheme, the hierarchical packaging process of the Memory by the function division is as follows:
a first layer: physical layer encapsulation, encapsulating aiming at different physical Memory and shielding physical layer details;
a second layer: and (3) packaging from the physical layer to the user demand layer, and adjusting the split physical Memory into a third layer corresponding to the user demand: instantiating the Memory of the same type through different parameters, and calling the same file module by all the Memory of the same type;
fourth layer: the FPGA and EDA simulation model files are packaged and the macros are defined and separated.
As a preferred solution, automatic gating is added at the time of physical layer encapsulation.
Compared with the prior art, the beneficial effects of adopting the technical scheme are as follows: the method can be used for establishing the top layer of the universal Memory according to different Memory tools of a process and a provider and combining with specific Memory requirements of the project, the bottom layer is shielded, the universal top layer is conveniently and clearly called in the project, the Memory integration efficiency of the project is improved, the comprehensive use of the project in the early verification and later stage is met, and the research and development management level of the integrated circuit project is improved. The application can be applied to all chip development projects.
Drawings
FIG. 1 is a schematic diagram showing a Memory integration method of an integrated circuit according to the present application.
FIG. 2 is a diagram illustrating a specific general user requirement according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar modules or modules having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application. On the contrary, the embodiments of the application include all alternatives, modifications and equivalents as may be included within the spirit and scope of the appended claims.
Aiming at the problems that the Memory generated in the prior art does not necessarily meet the requirements of users, the area waste is possibly caused, the time sequence is possibly not met, and the use methods and parameters of Memory generating tools provided by different manufacturers are not consistent, the embodiment of the application provides a Memory integration method of an integrated circuit, and the Memory integration method is realized by combining the specific Memory requirements of a project, shielding a bottom layer and adopting a top layer of a general Memory, so that the general top layer can be conveniently called in the project, and the Memory integration efficiency of the project is improved. The specific scheme is as follows:
as shown in fig. 1, a Memory integration method of an integrated circuit includes:
establishing a general user demand table and an instantiation Memory general interface;
decomposing user demands in a general user demand table, and determining a physical Memory with the smallest total area;
and hierarchical encapsulation is carried out on the Memory through functional division.
In one embodiment, a generic Memory requirements interface is formed by a generic user requirements table and a Memory generic interface.
The general user requirement table considers most of requirement characteristics of the Memory, including common user characteristics such as depth, width, byte write enable, PG enable, redundancy and the like, and generalizes types of the Memory: SP, DP, TP, ROM, each property is formed into a Memory configuration item. In the actual use process, a user configures a general user demand table according to the self demand, and the table is used as a demand interface of the user to manage the Memory demand of the project. FIG. 2 illustrates a specific general user requirement representation of an intent in one embodiment.
The purpose of defining the user universal interface is mainly to facilitate the use of the user, the universal interface is instantiated by summarizing interface signals and parameters, the process is irrelevant, and meanwhile, the prior EDA simulation and FPGA verification interface is considered, so that the work development verification work can be carried out in the early stage of the project, and the generation of a real Memory is avoided.
After the user demand configuration is completed, in this embodiment, a Memory screening method based on project time sequence requirements is adopted to screen the satisfied Memory, that is, on the basis of satisfying the time sequence requirements, scripts are used to decompose the user demands, and an "bubbling method" is adopted to screen the physical Memory with the smallest total area on the basis of satisfying the time sequence requirements, so as to achieve the purpose of reducing the whole area of the chip, and meanwhile, in the splitting process, the method is not based on a conventional bisection method, but adopts a natural number splitting rule. Based on the minimum area screening idea under time sequence priority, project work iteration can be effectively reduced. Specific:
and traversing all Memory configuration items to find an optimal splitting result according to the user requirements. And carrying out splitting screening treatment on each configuration item according to the sequence of the configuration items, judging the screening result after splitting and screening of one Memory configuration item is finished, recording the configuration item if the screened configuration item meets the requirement, simultaneously comparing the result of the configuration item with the previous screening result, recording the optimal screening result, and simultaneously recording all the configuration items meeting the condition, thereby being convenient for subsequent inquiry and use. If no suitable split configuration item is found, the split screening information of the time is recorded, and the split granularity of screening can be adjusted in the subsequent process. In one embodiment, the method for adjusting the resolution granularity of the screening comprises: adjusting width splitting granularity (thinner splitting), depth splitting strength (thinner splitting), width-to-length ratio, timing margin and the like.
The specific splitting method for the single configuration item comprises the following steps:
calculating a minimum splitting base number according to the user requirement and the depth and width requirements of the configuration item, and calculating a specific splitting table item according to the splitting granularity of the depth and the width on the basis of the minimum splitting base number; splitting the splitting table items in sequence, generating corresponding Memory by utilizing the split configuration, calculating whether the Memory time sequence generated by the configuration items is met according to the frequency required by the user, and if so, jumping out of the sub-function and entering the next Memory configuration item; if the splitting of the configuration options is completed, the Memory meeting the conditions is not found, the sub-function is also exited, and the next Memory configuration item is entered.
This process is further illustrated below with one specific split example:
user configuration parameters (SP, 1024X800, 500M), minimum split radix is calculated for RFSP (type of SP ram, single port Memory of register file) lower compiler (Memory generation tool) configuration items: the 1024X800 needs to be split into 20 memories of 256X160, and the configured Memory information is generated with the following cardinality: depth 1024/256=4 and width 800/160=5.
If the split granularity is configured to be depth 3 and width 2. The depth direction is split to [1024/4 ],
1024/5,1024/7 = [256,204.8,146.28], and the width direction is split into [800/5,800/6] = [160,133.333], so for this configuration item, memory of the following 6 configurations is generated:
memory1 (256,160), memory2 (204.8,160), memory3 (146.28,160), memory4 (256,133.333), memory y5 (204.8,133.333), memory6 (146.28,133.333). In actual processing, the above-mentioned decimal number needs to be rounded up, while taking into consideration the step size step of the depth and width of the Memory.
After the creation of the Memory is completed, encapsulation is required. In this embodiment, a hierarchical encapsulation Memory is proposed, each layer performs different functional division, which is beneficial to shielding the bottom details of the Memory, such as the process, the supplier, etc., and the encapsulation is divided into four layers:
a first layer: and the packaging of the physical layer is carried out aiming at different physical memories, the details of the physical layer are always shielded at the layer, signals with functional significance are extracted, meanwhile, the low power consumption is considered at the layer, the automatic gating is increased, and the power consumption is reduced.
A second layer: and (3) packaging from the physical layer to the user demand layer, and changing the split physical Memory into a Memory corresponding to the user demand.
Third layer: the Memory of the same type is instantiated through different parameters, so that all the Memory of the same type can call the same file module.
Fourth layer: the FPGA and simulation model files are added and separated by macro definition, so that EDA verification or FPGA verification can be conveniently performed by project expansion;
through the four-layer package, details irrelevant to the process and suppliers are shielded, and early work development and early progress of projects are facilitated.
The application can shield the bottom layer realization aiming at Memory tools with different technologies and suppliers and combining the specific Memory demands of the project, thereby realizing the top layer of the universal Memory, facilitating the invoking of the universal top layer in the project, improving the Memory integration efficiency of the project, meeting the comprehensive use of the project in the early verification and later stage, and improving the research and development management level of the integrated circuit project. The application can be applied to all chip development projects.
Example 1
The embodiment provides a Memory integration method of an integrated circuit, which comprises the following steps:
establishing a general user demand table and an instantiation Memory general interface;
decomposing user demands in a general user demand table, and determining a physical Memory with the smallest total area;
and hierarchical encapsulation is carried out on the Memory through functional division.
Example 2
On the basis of embodiment 1, the general user requirement table in this embodiment forms the requirement characteristics related to the Memory into configuration items, including depth, width, byte write enable, PG enable, redundancy parameters, and types of the Memory.
Example 3
On the basis of embodiment 1 or 2, in this embodiment, when the Memory universal interface is instantiated, interface signals and parameters are configured, so that the process is irrelevant; and EDA simulation and FPGA verification interfaces are also provided.
Example 4
On the basis of embodiment 1, the decomposition process in this embodiment is:
s1, aiming at an established user demand table, carrying out split screening treatment on each configuration item according to the sequence of the configuration items;
s2, judging whether a screening result meets the requirement after the splitting and screening of one configuration item are finished, recording the configuration item if the screening result meets the requirement, and simultaneously comparing the configuration item with the previous screening result and recording the optimal configuration item;
s3, traversing all the configuration items in sequence, and if the splitting and screening are successful, recording an optimal result and all the configuration items meeting the conditions; if no satisfied configuration item is found, corresponding resolution screening information is recorded, and the resolution granularity of screening is adjusted in the subsequent process.
Example 5
Based on embodiment 4, the method for adjusting the resolution granularity of the screening in this embodiment includes: adjusting width splitting granularity, depth splitting strength, width-to-length ratio and timing margin.
Example 6
Based on embodiment 4, in step S2 described in this embodiment, the specific method for splitting and screening configuration items is as follows:
s21, calculating to obtain a minimum splitting base number according to user requirements and depth and width requirements of the configuration item, and calculating a specific splitting table item by combining splitting granularity of the depth and the width;
s22, splitting the splitting table items in sequence, generating corresponding Memory by utilizing the split configuration, calculating whether the Memory time sequence generated by the configuration items is met according to the frequency required by the user, and if so, jumping out the sub-function and entering the next Memory configuration item; if the splitting of the configuration options is completed, the Memory meeting the conditions is not found, the sub-function is also exited, and the next Memory configuration item is entered.
Example 7
On the basis of embodiment 6, in step S22 described in this embodiment, when splitting the splitting table entry, if the splitting table entry is configured to be a decimal, then an upward rounding process is required.
Example 8
Based on embodiment 4, the hierarchical encapsulation process for the Memory by the functional division in this embodiment is as follows:
a first layer: physical layer encapsulation, encapsulating aiming at different physical Memory and shielding physical layer details;
a second layer: and (3) packaging from the physical layer to the user demand layer, and adjusting the split physical Memory into a third layer corresponding to the user demand: instantiating the Memory of the same type through different parameters, and calling the same file module by all the Memory of the same type;
fourth layer: the FPGA and EDA simulation model files are packaged and the macros are defined and separated.
Example 9
On the basis of embodiment 8, automatic gating is added during physical layer encapsulation in this embodiment.
The present application can be preferably achieved by the above examples 1 to 9.
It should be noted that, in the description of the embodiments of the present application, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; may be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present application will be understood in detail by those skilled in the art; the accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (9)
1. A Memory integration method of an integrated circuit, comprising:
establishing a general user demand table and an instantiation Memory general interface;
decomposing user demands in a general user demand table, and determining a physical Memory with the smallest total area;
and hierarchical encapsulation is carried out on the Memory through functional division.
2. The Memory integration method of claim 1, wherein the general user requirements table forms the requirements characteristics related to the Memory into configuration items including depth, width, byte write enable, PG enable, redundancy parameters, and type of Memory.
3. The Memory integration method of an integrated circuit according to claim 1 or 2, wherein when a Memory universal interface is instantiated, interface signals and parameters are configured to be independent of a process; and EDA simulation and FPGA verification interfaces are also provided.
4. The Memory integration method of an integrated circuit of claim 1, wherein the decomposition process is:
s1, aiming at an established user demand table, carrying out split screening treatment on each configuration item according to the sequence of the configuration items;
s2, judging whether a screening result meets the requirement after the splitting and screening of one configuration item are finished, recording the configuration item if the screening result meets the requirement, and simultaneously comparing the configuration item with the previous screening result and recording the optimal configuration item;
s3, traversing all the configuration items in sequence, and if the splitting and screening are successful, recording an optimal result and all the configuration items meeting the conditions; if no satisfied configuration item is found, corresponding resolution screening information is recorded, and the resolution granularity of screening is adjusted in the subsequent process.
5. The Memory integration method of an integrated circuit of claim 4, wherein the adjusting the resolution granularity of the filtering method comprises: adjusting width splitting granularity, depth splitting strength, width-to-length ratio and timing margin.
6. The Memory integration method of an integrated circuit according to claim 4 or 5, wherein in the step S2, the specific method of configuration item splitting and filtering is as follows:
s21, calculating to obtain a minimum splitting base number according to user requirements and depth and width requirements of the configuration item, and calculating a specific splitting table item by combining splitting granularity of the depth and the width;
s22, splitting the splitting table items in sequence, generating corresponding Memory by utilizing the split configuration, calculating whether the Memory time sequence generated by the configuration items is met according to the frequency required by the user, and if so, jumping out the sub-function and entering the next Memory configuration item; if the splitting of the configuration options is completed, the Memory meeting the conditions is not found, the sub-function is also exited, and the next Memory configuration item is entered.
7. The Memory integration method of the integrated circuit according to claim 6, wherein in the step S22, when the splitting table entry is split, if the split configuration is a decimal, then a rounding-up process is required.
8.The Memory integration method of an integrated circuit of claim 4, wherein the pass-through functionThe hierarchical packaging process of the Memory comprises the following steps of:
a first layer: physical layer encapsulation, encapsulating aiming at different physical Memory and shielding physical layer details;
a second layer: and (3) packaging from the physical layer to the user demand layer, and adjusting the split physical Memory into a third layer corresponding to the user demand: instantiating the Memory of the same type through different parameters, and calling the same file module by all the Memory of the same type;
fourth layer: the FPGA and EDA simulation model files are packaged and the macros are defined and separated.
9. The Memory integration method of an integrated circuit of claim 8, wherein automatic gating is added at physical layer packaging.
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